2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include "mlx5_ifc_fpga.h"
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
77 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4,
81 MLX5_SHARED_RESOURCE_UID = 0xffff,
85 MLX5_OBJ_TYPE_SW_ICM = 0x0008,
89 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
90 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
91 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
95 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
96 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
97 MLX5_OBJ_TYPE_MKEY = 0xff01,
98 MLX5_OBJ_TYPE_QP = 0xff02,
99 MLX5_OBJ_TYPE_PSV = 0xff03,
100 MLX5_OBJ_TYPE_RMP = 0xff04,
101 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
102 MLX5_OBJ_TYPE_RQ = 0xff06,
103 MLX5_OBJ_TYPE_SQ = 0xff07,
104 MLX5_OBJ_TYPE_TIR = 0xff08,
105 MLX5_OBJ_TYPE_TIS = 0xff09,
106 MLX5_OBJ_TYPE_DCT = 0xff0a,
107 MLX5_OBJ_TYPE_XRQ = 0xff0b,
108 MLX5_OBJ_TYPE_RQT = 0xff0e,
109 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
110 MLX5_OBJ_TYPE_CQ = 0xff10,
114 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
115 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
116 MLX5_CMD_OP_INIT_HCA = 0x102,
117 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
118 MLX5_CMD_OP_ENABLE_HCA = 0x104,
119 MLX5_CMD_OP_DISABLE_HCA = 0x105,
120 MLX5_CMD_OP_QUERY_PAGES = 0x107,
121 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
122 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
123 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
124 MLX5_CMD_OP_SET_ISSI = 0x10b,
125 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
126 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
127 MLX5_CMD_OP_ALLOC_SF = 0x113,
128 MLX5_CMD_OP_DEALLOC_SF = 0x114,
129 MLX5_CMD_OP_CREATE_MKEY = 0x200,
130 MLX5_CMD_OP_QUERY_MKEY = 0x201,
131 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
132 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
133 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
134 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
135 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
136 MLX5_CMD_OP_CREATE_EQ = 0x301,
137 MLX5_CMD_OP_DESTROY_EQ = 0x302,
138 MLX5_CMD_OP_QUERY_EQ = 0x303,
139 MLX5_CMD_OP_GEN_EQE = 0x304,
140 MLX5_CMD_OP_CREATE_CQ = 0x400,
141 MLX5_CMD_OP_DESTROY_CQ = 0x401,
142 MLX5_CMD_OP_QUERY_CQ = 0x402,
143 MLX5_CMD_OP_MODIFY_CQ = 0x403,
144 MLX5_CMD_OP_CREATE_QP = 0x500,
145 MLX5_CMD_OP_DESTROY_QP = 0x501,
146 MLX5_CMD_OP_RST2INIT_QP = 0x502,
147 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
148 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
149 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
150 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
151 MLX5_CMD_OP_2ERR_QP = 0x507,
152 MLX5_CMD_OP_2RST_QP = 0x50a,
153 MLX5_CMD_OP_QUERY_QP = 0x50b,
154 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
155 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
156 MLX5_CMD_OP_CREATE_PSV = 0x600,
157 MLX5_CMD_OP_DESTROY_PSV = 0x601,
158 MLX5_CMD_OP_CREATE_SRQ = 0x700,
159 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
160 MLX5_CMD_OP_QUERY_SRQ = 0x702,
161 MLX5_CMD_OP_ARM_RQ = 0x703,
162 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
163 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
164 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
165 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
166 MLX5_CMD_OP_CREATE_DCT = 0x710,
167 MLX5_CMD_OP_DESTROY_DCT = 0x711,
168 MLX5_CMD_OP_DRAIN_DCT = 0x712,
169 MLX5_CMD_OP_QUERY_DCT = 0x713,
170 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
171 MLX5_CMD_OP_CREATE_XRQ = 0x717,
172 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
173 MLX5_CMD_OP_QUERY_XRQ = 0x719,
174 MLX5_CMD_OP_ARM_XRQ = 0x71a,
175 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
176 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
177 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
178 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729,
179 MLX5_CMD_OP_MODIFY_XRQ = 0x72a,
180 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
181 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
182 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
183 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
184 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
185 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
186 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
187 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
188 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
189 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
190 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
191 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
192 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
193 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
194 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
195 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
196 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
197 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
198 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
199 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
200 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
201 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
202 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
203 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
204 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
205 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
206 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
207 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
208 MLX5_CMD_OP_ALLOC_PD = 0x800,
209 MLX5_CMD_OP_DEALLOC_PD = 0x801,
210 MLX5_CMD_OP_ALLOC_UAR = 0x802,
211 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
212 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
213 MLX5_CMD_OP_ACCESS_REG = 0x805,
214 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
215 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
216 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
217 MLX5_CMD_OP_MAD_IFC = 0x50d,
218 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
219 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
220 MLX5_CMD_OP_NOP = 0x80d,
221 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
222 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
223 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
224 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
225 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
226 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
227 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
228 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
229 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
230 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
231 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
232 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
233 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
234 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
235 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
236 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
237 MLX5_CMD_OP_CREATE_LAG = 0x840,
238 MLX5_CMD_OP_MODIFY_LAG = 0x841,
239 MLX5_CMD_OP_QUERY_LAG = 0x842,
240 MLX5_CMD_OP_DESTROY_LAG = 0x843,
241 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
242 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
243 MLX5_CMD_OP_CREATE_TIR = 0x900,
244 MLX5_CMD_OP_MODIFY_TIR = 0x901,
245 MLX5_CMD_OP_DESTROY_TIR = 0x902,
246 MLX5_CMD_OP_QUERY_TIR = 0x903,
247 MLX5_CMD_OP_CREATE_SQ = 0x904,
248 MLX5_CMD_OP_MODIFY_SQ = 0x905,
249 MLX5_CMD_OP_DESTROY_SQ = 0x906,
250 MLX5_CMD_OP_QUERY_SQ = 0x907,
251 MLX5_CMD_OP_CREATE_RQ = 0x908,
252 MLX5_CMD_OP_MODIFY_RQ = 0x909,
253 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
254 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
255 MLX5_CMD_OP_QUERY_RQ = 0x90b,
256 MLX5_CMD_OP_CREATE_RMP = 0x90c,
257 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
258 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
259 MLX5_CMD_OP_QUERY_RMP = 0x90f,
260 MLX5_CMD_OP_CREATE_TIS = 0x912,
261 MLX5_CMD_OP_MODIFY_TIS = 0x913,
262 MLX5_CMD_OP_DESTROY_TIS = 0x914,
263 MLX5_CMD_OP_QUERY_TIS = 0x915,
264 MLX5_CMD_OP_CREATE_RQT = 0x916,
265 MLX5_CMD_OP_MODIFY_RQT = 0x917,
266 MLX5_CMD_OP_DESTROY_RQT = 0x918,
267 MLX5_CMD_OP_QUERY_RQT = 0x919,
268 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
269 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
270 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
271 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
272 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
273 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
274 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
275 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
276 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
277 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
278 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
279 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
280 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
281 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
282 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
283 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
284 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
285 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
286 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
287 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
288 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
289 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
290 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
291 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
292 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
293 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
294 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
295 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
296 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
297 MLX5_CMD_OP_CREATE_UCTX = 0xa04,
298 MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
299 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
300 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
301 MLX5_CMD_OP_SYNC_STEERING = 0xb00,
305 /* Valid range for general commands that don't work over an object */
307 MLX5_CMD_OP_GENERAL_START = 0xb00,
308 MLX5_CMD_OP_GENERAL_END = 0xd00,
311 struct mlx5_ifc_flow_table_fields_supported_bits {
314 u8 outer_ether_type[0x1];
315 u8 outer_ip_version[0x1];
316 u8 outer_first_prio[0x1];
317 u8 outer_first_cfi[0x1];
318 u8 outer_first_vid[0x1];
319 u8 outer_ipv4_ttl[0x1];
320 u8 outer_second_prio[0x1];
321 u8 outer_second_cfi[0x1];
322 u8 outer_second_vid[0x1];
323 u8 reserved_at_b[0x1];
327 u8 outer_ip_protocol[0x1];
328 u8 outer_ip_ecn[0x1];
329 u8 outer_ip_dscp[0x1];
330 u8 outer_udp_sport[0x1];
331 u8 outer_udp_dport[0x1];
332 u8 outer_tcp_sport[0x1];
333 u8 outer_tcp_dport[0x1];
334 u8 outer_tcp_flags[0x1];
335 u8 outer_gre_protocol[0x1];
336 u8 outer_gre_key[0x1];
337 u8 outer_vxlan_vni[0x1];
338 u8 outer_geneve_vni[0x1];
339 u8 outer_geneve_oam[0x1];
340 u8 outer_geneve_protocol_type[0x1];
341 u8 outer_geneve_opt_len[0x1];
342 u8 reserved_at_1e[0x1];
343 u8 source_eswitch_port[0x1];
347 u8 inner_ether_type[0x1];
348 u8 inner_ip_version[0x1];
349 u8 inner_first_prio[0x1];
350 u8 inner_first_cfi[0x1];
351 u8 inner_first_vid[0x1];
352 u8 reserved_at_27[0x1];
353 u8 inner_second_prio[0x1];
354 u8 inner_second_cfi[0x1];
355 u8 inner_second_vid[0x1];
356 u8 reserved_at_2b[0x1];
360 u8 inner_ip_protocol[0x1];
361 u8 inner_ip_ecn[0x1];
362 u8 inner_ip_dscp[0x1];
363 u8 inner_udp_sport[0x1];
364 u8 inner_udp_dport[0x1];
365 u8 inner_tcp_sport[0x1];
366 u8 inner_tcp_dport[0x1];
367 u8 inner_tcp_flags[0x1];
368 u8 reserved_at_37[0x9];
370 u8 geneve_tlv_option_0_data[0x1];
371 u8 reserved_at_41[0x4];
372 u8 outer_first_mpls_over_udp[0x4];
373 u8 outer_first_mpls_over_gre[0x4];
374 u8 inner_first_mpls[0x4];
375 u8 outer_first_mpls[0x4];
376 u8 reserved_at_55[0x2];
377 u8 outer_esp_spi[0x1];
378 u8 reserved_at_58[0x2];
380 u8 reserved_at_5b[0x5];
382 u8 reserved_at_60[0x18];
383 u8 metadata_reg_c_7[0x1];
384 u8 metadata_reg_c_6[0x1];
385 u8 metadata_reg_c_5[0x1];
386 u8 metadata_reg_c_4[0x1];
387 u8 metadata_reg_c_3[0x1];
388 u8 metadata_reg_c_2[0x1];
389 u8 metadata_reg_c_1[0x1];
390 u8 metadata_reg_c_0[0x1];
393 struct mlx5_ifc_flow_table_prop_layout_bits {
395 u8 reserved_at_1[0x1];
396 u8 flow_counter[0x1];
397 u8 flow_modify_en[0x1];
399 u8 identified_miss_table_mode[0x1];
400 u8 flow_table_modify[0x1];
403 u8 reserved_at_9[0x1];
406 u8 reserved_at_c[0x1];
409 u8 reformat_and_vlan_action[0x1];
410 u8 reserved_at_10[0x1];
412 u8 reformat_l3_tunnel_to_l2[0x1];
413 u8 reformat_l2_to_l3_tunnel[0x1];
414 u8 reformat_and_modify_action[0x1];
415 u8 ignore_flow_level[0x1];
416 u8 reserved_at_16[0x1];
417 u8 table_miss_action_domain[0x1];
418 u8 termination_table[0x1];
419 u8 reformat_and_fwd_to_table[0x1];
420 u8 reserved_at_1a[0x2];
421 u8 ipsec_encrypt[0x1];
422 u8 ipsec_decrypt[0x1];
424 u8 reserved_at_1f[0x1];
426 u8 termination_table_raw_traffic[0x1];
427 u8 reserved_at_21[0x1];
428 u8 log_max_ft_size[0x6];
429 u8 log_max_modify_header_context[0x8];
430 u8 max_modify_header_actions[0x8];
431 u8 max_ft_level[0x8];
433 u8 reserved_at_40[0x20];
435 u8 reserved_at_60[0x18];
436 u8 log_max_ft_num[0x8];
438 u8 reserved_at_80[0x18];
439 u8 log_max_destination[0x8];
441 u8 log_max_flow_counter[0x8];
442 u8 reserved_at_a8[0x10];
443 u8 log_max_flow[0x8];
445 u8 reserved_at_c0[0x40];
447 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
449 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
452 struct mlx5_ifc_odp_per_transport_service_cap_bits {
459 u8 reserved_at_6[0x1a];
462 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
487 u8 reserved_at_c0[0x18];
488 u8 ttl_hoplimit[0x8];
493 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
495 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
498 struct mlx5_ifc_nvgre_key_bits {
503 union mlx5_ifc_gre_key_bits {
504 struct mlx5_ifc_nvgre_key_bits nvgre;
508 struct mlx5_ifc_fte_match_set_misc_bits {
509 u8 gre_c_present[0x1];
510 u8 reserved_at_1[0x1];
511 u8 gre_k_present[0x1];
512 u8 gre_s_present[0x1];
513 u8 source_vhca_port[0x4];
516 u8 source_eswitch_owner_vhca_id[0x10];
517 u8 source_port[0x10];
519 u8 outer_second_prio[0x3];
520 u8 outer_second_cfi[0x1];
521 u8 outer_second_vid[0xc];
522 u8 inner_second_prio[0x3];
523 u8 inner_second_cfi[0x1];
524 u8 inner_second_vid[0xc];
526 u8 outer_second_cvlan_tag[0x1];
527 u8 inner_second_cvlan_tag[0x1];
528 u8 outer_second_svlan_tag[0x1];
529 u8 inner_second_svlan_tag[0x1];
530 u8 reserved_at_64[0xc];
531 u8 gre_protocol[0x10];
533 union mlx5_ifc_gre_key_bits gre_key;
536 u8 reserved_at_b8[0x8];
539 u8 reserved_at_d8[0x7];
542 u8 reserved_at_e0[0xc];
543 u8 outer_ipv6_flow_label[0x14];
545 u8 reserved_at_100[0xc];
546 u8 inner_ipv6_flow_label[0x14];
548 u8 reserved_at_120[0xa];
549 u8 geneve_opt_len[0x6];
550 u8 geneve_protocol_type[0x10];
552 u8 reserved_at_140[0x8];
554 u8 reserved_at_160[0x20];
555 u8 outer_esp_spi[0x20];
556 u8 reserved_at_1a0[0x60];
559 struct mlx5_ifc_fte_match_mpls_bits {
566 struct mlx5_ifc_fte_match_set_misc2_bits {
567 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
569 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
571 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
573 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
575 u8 metadata_reg_c_7[0x20];
577 u8 metadata_reg_c_6[0x20];
579 u8 metadata_reg_c_5[0x20];
581 u8 metadata_reg_c_4[0x20];
583 u8 metadata_reg_c_3[0x20];
585 u8 metadata_reg_c_2[0x20];
587 u8 metadata_reg_c_1[0x20];
589 u8 metadata_reg_c_0[0x20];
591 u8 metadata_reg_a[0x20];
593 u8 reserved_at_1a0[0x60];
596 struct mlx5_ifc_fte_match_set_misc3_bits {
597 u8 inner_tcp_seq_num[0x20];
599 u8 outer_tcp_seq_num[0x20];
601 u8 inner_tcp_ack_num[0x20];
603 u8 outer_tcp_ack_num[0x20];
605 u8 reserved_at_80[0x8];
606 u8 outer_vxlan_gpe_vni[0x18];
608 u8 outer_vxlan_gpe_next_protocol[0x8];
609 u8 outer_vxlan_gpe_flags[0x8];
610 u8 reserved_at_b0[0x10];
612 u8 icmp_header_data[0x20];
614 u8 icmpv6_header_data[0x20];
621 u8 geneve_tlv_option_0_data[0x20];
623 u8 reserved_at_140[0xc0];
626 struct mlx5_ifc_cmd_pas_bits {
630 u8 reserved_at_34[0xc];
633 struct mlx5_ifc_uint64_bits {
640 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
641 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
642 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
643 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
644 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
645 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
646 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
647 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
648 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
649 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
652 struct mlx5_ifc_ads_bits {
655 u8 reserved_at_2[0xe];
658 u8 reserved_at_20[0x8];
664 u8 reserved_at_45[0x3];
665 u8 src_addr_index[0x8];
666 u8 reserved_at_50[0x4];
670 u8 reserved_at_60[0x4];
674 u8 rgid_rip[16][0x8];
676 u8 reserved_at_100[0x4];
679 u8 reserved_at_106[0x1];
688 u8 vhca_port_num[0x8];
694 struct mlx5_ifc_flow_table_nic_cap_bits {
695 u8 nic_rx_multi_path_tirs[0x1];
696 u8 nic_rx_multi_path_tirs_fts[0x1];
697 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
698 u8 reserved_at_3[0x4];
699 u8 sw_owner_reformat_supported[0x1];
700 u8 reserved_at_8[0x18];
702 u8 encap_general_header[0x1];
703 u8 reserved_at_21[0xa];
704 u8 log_max_packet_reformat_context[0x5];
705 u8 reserved_at_30[0x6];
706 u8 max_encap_header_size[0xa];
707 u8 reserved_at_40[0x1c0];
709 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
711 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
713 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
715 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
717 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
719 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
721 u8 reserved_at_e00[0x1200];
723 u8 sw_steering_nic_rx_action_drop_icm_address[0x40];
725 u8 sw_steering_nic_tx_action_drop_icm_address[0x40];
727 u8 sw_steering_nic_tx_action_allow_icm_address[0x40];
729 u8 reserved_at_20c0[0x5f40];
733 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
734 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
735 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
736 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
737 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
738 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
739 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
740 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
743 struct mlx5_ifc_flow_table_eswitch_cap_bits {
744 u8 fdb_to_vport_reg_c_id[0x8];
745 u8 reserved_at_8[0xd];
746 u8 fdb_modify_header_fwd_to_table[0x1];
747 u8 reserved_at_16[0x1];
749 u8 reserved_at_18[0x2];
750 u8 multi_fdb_encap[0x1];
751 u8 egress_acl_forward_to_vport[0x1];
752 u8 fdb_multi_path_to_table[0x1];
753 u8 reserved_at_1d[0x3];
755 u8 reserved_at_20[0x1e0];
757 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
759 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
761 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
763 u8 reserved_at_800[0x1000];
765 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40];
767 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40];
769 u8 sw_steering_uplink_icm_address_rx[0x40];
771 u8 sw_steering_uplink_icm_address_tx[0x40];
773 u8 reserved_at_1900[0x6700];
777 MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
778 MLX5_COUNTER_FLOW_ESWITCH = 0x1,
781 struct mlx5_ifc_e_switch_cap_bits {
782 u8 vport_svlan_strip[0x1];
783 u8 vport_cvlan_strip[0x1];
784 u8 vport_svlan_insert[0x1];
785 u8 vport_cvlan_insert_if_not_exist[0x1];
786 u8 vport_cvlan_insert_overwrite[0x1];
787 u8 reserved_at_5[0x3];
788 u8 esw_uplink_ingress_acl[0x1];
789 u8 reserved_at_9[0x10];
790 u8 esw_functions_changed[0x1];
791 u8 reserved_at_1a[0x1];
792 u8 ecpf_vport_exists[0x1];
793 u8 counter_eswitch_affinity[0x1];
794 u8 merged_eswitch[0x1];
795 u8 nic_vport_node_guid_modify[0x1];
796 u8 nic_vport_port_guid_modify[0x1];
798 u8 vxlan_encap_decap[0x1];
799 u8 nvgre_encap_decap[0x1];
800 u8 reserved_at_22[0x1];
801 u8 log_max_fdb_encap_uplink[0x5];
802 u8 reserved_at_21[0x3];
803 u8 log_max_packet_reformat_context[0x5];
805 u8 max_encap_header_size[0xa];
807 u8 reserved_at_40[0xb];
808 u8 log_max_esw_sf[0x5];
809 u8 esw_sf_base_id[0x10];
811 u8 reserved_at_60[0x7a0];
815 struct mlx5_ifc_qos_cap_bits {
816 u8 packet_pacing[0x1];
817 u8 esw_scheduling[0x1];
818 u8 esw_bw_share[0x1];
819 u8 esw_rate_limit[0x1];
820 u8 reserved_at_4[0x1];
821 u8 packet_pacing_burst_bound[0x1];
822 u8 packet_pacing_typical_size[0x1];
823 u8 reserved_at_7[0x4];
824 u8 packet_pacing_uid[0x1];
825 u8 reserved_at_c[0x14];
827 u8 reserved_at_20[0x20];
829 u8 packet_pacing_max_rate[0x20];
831 u8 packet_pacing_min_rate[0x20];
833 u8 reserved_at_80[0x10];
834 u8 packet_pacing_rate_table_size[0x10];
836 u8 esw_element_type[0x10];
837 u8 esw_tsar_type[0x10];
839 u8 reserved_at_c0[0x10];
840 u8 max_qos_para_vport[0x10];
842 u8 max_tsar_bw_share[0x20];
844 u8 reserved_at_100[0x700];
847 struct mlx5_ifc_debug_cap_bits {
848 u8 core_dump_general[0x1];
849 u8 core_dump_qp[0x1];
850 u8 reserved_at_2[0x7];
851 u8 resource_dump[0x1];
852 u8 reserved_at_a[0x16];
854 u8 reserved_at_20[0x2];
855 u8 stall_detect[0x1];
856 u8 reserved_at_23[0x1d];
858 u8 reserved_at_40[0x7c0];
861 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
865 u8 lro_psh_flag[0x1];
866 u8 lro_time_stamp[0x1];
867 u8 reserved_at_5[0x2];
868 u8 wqe_vlan_insert[0x1];
869 u8 self_lb_en_modifiable[0x1];
870 u8 reserved_at_9[0x2];
872 u8 multi_pkt_send_wqe[0x2];
873 u8 wqe_inline_mode[0x2];
874 u8 rss_ind_tbl_cap[0x4];
877 u8 enhanced_multi_pkt_send_wqe[0x1];
878 u8 tunnel_lso_const_out_ip_id[0x1];
879 u8 reserved_at_1c[0x2];
880 u8 tunnel_stateless_gre[0x1];
881 u8 tunnel_stateless_vxlan[0x1];
886 u8 cqe_checksum_full[0x1];
887 u8 tunnel_stateless_geneve_tx[0x1];
888 u8 tunnel_stateless_mpls_over_udp[0x1];
889 u8 tunnel_stateless_mpls_over_gre[0x1];
890 u8 tunnel_stateless_vxlan_gpe[0x1];
891 u8 tunnel_stateless_ipv4_over_vxlan[0x1];
892 u8 tunnel_stateless_ip_over_ip[0x1];
893 u8 insert_trailer[0x1];
894 u8 reserved_at_2b[0x5];
895 u8 max_vxlan_udp_ports[0x8];
896 u8 reserved_at_38[0x6];
897 u8 max_geneve_opt_len[0x1];
898 u8 tunnel_stateless_geneve_rx[0x1];
900 u8 reserved_at_40[0x10];
901 u8 lro_min_mss_size[0x10];
903 u8 reserved_at_60[0x120];
905 u8 lro_timer_supported_periods[4][0x20];
907 u8 reserved_at_200[0x600];
910 struct mlx5_ifc_roce_cap_bits {
912 u8 reserved_at_1[0x3];
913 u8 sw_r_roce_src_udp_port[0x1];
914 u8 reserved_at_5[0x1b];
916 u8 reserved_at_20[0x60];
918 u8 reserved_at_80[0xc];
920 u8 reserved_at_90[0x8];
921 u8 roce_version[0x8];
923 u8 reserved_at_a0[0x10];
924 u8 r_roce_dest_udp_port[0x10];
926 u8 r_roce_max_src_udp_port[0x10];
927 u8 r_roce_min_src_udp_port[0x10];
929 u8 reserved_at_e0[0x10];
930 u8 roce_address_table_size[0x10];
932 u8 reserved_at_100[0x700];
935 struct mlx5_ifc_sync_steering_in_bits {
939 u8 reserved_at_20[0x10];
942 u8 reserved_at_40[0xc0];
945 struct mlx5_ifc_sync_steering_out_bits {
947 u8 reserved_at_8[0x18];
951 u8 reserved_at_40[0x40];
954 struct mlx5_ifc_device_mem_cap_bits {
956 u8 reserved_at_1[0x1f];
958 u8 reserved_at_20[0xb];
959 u8 log_min_memic_alloc_size[0x5];
960 u8 reserved_at_30[0x8];
961 u8 log_max_memic_addr_alignment[0x8];
963 u8 memic_bar_start_addr[0x40];
965 u8 memic_bar_size[0x20];
967 u8 max_memic_size[0x20];
969 u8 steering_sw_icm_start_address[0x40];
971 u8 reserved_at_100[0x8];
972 u8 log_header_modify_sw_icm_size[0x8];
973 u8 reserved_at_110[0x2];
974 u8 log_sw_icm_alloc_granularity[0x6];
975 u8 log_steering_sw_icm_size[0x8];
977 u8 reserved_at_120[0x20];
979 u8 header_modify_sw_icm_start_address[0x40];
981 u8 reserved_at_180[0x680];
984 struct mlx5_ifc_device_event_cap_bits {
985 u8 user_affiliated_events[4][0x40];
987 u8 user_unaffiliated_events[4][0x40];
990 struct mlx5_ifc_virtio_emulation_cap_bits {
991 u8 desc_tunnel_offload_type[0x1];
992 u8 eth_frame_offload_type[0x1];
993 u8 virtio_version_1_0[0x1];
994 u8 device_features_bits_mask[0xd];
996 u8 virtio_queue_type[0x8];
998 u8 max_tunnel_desc[0x10];
999 u8 reserved_at_30[0x3];
1000 u8 log_doorbell_stride[0x5];
1001 u8 reserved_at_38[0x3];
1002 u8 log_doorbell_bar_size[0x5];
1004 u8 doorbell_bar_offset[0x40];
1006 u8 max_emulated_devices[0x8];
1007 u8 max_num_virtio_queues[0x18];
1009 u8 reserved_at_a0[0x60];
1011 u8 umem_1_buffer_param_a[0x20];
1013 u8 umem_1_buffer_param_b[0x20];
1015 u8 umem_2_buffer_param_a[0x20];
1017 u8 umem_2_buffer_param_b[0x20];
1019 u8 umem_3_buffer_param_a[0x20];
1021 u8 umem_3_buffer_param_b[0x20];
1023 u8 reserved_at_1c0[0x640];
1027 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
1028 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
1029 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
1030 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
1031 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
1032 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
1033 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
1034 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
1035 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
1039 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
1040 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
1041 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
1042 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
1043 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
1044 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
1045 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
1046 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
1047 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
1050 struct mlx5_ifc_atomic_caps_bits {
1051 u8 reserved_at_0[0x40];
1053 u8 atomic_req_8B_endianness_mode[0x2];
1054 u8 reserved_at_42[0x4];
1055 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
1057 u8 reserved_at_47[0x19];
1059 u8 reserved_at_60[0x20];
1061 u8 reserved_at_80[0x10];
1062 u8 atomic_operations[0x10];
1064 u8 reserved_at_a0[0x10];
1065 u8 atomic_size_qp[0x10];
1067 u8 reserved_at_c0[0x10];
1068 u8 atomic_size_dc[0x10];
1070 u8 reserved_at_e0[0x720];
1073 struct mlx5_ifc_odp_cap_bits {
1074 u8 reserved_at_0[0x40];
1077 u8 reserved_at_41[0x1f];
1079 u8 reserved_at_60[0x20];
1081 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1083 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1085 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1087 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1089 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1091 u8 reserved_at_120[0x6E0];
1094 struct mlx5_ifc_calc_op {
1095 u8 reserved_at_0[0x10];
1096 u8 reserved_at_10[0x9];
1097 u8 op_swap_endianness[0x1];
1106 struct mlx5_ifc_vector_calc_cap_bits {
1107 u8 calc_matrix[0x1];
1108 u8 reserved_at_1[0x1f];
1109 u8 reserved_at_20[0x8];
1110 u8 max_vec_count[0x8];
1111 u8 reserved_at_30[0xd];
1112 u8 max_chunk_size[0x3];
1113 struct mlx5_ifc_calc_op calc0;
1114 struct mlx5_ifc_calc_op calc1;
1115 struct mlx5_ifc_calc_op calc2;
1116 struct mlx5_ifc_calc_op calc3;
1118 u8 reserved_at_c0[0x720];
1121 struct mlx5_ifc_tls_cap_bits {
1122 u8 tls_1_2_aes_gcm_128[0x1];
1123 u8 tls_1_3_aes_gcm_128[0x1];
1124 u8 tls_1_2_aes_gcm_256[0x1];
1125 u8 tls_1_3_aes_gcm_256[0x1];
1126 u8 reserved_at_4[0x1c];
1128 u8 reserved_at_20[0x7e0];
1131 struct mlx5_ifc_ipsec_cap_bits {
1132 u8 ipsec_full_offload[0x1];
1133 u8 ipsec_crypto_offload[0x1];
1135 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1136 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1137 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1138 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1139 u8 reserved_at_7[0x4];
1140 u8 log_max_ipsec_offload[0x5];
1141 u8 reserved_at_10[0x10];
1143 u8 min_log_ipsec_full_replay_window[0x8];
1144 u8 max_log_ipsec_full_replay_window[0x8];
1145 u8 reserved_at_30[0x7d0];
1149 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1150 MLX5_WQ_TYPE_CYCLIC = 0x1,
1151 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1152 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1156 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1157 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1161 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1162 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1163 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1164 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1165 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1169 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1170 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1171 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1172 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1173 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1174 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1178 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1179 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1183 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1184 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1185 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1189 MLX5_CAP_PORT_TYPE_IB = 0x0,
1190 MLX5_CAP_PORT_TYPE_ETH = 0x1,
1194 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
1195 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
1196 MLX5_CAP_UMR_FENCE_NONE = 0x2,
1200 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3,
1201 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7,
1202 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8,
1203 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9,
1207 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1208 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1211 #define MLX5_FC_BULK_SIZE_FACTOR 128
1213 enum mlx5_fc_bulk_alloc_bitmask {
1214 MLX5_FC_BULK_128 = (1 << 0),
1215 MLX5_FC_BULK_256 = (1 << 1),
1216 MLX5_FC_BULK_512 = (1 << 2),
1217 MLX5_FC_BULK_1024 = (1 << 3),
1218 MLX5_FC_BULK_2048 = (1 << 4),
1219 MLX5_FC_BULK_4096 = (1 << 5),
1220 MLX5_FC_BULK_8192 = (1 << 6),
1221 MLX5_FC_BULK_16384 = (1 << 7),
1224 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1226 struct mlx5_ifc_cmd_hca_cap_bits {
1227 u8 reserved_at_0[0x30];
1230 u8 reserved_at_40[0x40];
1232 u8 log_max_srq_sz[0x8];
1233 u8 log_max_qp_sz[0x8];
1235 u8 reserved_at_91[0x7];
1236 u8 prio_tag_required[0x1];
1237 u8 reserved_at_99[0x2];
1240 u8 reserved_at_a0[0x3];
1241 u8 ece_support[0x1];
1242 u8 reserved_at_a4[0x7];
1243 u8 log_max_srq[0x5];
1244 u8 reserved_at_b0[0x10];
1246 u8 max_sgl_for_optimized_performance[0x8];
1247 u8 log_max_cq_sz[0x8];
1248 u8 relaxed_ordering_write_umr[0x1];
1249 u8 relaxed_ordering_read_umr[0x1];
1250 u8 reserved_at_d2[0x7];
1251 u8 virtio_net_device_emualtion_manager[0x1];
1252 u8 virtio_blk_device_emualtion_manager[0x1];
1255 u8 log_max_eq_sz[0x8];
1256 u8 relaxed_ordering_write[0x1];
1257 u8 relaxed_ordering_read[0x1];
1258 u8 log_max_mkey[0x6];
1259 u8 reserved_at_f0[0x8];
1260 u8 dump_fill_mkey[0x1];
1261 u8 reserved_at_f9[0x2];
1262 u8 fast_teardown[0x1];
1265 u8 max_indirection[0x8];
1266 u8 fixed_buffer_size[0x1];
1267 u8 log_max_mrw_sz[0x7];
1268 u8 force_teardown[0x1];
1269 u8 reserved_at_111[0x1];
1270 u8 log_max_bsf_list_size[0x6];
1271 u8 umr_extended_translation_offset[0x1];
1273 u8 log_max_klm_list_size[0x6];
1275 u8 reserved_at_120[0xa];
1276 u8 log_max_ra_req_dc[0x6];
1277 u8 reserved_at_130[0xa];
1278 u8 log_max_ra_res_dc[0x6];
1280 u8 reserved_at_140[0x6];
1281 u8 release_all_pages[0x1];
1282 u8 reserved_at_147[0x2];
1284 u8 log_max_ra_req_qp[0x6];
1285 u8 reserved_at_150[0xa];
1286 u8 log_max_ra_res_qp[0x6];
1289 u8 cc_query_allowed[0x1];
1290 u8 cc_modify_allowed[0x1];
1292 u8 cache_line_128byte[0x1];
1293 u8 reserved_at_165[0x4];
1294 u8 rts2rts_qp_counters_set_id[0x1];
1295 u8 reserved_at_16a[0x2];
1296 u8 vnic_env_int_rq_oob[0x1];
1298 u8 reserved_at_16e[0x1];
1300 u8 gid_table_size[0x10];
1302 u8 out_of_seq_cnt[0x1];
1303 u8 vport_counters[0x1];
1304 u8 retransmission_q_counters[0x1];
1306 u8 modify_rq_counter_set_id[0x1];
1307 u8 rq_delay_drop[0x1];
1309 u8 pkey_table_size[0x10];
1311 u8 vport_group_manager[0x1];
1312 u8 vhca_group_manager[0x1];
1315 u8 vnic_env_queue_counters[0x1];
1317 u8 nic_flow_table[0x1];
1318 u8 eswitch_manager[0x1];
1319 u8 device_memory[0x1];
1322 u8 local_ca_ack_delay[0x5];
1323 u8 port_module_event[0x1];
1324 u8 enhanced_error_q_counters[0x1];
1325 u8 ports_check[0x1];
1326 u8 reserved_at_1b3[0x1];
1327 u8 disable_link_up[0x1];
1332 u8 reserved_at_1c0[0x1];
1335 u8 log_max_msg[0x5];
1336 u8 reserved_at_1c8[0x4];
1338 u8 temp_warn_event[0x1];
1340 u8 general_notification_event[0x1];
1341 u8 reserved_at_1d3[0x2];
1345 u8 reserved_at_1d8[0x1];
1354 u8 stat_rate_support[0x10];
1355 u8 reserved_at_1f0[0x1];
1356 u8 pci_sync_for_fw_update_event[0x1];
1357 u8 reserved_at_1f2[0x6];
1358 u8 init2_lag_tx_port_affinity[0x1];
1359 u8 reserved_at_1fa[0x3];
1360 u8 cqe_version[0x4];
1362 u8 compact_address_vector[0x1];
1363 u8 striding_rq[0x1];
1364 u8 reserved_at_202[0x1];
1365 u8 ipoib_enhanced_offloads[0x1];
1366 u8 ipoib_basic_offloads[0x1];
1367 u8 reserved_at_205[0x1];
1368 u8 repeated_block_disabled[0x1];
1369 u8 umr_modify_entity_size_disabled[0x1];
1370 u8 umr_modify_atomic_disabled[0x1];
1371 u8 umr_indirect_mkey_disabled[0x1];
1373 u8 dc_req_scat_data_cqe[0x1];
1374 u8 reserved_at_20d[0x2];
1375 u8 drain_sigerr[0x1];
1376 u8 cmdif_checksum[0x2];
1378 u8 reserved_at_213[0x1];
1379 u8 wq_signature[0x1];
1380 u8 sctr_data_cqe[0x1];
1381 u8 reserved_at_216[0x1];
1387 u8 eth_net_offloads[0x1];
1390 u8 reserved_at_21f[0x1];
1394 u8 cq_moderation[0x1];
1395 u8 reserved_at_223[0x3];
1396 u8 cq_eq_remap[0x1];
1398 u8 block_lb_mc[0x1];
1399 u8 reserved_at_229[0x1];
1400 u8 scqe_break_moderation[0x1];
1401 u8 cq_period_start_from_cqe[0x1];
1403 u8 reserved_at_22d[0x1];
1405 u8 vector_calc[0x1];
1406 u8 umr_ptr_rlky[0x1];
1408 u8 qp_packet_based[0x1];
1409 u8 reserved_at_233[0x3];
1412 u8 set_deth_sqpn[0x1];
1413 u8 reserved_at_239[0x3];
1420 u8 reserved_at_241[0x9];
1422 u8 reserved_at_250[0x8];
1426 u8 driver_version[0x1];
1427 u8 pad_tx_eth_packet[0x1];
1428 u8 reserved_at_263[0x3];
1429 u8 mkey_by_name[0x1];
1430 u8 reserved_at_267[0x4];
1432 u8 log_bf_reg_size[0x5];
1434 u8 reserved_at_270[0x6];
1436 u8 lag_tx_port_affinity[0x1];
1437 u8 reserved_at_279[0x2];
1439 u8 num_lag_ports[0x4];
1441 u8 reserved_at_280[0x10];
1442 u8 max_wqe_sz_sq[0x10];
1444 u8 reserved_at_2a0[0x10];
1445 u8 max_wqe_sz_rq[0x10];
1447 u8 max_flow_counter_31_16[0x10];
1448 u8 max_wqe_sz_sq_dc[0x10];
1450 u8 reserved_at_2e0[0x7];
1451 u8 max_qp_mcg[0x19];
1453 u8 reserved_at_300[0x10];
1454 u8 flow_counter_bulk_alloc[0x8];
1455 u8 log_max_mcg[0x8];
1457 u8 reserved_at_320[0x3];
1458 u8 log_max_transport_domain[0x5];
1459 u8 reserved_at_328[0x3];
1461 u8 reserved_at_330[0xb];
1462 u8 log_max_xrcd[0x5];
1464 u8 nic_receive_steering_discard[0x1];
1465 u8 receive_discard_vport_down[0x1];
1466 u8 transmit_discard_vport_down[0x1];
1467 u8 reserved_at_343[0x5];
1468 u8 log_max_flow_counter_bulk[0x8];
1469 u8 max_flow_counter_15_0[0x10];
1472 u8 reserved_at_360[0x3];
1474 u8 reserved_at_368[0x3];
1476 u8 reserved_at_370[0x3];
1477 u8 log_max_tir[0x5];
1478 u8 reserved_at_378[0x3];
1479 u8 log_max_tis[0x5];
1481 u8 basic_cyclic_rcv_wqe[0x1];
1482 u8 reserved_at_381[0x2];
1483 u8 log_max_rmp[0x5];
1484 u8 reserved_at_388[0x3];
1485 u8 log_max_rqt[0x5];
1486 u8 reserved_at_390[0x3];
1487 u8 log_max_rqt_size[0x5];
1488 u8 reserved_at_398[0x3];
1489 u8 log_max_tis_per_sq[0x5];
1491 u8 ext_stride_num_range[0x1];
1492 u8 reserved_at_3a1[0x2];
1493 u8 log_max_stride_sz_rq[0x5];
1494 u8 reserved_at_3a8[0x3];
1495 u8 log_min_stride_sz_rq[0x5];
1496 u8 reserved_at_3b0[0x3];
1497 u8 log_max_stride_sz_sq[0x5];
1498 u8 reserved_at_3b8[0x3];
1499 u8 log_min_stride_sz_sq[0x5];
1502 u8 reserved_at_3c1[0x2];
1503 u8 log_max_hairpin_queues[0x5];
1504 u8 reserved_at_3c8[0x3];
1505 u8 log_max_hairpin_wq_data_sz[0x5];
1506 u8 reserved_at_3d0[0x3];
1507 u8 log_max_hairpin_num_packets[0x5];
1508 u8 reserved_at_3d8[0x3];
1509 u8 log_max_wq_sz[0x5];
1511 u8 nic_vport_change_event[0x1];
1512 u8 disable_local_lb_uc[0x1];
1513 u8 disable_local_lb_mc[0x1];
1514 u8 log_min_hairpin_wq_data_sz[0x5];
1515 u8 reserved_at_3e8[0x3];
1516 u8 log_max_vlan_list[0x5];
1517 u8 reserved_at_3f0[0x3];
1518 u8 log_max_current_mc_list[0x5];
1519 u8 reserved_at_3f8[0x3];
1520 u8 log_max_current_uc_list[0x5];
1522 u8 general_obj_types[0x40];
1524 u8 reserved_at_440[0x20];
1526 u8 reserved_at_460[0x3];
1527 u8 log_max_uctx[0x5];
1528 u8 reserved_at_468[0x2];
1529 u8 ipsec_offload[0x1];
1530 u8 log_max_umem[0x5];
1531 u8 max_num_eqs[0x10];
1533 u8 reserved_at_480[0x1];
1536 u8 log_max_l2_table[0x5];
1537 u8 reserved_at_488[0x8];
1538 u8 log_uar_page_sz[0x10];
1540 u8 reserved_at_4a0[0x20];
1541 u8 device_frequency_mhz[0x20];
1542 u8 device_frequency_khz[0x20];
1544 u8 reserved_at_500[0x20];
1545 u8 num_of_uars_per_page[0x20];
1547 u8 flex_parser_protocols[0x20];
1549 u8 max_geneve_tlv_options[0x8];
1550 u8 reserved_at_568[0x3];
1551 u8 max_geneve_tlv_option_data_len[0x5];
1552 u8 reserved_at_570[0x10];
1554 u8 reserved_at_580[0x33];
1555 u8 log_max_dek[0x5];
1556 u8 reserved_at_5b8[0x4];
1557 u8 mini_cqe_resp_stride_index[0x1];
1558 u8 cqe_128_always[0x1];
1559 u8 cqe_compression_128[0x1];
1560 u8 cqe_compression[0x1];
1562 u8 cqe_compression_timeout[0x10];
1563 u8 cqe_compression_max_num[0x10];
1565 u8 reserved_at_5e0[0x10];
1566 u8 tag_matching[0x1];
1567 u8 rndv_offload_rc[0x1];
1568 u8 rndv_offload_dc[0x1];
1569 u8 log_tag_matching_list_sz[0x5];
1570 u8 reserved_at_5f8[0x3];
1571 u8 log_max_xrq[0x5];
1573 u8 affiliate_nic_vport_criteria[0x8];
1574 u8 native_port_num[0x8];
1575 u8 num_vhca_ports[0x8];
1576 u8 reserved_at_618[0x6];
1577 u8 sw_owner_id[0x1];
1578 u8 reserved_at_61f[0x1];
1580 u8 max_num_of_monitor_counters[0x10];
1581 u8 num_ppcnt_monitor_counters[0x10];
1583 u8 reserved_at_640[0x10];
1584 u8 num_q_monitor_counters[0x10];
1586 u8 reserved_at_660[0x20];
1589 u8 sf_set_partition[0x1];
1590 u8 reserved_at_682[0x1];
1592 u8 reserved_at_688[0x8];
1593 u8 log_min_sf_size[0x8];
1594 u8 max_num_sf_partitions[0x8];
1598 u8 reserved_at_6c0[0x4];
1599 u8 flex_parser_id_geneve_tlv_option_0[0x4];
1600 u8 flex_parser_id_icmp_dw1[0x4];
1601 u8 flex_parser_id_icmp_dw0[0x4];
1602 u8 flex_parser_id_icmpv6_dw1[0x4];
1603 u8 flex_parser_id_icmpv6_dw0[0x4];
1604 u8 flex_parser_id_outer_first_mpls_over_gre[0x4];
1605 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1607 u8 reserved_at_6e0[0x10];
1608 u8 sf_base_id[0x10];
1610 u8 reserved_at_700[0x80];
1611 u8 vhca_tunnel_commands[0x40];
1612 u8 reserved_at_7c0[0x40];
1615 enum mlx5_flow_destination_type {
1616 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1617 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1618 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1620 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
1621 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1622 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1625 enum mlx5_flow_table_miss_action {
1626 MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1627 MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1628 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1631 struct mlx5_ifc_dest_format_struct_bits {
1632 u8 destination_type[0x8];
1633 u8 destination_id[0x18];
1635 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1636 u8 packet_reformat[0x1];
1637 u8 reserved_at_22[0xe];
1638 u8 destination_eswitch_owner_vhca_id[0x10];
1641 struct mlx5_ifc_flow_counter_list_bits {
1642 u8 flow_counter_id[0x20];
1644 u8 reserved_at_20[0x20];
1647 struct mlx5_ifc_extended_dest_format_bits {
1648 struct mlx5_ifc_dest_format_struct_bits destination_entry;
1650 u8 packet_reformat_id[0x20];
1652 u8 reserved_at_60[0x20];
1655 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1656 struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
1657 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1660 struct mlx5_ifc_fte_match_param_bits {
1661 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1663 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1665 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1667 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1669 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1671 u8 reserved_at_a00[0x600];
1675 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1676 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1677 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1678 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1679 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1682 struct mlx5_ifc_rx_hash_field_select_bits {
1683 u8 l3_prot_type[0x1];
1684 u8 l4_prot_type[0x1];
1685 u8 selected_fields[0x1e];
1689 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1690 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1694 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1695 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1698 struct mlx5_ifc_wq_bits {
1700 u8 wq_signature[0x1];
1701 u8 end_padding_mode[0x2];
1703 u8 reserved_at_8[0x18];
1705 u8 hds_skip_first_sge[0x1];
1706 u8 log2_hds_buf_size[0x3];
1707 u8 reserved_at_24[0x7];
1708 u8 page_offset[0x5];
1711 u8 reserved_at_40[0x8];
1714 u8 reserved_at_60[0x8];
1719 u8 hw_counter[0x20];
1721 u8 sw_counter[0x20];
1723 u8 reserved_at_100[0xc];
1724 u8 log_wq_stride[0x4];
1725 u8 reserved_at_110[0x3];
1726 u8 log_wq_pg_sz[0x5];
1727 u8 reserved_at_118[0x3];
1730 u8 dbr_umem_valid[0x1];
1731 u8 wq_umem_valid[0x1];
1732 u8 reserved_at_122[0x1];
1733 u8 log_hairpin_num_packets[0x5];
1734 u8 reserved_at_128[0x3];
1735 u8 log_hairpin_data_sz[0x5];
1737 u8 reserved_at_130[0x4];
1738 u8 log_wqe_num_of_strides[0x4];
1739 u8 two_byte_shift_en[0x1];
1740 u8 reserved_at_139[0x4];
1741 u8 log_wqe_stride_size[0x3];
1743 u8 reserved_at_140[0x4c0];
1745 struct mlx5_ifc_cmd_pas_bits pas[];
1748 struct mlx5_ifc_rq_num_bits {
1749 u8 reserved_at_0[0x8];
1753 struct mlx5_ifc_mac_address_layout_bits {
1754 u8 reserved_at_0[0x10];
1755 u8 mac_addr_47_32[0x10];
1757 u8 mac_addr_31_0[0x20];
1760 struct mlx5_ifc_vlan_layout_bits {
1761 u8 reserved_at_0[0x14];
1764 u8 reserved_at_20[0x20];
1767 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1768 u8 reserved_at_0[0xa0];
1770 u8 min_time_between_cnps[0x20];
1772 u8 reserved_at_c0[0x12];
1774 u8 reserved_at_d8[0x4];
1775 u8 cnp_prio_mode[0x1];
1776 u8 cnp_802p_prio[0x3];
1778 u8 reserved_at_e0[0x720];
1781 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1782 u8 reserved_at_0[0x60];
1784 u8 reserved_at_60[0x4];
1785 u8 clamp_tgt_rate[0x1];
1786 u8 reserved_at_65[0x3];
1787 u8 clamp_tgt_rate_after_time_inc[0x1];
1788 u8 reserved_at_69[0x17];
1790 u8 reserved_at_80[0x20];
1792 u8 rpg_time_reset[0x20];
1794 u8 rpg_byte_reset[0x20];
1796 u8 rpg_threshold[0x20];
1798 u8 rpg_max_rate[0x20];
1800 u8 rpg_ai_rate[0x20];
1802 u8 rpg_hai_rate[0x20];
1806 u8 rpg_min_dec_fac[0x20];
1808 u8 rpg_min_rate[0x20];
1810 u8 reserved_at_1c0[0xe0];
1812 u8 rate_to_set_on_first_cnp[0x20];
1816 u8 dce_tcp_rtt[0x20];
1818 u8 rate_reduce_monitor_period[0x20];
1820 u8 reserved_at_320[0x20];
1822 u8 initial_alpha_value[0x20];
1824 u8 reserved_at_360[0x4a0];
1827 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1828 u8 reserved_at_0[0x80];
1830 u8 rppp_max_rps[0x20];
1832 u8 rpg_time_reset[0x20];
1834 u8 rpg_byte_reset[0x20];
1836 u8 rpg_threshold[0x20];
1838 u8 rpg_max_rate[0x20];
1840 u8 rpg_ai_rate[0x20];
1842 u8 rpg_hai_rate[0x20];
1846 u8 rpg_min_dec_fac[0x20];
1848 u8 rpg_min_rate[0x20];
1850 u8 reserved_at_1c0[0x640];
1854 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1855 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1856 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1859 struct mlx5_ifc_resize_field_select_bits {
1860 u8 resize_field_select[0x20];
1863 struct mlx5_ifc_resource_dump_bits {
1865 u8 inline_dump[0x1];
1866 u8 reserved_at_2[0xa];
1868 u8 segment_type[0x10];
1870 u8 reserved_at_20[0x10];
1877 u8 num_of_obj1[0x10];
1878 u8 num_of_obj2[0x10];
1880 u8 reserved_at_a0[0x20];
1882 u8 device_opaque[0x40];
1890 u8 inline_data[52][0x20];
1893 struct mlx5_ifc_resource_dump_menu_record_bits {
1894 u8 reserved_at_0[0x4];
1895 u8 num_of_obj2_supports_active[0x1];
1896 u8 num_of_obj2_supports_all[0x1];
1897 u8 must_have_num_of_obj2[0x1];
1898 u8 support_num_of_obj2[0x1];
1899 u8 num_of_obj1_supports_active[0x1];
1900 u8 num_of_obj1_supports_all[0x1];
1901 u8 must_have_num_of_obj1[0x1];
1902 u8 support_num_of_obj1[0x1];
1903 u8 must_have_index2[0x1];
1904 u8 support_index2[0x1];
1905 u8 must_have_index1[0x1];
1906 u8 support_index1[0x1];
1907 u8 segment_type[0x10];
1909 u8 segment_name[4][0x20];
1911 u8 index1_name[4][0x20];
1913 u8 index2_name[4][0x20];
1916 struct mlx5_ifc_resource_dump_segment_header_bits {
1918 u8 segment_type[0x10];
1921 struct mlx5_ifc_resource_dump_command_segment_bits {
1922 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1924 u8 segment_called[0x10];
1931 u8 num_of_obj1[0x10];
1932 u8 num_of_obj2[0x10];
1935 struct mlx5_ifc_resource_dump_error_segment_bits {
1936 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1938 u8 reserved_at_20[0x10];
1939 u8 syndrome_id[0x10];
1941 u8 reserved_at_40[0x40];
1946 struct mlx5_ifc_resource_dump_info_segment_bits {
1947 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1949 u8 reserved_at_20[0x18];
1950 u8 dump_version[0x8];
1952 u8 hw_version[0x20];
1954 u8 fw_version[0x20];
1957 struct mlx5_ifc_resource_dump_menu_segment_bits {
1958 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1960 u8 reserved_at_20[0x10];
1961 u8 num_of_records[0x10];
1963 struct mlx5_ifc_resource_dump_menu_record_bits record[];
1966 struct mlx5_ifc_resource_dump_resource_segment_bits {
1967 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1969 u8 reserved_at_20[0x20];
1978 struct mlx5_ifc_resource_dump_terminate_segment_bits {
1979 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1982 struct mlx5_ifc_menu_resource_dump_response_bits {
1983 struct mlx5_ifc_resource_dump_info_segment_bits info;
1984 struct mlx5_ifc_resource_dump_command_segment_bits cmd;
1985 struct mlx5_ifc_resource_dump_menu_segment_bits menu;
1986 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
1990 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1991 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1992 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1993 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1996 struct mlx5_ifc_modify_field_select_bits {
1997 u8 modify_field_select[0x20];
2000 struct mlx5_ifc_field_select_r_roce_np_bits {
2001 u8 field_select_r_roce_np[0x20];
2004 struct mlx5_ifc_field_select_r_roce_rp_bits {
2005 u8 field_select_r_roce_rp[0x20];
2009 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
2010 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
2011 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
2012 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
2013 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
2014 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
2015 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
2016 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
2017 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
2018 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
2021 struct mlx5_ifc_field_select_802_1qau_rp_bits {
2022 u8 field_select_8021qaurp[0x20];
2025 struct mlx5_ifc_phys_layer_cntrs_bits {
2026 u8 time_since_last_clear_high[0x20];
2028 u8 time_since_last_clear_low[0x20];
2030 u8 symbol_errors_high[0x20];
2032 u8 symbol_errors_low[0x20];
2034 u8 sync_headers_errors_high[0x20];
2036 u8 sync_headers_errors_low[0x20];
2038 u8 edpl_bip_errors_lane0_high[0x20];
2040 u8 edpl_bip_errors_lane0_low[0x20];
2042 u8 edpl_bip_errors_lane1_high[0x20];
2044 u8 edpl_bip_errors_lane1_low[0x20];
2046 u8 edpl_bip_errors_lane2_high[0x20];
2048 u8 edpl_bip_errors_lane2_low[0x20];
2050 u8 edpl_bip_errors_lane3_high[0x20];
2052 u8 edpl_bip_errors_lane3_low[0x20];
2054 u8 fc_fec_corrected_blocks_lane0_high[0x20];
2056 u8 fc_fec_corrected_blocks_lane0_low[0x20];
2058 u8 fc_fec_corrected_blocks_lane1_high[0x20];
2060 u8 fc_fec_corrected_blocks_lane1_low[0x20];
2062 u8 fc_fec_corrected_blocks_lane2_high[0x20];
2064 u8 fc_fec_corrected_blocks_lane2_low[0x20];
2066 u8 fc_fec_corrected_blocks_lane3_high[0x20];
2068 u8 fc_fec_corrected_blocks_lane3_low[0x20];
2070 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
2072 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
2074 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
2076 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
2078 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
2080 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
2082 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
2084 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
2086 u8 rs_fec_corrected_blocks_high[0x20];
2088 u8 rs_fec_corrected_blocks_low[0x20];
2090 u8 rs_fec_uncorrectable_blocks_high[0x20];
2092 u8 rs_fec_uncorrectable_blocks_low[0x20];
2094 u8 rs_fec_no_errors_blocks_high[0x20];
2096 u8 rs_fec_no_errors_blocks_low[0x20];
2098 u8 rs_fec_single_error_blocks_high[0x20];
2100 u8 rs_fec_single_error_blocks_low[0x20];
2102 u8 rs_fec_corrected_symbols_total_high[0x20];
2104 u8 rs_fec_corrected_symbols_total_low[0x20];
2106 u8 rs_fec_corrected_symbols_lane0_high[0x20];
2108 u8 rs_fec_corrected_symbols_lane0_low[0x20];
2110 u8 rs_fec_corrected_symbols_lane1_high[0x20];
2112 u8 rs_fec_corrected_symbols_lane1_low[0x20];
2114 u8 rs_fec_corrected_symbols_lane2_high[0x20];
2116 u8 rs_fec_corrected_symbols_lane2_low[0x20];
2118 u8 rs_fec_corrected_symbols_lane3_high[0x20];
2120 u8 rs_fec_corrected_symbols_lane3_low[0x20];
2122 u8 link_down_events[0x20];
2124 u8 successful_recovery_events[0x20];
2126 u8 reserved_at_640[0x180];
2129 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2130 u8 time_since_last_clear_high[0x20];
2132 u8 time_since_last_clear_low[0x20];
2134 u8 phy_received_bits_high[0x20];
2136 u8 phy_received_bits_low[0x20];
2138 u8 phy_symbol_errors_high[0x20];
2140 u8 phy_symbol_errors_low[0x20];
2142 u8 phy_corrected_bits_high[0x20];
2144 u8 phy_corrected_bits_low[0x20];
2146 u8 phy_corrected_bits_lane0_high[0x20];
2148 u8 phy_corrected_bits_lane0_low[0x20];
2150 u8 phy_corrected_bits_lane1_high[0x20];
2152 u8 phy_corrected_bits_lane1_low[0x20];
2154 u8 phy_corrected_bits_lane2_high[0x20];
2156 u8 phy_corrected_bits_lane2_low[0x20];
2158 u8 phy_corrected_bits_lane3_high[0x20];
2160 u8 phy_corrected_bits_lane3_low[0x20];
2162 u8 reserved_at_200[0x5c0];
2165 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2166 u8 symbol_error_counter[0x10];
2168 u8 link_error_recovery_counter[0x8];
2170 u8 link_downed_counter[0x8];
2172 u8 port_rcv_errors[0x10];
2174 u8 port_rcv_remote_physical_errors[0x10];
2176 u8 port_rcv_switch_relay_errors[0x10];
2178 u8 port_xmit_discards[0x10];
2180 u8 port_xmit_constraint_errors[0x8];
2182 u8 port_rcv_constraint_errors[0x8];
2184 u8 reserved_at_70[0x8];
2186 u8 link_overrun_errors[0x8];
2188 u8 reserved_at_80[0x10];
2190 u8 vl_15_dropped[0x10];
2192 u8 reserved_at_a0[0x80];
2194 u8 port_xmit_wait[0x20];
2197 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2198 u8 transmit_queue_high[0x20];
2200 u8 transmit_queue_low[0x20];
2202 u8 no_buffer_discard_uc_high[0x20];
2204 u8 no_buffer_discard_uc_low[0x20];
2206 u8 reserved_at_80[0x740];
2209 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2210 u8 wred_discard_high[0x20];
2212 u8 wred_discard_low[0x20];
2214 u8 ecn_marked_tc_high[0x20];
2216 u8 ecn_marked_tc_low[0x20];
2218 u8 reserved_at_80[0x740];
2221 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2222 u8 rx_octets_high[0x20];
2224 u8 rx_octets_low[0x20];
2226 u8 reserved_at_40[0xc0];
2228 u8 rx_frames_high[0x20];
2230 u8 rx_frames_low[0x20];
2232 u8 tx_octets_high[0x20];
2234 u8 tx_octets_low[0x20];
2236 u8 reserved_at_180[0xc0];
2238 u8 tx_frames_high[0x20];
2240 u8 tx_frames_low[0x20];
2242 u8 rx_pause_high[0x20];
2244 u8 rx_pause_low[0x20];
2246 u8 rx_pause_duration_high[0x20];
2248 u8 rx_pause_duration_low[0x20];
2250 u8 tx_pause_high[0x20];
2252 u8 tx_pause_low[0x20];
2254 u8 tx_pause_duration_high[0x20];
2256 u8 tx_pause_duration_low[0x20];
2258 u8 rx_pause_transition_high[0x20];
2260 u8 rx_pause_transition_low[0x20];
2262 u8 rx_discards_high[0x20];
2264 u8 rx_discards_low[0x20];
2266 u8 device_stall_minor_watermark_cnt_high[0x20];
2268 u8 device_stall_minor_watermark_cnt_low[0x20];
2270 u8 device_stall_critical_watermark_cnt_high[0x20];
2272 u8 device_stall_critical_watermark_cnt_low[0x20];
2274 u8 reserved_at_480[0x340];
2277 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2278 u8 port_transmit_wait_high[0x20];
2280 u8 port_transmit_wait_low[0x20];
2282 u8 reserved_at_40[0x100];
2284 u8 rx_buffer_almost_full_high[0x20];
2286 u8 rx_buffer_almost_full_low[0x20];
2288 u8 rx_buffer_full_high[0x20];
2290 u8 rx_buffer_full_low[0x20];
2292 u8 rx_icrc_encapsulated_high[0x20];
2294 u8 rx_icrc_encapsulated_low[0x20];
2296 u8 reserved_at_200[0x5c0];
2299 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2300 u8 dot3stats_alignment_errors_high[0x20];
2302 u8 dot3stats_alignment_errors_low[0x20];
2304 u8 dot3stats_fcs_errors_high[0x20];
2306 u8 dot3stats_fcs_errors_low[0x20];
2308 u8 dot3stats_single_collision_frames_high[0x20];
2310 u8 dot3stats_single_collision_frames_low[0x20];
2312 u8 dot3stats_multiple_collision_frames_high[0x20];
2314 u8 dot3stats_multiple_collision_frames_low[0x20];
2316 u8 dot3stats_sqe_test_errors_high[0x20];
2318 u8 dot3stats_sqe_test_errors_low[0x20];
2320 u8 dot3stats_deferred_transmissions_high[0x20];
2322 u8 dot3stats_deferred_transmissions_low[0x20];
2324 u8 dot3stats_late_collisions_high[0x20];
2326 u8 dot3stats_late_collisions_low[0x20];
2328 u8 dot3stats_excessive_collisions_high[0x20];
2330 u8 dot3stats_excessive_collisions_low[0x20];
2332 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
2334 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
2336 u8 dot3stats_carrier_sense_errors_high[0x20];
2338 u8 dot3stats_carrier_sense_errors_low[0x20];
2340 u8 dot3stats_frame_too_longs_high[0x20];
2342 u8 dot3stats_frame_too_longs_low[0x20];
2344 u8 dot3stats_internal_mac_receive_errors_high[0x20];
2346 u8 dot3stats_internal_mac_receive_errors_low[0x20];
2348 u8 dot3stats_symbol_errors_high[0x20];
2350 u8 dot3stats_symbol_errors_low[0x20];
2352 u8 dot3control_in_unknown_opcodes_high[0x20];
2354 u8 dot3control_in_unknown_opcodes_low[0x20];
2356 u8 dot3in_pause_frames_high[0x20];
2358 u8 dot3in_pause_frames_low[0x20];
2360 u8 dot3out_pause_frames_high[0x20];
2362 u8 dot3out_pause_frames_low[0x20];
2364 u8 reserved_at_400[0x3c0];
2367 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2368 u8 ether_stats_drop_events_high[0x20];
2370 u8 ether_stats_drop_events_low[0x20];
2372 u8 ether_stats_octets_high[0x20];
2374 u8 ether_stats_octets_low[0x20];
2376 u8 ether_stats_pkts_high[0x20];
2378 u8 ether_stats_pkts_low[0x20];
2380 u8 ether_stats_broadcast_pkts_high[0x20];
2382 u8 ether_stats_broadcast_pkts_low[0x20];
2384 u8 ether_stats_multicast_pkts_high[0x20];
2386 u8 ether_stats_multicast_pkts_low[0x20];
2388 u8 ether_stats_crc_align_errors_high[0x20];
2390 u8 ether_stats_crc_align_errors_low[0x20];
2392 u8 ether_stats_undersize_pkts_high[0x20];
2394 u8 ether_stats_undersize_pkts_low[0x20];
2396 u8 ether_stats_oversize_pkts_high[0x20];
2398 u8 ether_stats_oversize_pkts_low[0x20];
2400 u8 ether_stats_fragments_high[0x20];
2402 u8 ether_stats_fragments_low[0x20];
2404 u8 ether_stats_jabbers_high[0x20];
2406 u8 ether_stats_jabbers_low[0x20];
2408 u8 ether_stats_collisions_high[0x20];
2410 u8 ether_stats_collisions_low[0x20];
2412 u8 ether_stats_pkts64octets_high[0x20];
2414 u8 ether_stats_pkts64octets_low[0x20];
2416 u8 ether_stats_pkts65to127octets_high[0x20];
2418 u8 ether_stats_pkts65to127octets_low[0x20];
2420 u8 ether_stats_pkts128to255octets_high[0x20];
2422 u8 ether_stats_pkts128to255octets_low[0x20];
2424 u8 ether_stats_pkts256to511octets_high[0x20];
2426 u8 ether_stats_pkts256to511octets_low[0x20];
2428 u8 ether_stats_pkts512to1023octets_high[0x20];
2430 u8 ether_stats_pkts512to1023octets_low[0x20];
2432 u8 ether_stats_pkts1024to1518octets_high[0x20];
2434 u8 ether_stats_pkts1024to1518octets_low[0x20];
2436 u8 ether_stats_pkts1519to2047octets_high[0x20];
2438 u8 ether_stats_pkts1519to2047octets_low[0x20];
2440 u8 ether_stats_pkts2048to4095octets_high[0x20];
2442 u8 ether_stats_pkts2048to4095octets_low[0x20];
2444 u8 ether_stats_pkts4096to8191octets_high[0x20];
2446 u8 ether_stats_pkts4096to8191octets_low[0x20];
2448 u8 ether_stats_pkts8192to10239octets_high[0x20];
2450 u8 ether_stats_pkts8192to10239octets_low[0x20];
2452 u8 reserved_at_540[0x280];
2455 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2456 u8 if_in_octets_high[0x20];
2458 u8 if_in_octets_low[0x20];
2460 u8 if_in_ucast_pkts_high[0x20];
2462 u8 if_in_ucast_pkts_low[0x20];
2464 u8 if_in_discards_high[0x20];
2466 u8 if_in_discards_low[0x20];
2468 u8 if_in_errors_high[0x20];
2470 u8 if_in_errors_low[0x20];
2472 u8 if_in_unknown_protos_high[0x20];
2474 u8 if_in_unknown_protos_low[0x20];
2476 u8 if_out_octets_high[0x20];
2478 u8 if_out_octets_low[0x20];
2480 u8 if_out_ucast_pkts_high[0x20];
2482 u8 if_out_ucast_pkts_low[0x20];
2484 u8 if_out_discards_high[0x20];
2486 u8 if_out_discards_low[0x20];
2488 u8 if_out_errors_high[0x20];
2490 u8 if_out_errors_low[0x20];
2492 u8 if_in_multicast_pkts_high[0x20];
2494 u8 if_in_multicast_pkts_low[0x20];
2496 u8 if_in_broadcast_pkts_high[0x20];
2498 u8 if_in_broadcast_pkts_low[0x20];
2500 u8 if_out_multicast_pkts_high[0x20];
2502 u8 if_out_multicast_pkts_low[0x20];
2504 u8 if_out_broadcast_pkts_high[0x20];
2506 u8 if_out_broadcast_pkts_low[0x20];
2508 u8 reserved_at_340[0x480];
2511 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2512 u8 a_frames_transmitted_ok_high[0x20];
2514 u8 a_frames_transmitted_ok_low[0x20];
2516 u8 a_frames_received_ok_high[0x20];
2518 u8 a_frames_received_ok_low[0x20];
2520 u8 a_frame_check_sequence_errors_high[0x20];
2522 u8 a_frame_check_sequence_errors_low[0x20];
2524 u8 a_alignment_errors_high[0x20];
2526 u8 a_alignment_errors_low[0x20];
2528 u8 a_octets_transmitted_ok_high[0x20];
2530 u8 a_octets_transmitted_ok_low[0x20];
2532 u8 a_octets_received_ok_high[0x20];
2534 u8 a_octets_received_ok_low[0x20];
2536 u8 a_multicast_frames_xmitted_ok_high[0x20];
2538 u8 a_multicast_frames_xmitted_ok_low[0x20];
2540 u8 a_broadcast_frames_xmitted_ok_high[0x20];
2542 u8 a_broadcast_frames_xmitted_ok_low[0x20];
2544 u8 a_multicast_frames_received_ok_high[0x20];
2546 u8 a_multicast_frames_received_ok_low[0x20];
2548 u8 a_broadcast_frames_received_ok_high[0x20];
2550 u8 a_broadcast_frames_received_ok_low[0x20];
2552 u8 a_in_range_length_errors_high[0x20];
2554 u8 a_in_range_length_errors_low[0x20];
2556 u8 a_out_of_range_length_field_high[0x20];
2558 u8 a_out_of_range_length_field_low[0x20];
2560 u8 a_frame_too_long_errors_high[0x20];
2562 u8 a_frame_too_long_errors_low[0x20];
2564 u8 a_symbol_error_during_carrier_high[0x20];
2566 u8 a_symbol_error_during_carrier_low[0x20];
2568 u8 a_mac_control_frames_transmitted_high[0x20];
2570 u8 a_mac_control_frames_transmitted_low[0x20];
2572 u8 a_mac_control_frames_received_high[0x20];
2574 u8 a_mac_control_frames_received_low[0x20];
2576 u8 a_unsupported_opcodes_received_high[0x20];
2578 u8 a_unsupported_opcodes_received_low[0x20];
2580 u8 a_pause_mac_ctrl_frames_received_high[0x20];
2582 u8 a_pause_mac_ctrl_frames_received_low[0x20];
2584 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
2586 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
2588 u8 reserved_at_4c0[0x300];
2591 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2592 u8 life_time_counter_high[0x20];
2594 u8 life_time_counter_low[0x20];
2600 u8 l0_to_recovery_eieos[0x20];
2602 u8 l0_to_recovery_ts[0x20];
2604 u8 l0_to_recovery_framing[0x20];
2606 u8 l0_to_recovery_retrain[0x20];
2608 u8 crc_error_dllp[0x20];
2610 u8 crc_error_tlp[0x20];
2612 u8 tx_overflow_buffer_pkt_high[0x20];
2614 u8 tx_overflow_buffer_pkt_low[0x20];
2616 u8 outbound_stalled_reads[0x20];
2618 u8 outbound_stalled_writes[0x20];
2620 u8 outbound_stalled_reads_events[0x20];
2622 u8 outbound_stalled_writes_events[0x20];
2624 u8 reserved_at_200[0x5c0];
2627 struct mlx5_ifc_cmd_inter_comp_event_bits {
2628 u8 command_completion_vector[0x20];
2630 u8 reserved_at_20[0xc0];
2633 struct mlx5_ifc_stall_vl_event_bits {
2634 u8 reserved_at_0[0x18];
2636 u8 reserved_at_19[0x3];
2639 u8 reserved_at_20[0xa0];
2642 struct mlx5_ifc_db_bf_congestion_event_bits {
2643 u8 event_subtype[0x8];
2644 u8 reserved_at_8[0x8];
2645 u8 congestion_level[0x8];
2646 u8 reserved_at_18[0x8];
2648 u8 reserved_at_20[0xa0];
2651 struct mlx5_ifc_gpio_event_bits {
2652 u8 reserved_at_0[0x60];
2654 u8 gpio_event_hi[0x20];
2656 u8 gpio_event_lo[0x20];
2658 u8 reserved_at_a0[0x40];
2661 struct mlx5_ifc_port_state_change_event_bits {
2662 u8 reserved_at_0[0x40];
2665 u8 reserved_at_44[0x1c];
2667 u8 reserved_at_60[0x80];
2670 struct mlx5_ifc_dropped_packet_logged_bits {
2671 u8 reserved_at_0[0xe0];
2675 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2676 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2679 struct mlx5_ifc_cq_error_bits {
2680 u8 reserved_at_0[0x8];
2683 u8 reserved_at_20[0x20];
2685 u8 reserved_at_40[0x18];
2688 u8 reserved_at_60[0x80];
2691 struct mlx5_ifc_rdma_page_fault_event_bits {
2692 u8 bytes_committed[0x20];
2696 u8 reserved_at_40[0x10];
2697 u8 packet_len[0x10];
2699 u8 rdma_op_len[0x20];
2703 u8 reserved_at_c0[0x5];
2710 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2711 u8 bytes_committed[0x20];
2713 u8 reserved_at_20[0x10];
2716 u8 reserved_at_40[0x10];
2719 u8 reserved_at_60[0x60];
2721 u8 reserved_at_c0[0x5];
2728 struct mlx5_ifc_qp_events_bits {
2729 u8 reserved_at_0[0xa0];
2732 u8 reserved_at_a8[0x18];
2734 u8 reserved_at_c0[0x8];
2735 u8 qpn_rqn_sqn[0x18];
2738 struct mlx5_ifc_dct_events_bits {
2739 u8 reserved_at_0[0xc0];
2741 u8 reserved_at_c0[0x8];
2742 u8 dct_number[0x18];
2745 struct mlx5_ifc_comp_event_bits {
2746 u8 reserved_at_0[0xc0];
2748 u8 reserved_at_c0[0x8];
2753 MLX5_QPC_STATE_RST = 0x0,
2754 MLX5_QPC_STATE_INIT = 0x1,
2755 MLX5_QPC_STATE_RTR = 0x2,
2756 MLX5_QPC_STATE_RTS = 0x3,
2757 MLX5_QPC_STATE_SQER = 0x4,
2758 MLX5_QPC_STATE_ERR = 0x6,
2759 MLX5_QPC_STATE_SQD = 0x7,
2760 MLX5_QPC_STATE_SUSPENDED = 0x9,
2764 MLX5_QPC_ST_RC = 0x0,
2765 MLX5_QPC_ST_UC = 0x1,
2766 MLX5_QPC_ST_UD = 0x2,
2767 MLX5_QPC_ST_XRC = 0x3,
2768 MLX5_QPC_ST_DCI = 0x5,
2769 MLX5_QPC_ST_QP0 = 0x7,
2770 MLX5_QPC_ST_QP1 = 0x8,
2771 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2772 MLX5_QPC_ST_REG_UMR = 0xc,
2776 MLX5_QPC_PM_STATE_ARMED = 0x0,
2777 MLX5_QPC_PM_STATE_REARM = 0x1,
2778 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2779 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2783 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2787 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2788 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2792 MLX5_QPC_MTU_256_BYTES = 0x1,
2793 MLX5_QPC_MTU_512_BYTES = 0x2,
2794 MLX5_QPC_MTU_1K_BYTES = 0x3,
2795 MLX5_QPC_MTU_2K_BYTES = 0x4,
2796 MLX5_QPC_MTU_4K_BYTES = 0x5,
2797 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2801 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2802 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2803 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2804 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2805 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2806 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2807 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2808 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2812 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2813 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2814 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2818 MLX5_QPC_CS_RES_DISABLE = 0x0,
2819 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2820 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2823 struct mlx5_ifc_qpc_bits {
2825 u8 lag_tx_port_affinity[0x4];
2827 u8 reserved_at_10[0x3];
2829 u8 reserved_at_15[0x1];
2830 u8 req_e2e_credit_mode[0x2];
2831 u8 offload_type[0x4];
2832 u8 end_padding_mode[0x2];
2833 u8 reserved_at_1e[0x2];
2835 u8 wq_signature[0x1];
2836 u8 block_lb_mc[0x1];
2837 u8 atomic_like_write_en[0x1];
2838 u8 latency_sensitive[0x1];
2839 u8 reserved_at_24[0x1];
2840 u8 drain_sigerr[0x1];
2841 u8 reserved_at_26[0x2];
2845 u8 log_msg_max[0x5];
2846 u8 reserved_at_48[0x1];
2847 u8 log_rq_size[0x4];
2848 u8 log_rq_stride[0x3];
2850 u8 log_sq_size[0x4];
2851 u8 reserved_at_55[0x6];
2853 u8 ulp_stateless_offload_mode[0x4];
2855 u8 counter_set_id[0x8];
2858 u8 reserved_at_80[0x8];
2859 u8 user_index[0x18];
2861 u8 reserved_at_a0[0x3];
2862 u8 log_page_size[0x5];
2863 u8 remote_qpn[0x18];
2865 struct mlx5_ifc_ads_bits primary_address_path;
2867 struct mlx5_ifc_ads_bits secondary_address_path;
2869 u8 log_ack_req_freq[0x4];
2870 u8 reserved_at_384[0x4];
2871 u8 log_sra_max[0x3];
2872 u8 reserved_at_38b[0x2];
2873 u8 retry_count[0x3];
2875 u8 reserved_at_393[0x1];
2877 u8 cur_rnr_retry[0x3];
2878 u8 cur_retry_count[0x3];
2879 u8 reserved_at_39b[0x5];
2881 u8 reserved_at_3a0[0x20];
2883 u8 reserved_at_3c0[0x8];
2884 u8 next_send_psn[0x18];
2886 u8 reserved_at_3e0[0x8];
2889 u8 reserved_at_400[0x8];
2892 u8 reserved_at_420[0x20];
2894 u8 reserved_at_440[0x8];
2895 u8 last_acked_psn[0x18];
2897 u8 reserved_at_460[0x8];
2900 u8 reserved_at_480[0x8];
2901 u8 log_rra_max[0x3];
2902 u8 reserved_at_48b[0x1];
2903 u8 atomic_mode[0x4];
2907 u8 reserved_at_493[0x1];
2908 u8 page_offset[0x6];
2909 u8 reserved_at_49a[0x3];
2910 u8 cd_slave_receive[0x1];
2911 u8 cd_slave_send[0x1];
2914 u8 reserved_at_4a0[0x3];
2915 u8 min_rnr_nak[0x5];
2916 u8 next_rcv_psn[0x18];
2918 u8 reserved_at_4c0[0x8];
2921 u8 reserved_at_4e0[0x8];
2928 u8 reserved_at_560[0x5];
2930 u8 srqn_rmpn_xrqn[0x18];
2932 u8 reserved_at_580[0x8];
2935 u8 hw_sq_wqebb_counter[0x10];
2936 u8 sw_sq_wqebb_counter[0x10];
2938 u8 hw_rq_counter[0x20];
2940 u8 sw_rq_counter[0x20];
2942 u8 reserved_at_600[0x20];
2944 u8 reserved_at_620[0xf];
2949 u8 dc_access_key[0x40];
2951 u8 reserved_at_680[0x3];
2952 u8 dbr_umem_valid[0x1];
2954 u8 reserved_at_684[0xbc];
2957 struct mlx5_ifc_roce_addr_layout_bits {
2958 u8 source_l3_address[16][0x8];
2960 u8 reserved_at_80[0x3];
2963 u8 source_mac_47_32[0x10];
2965 u8 source_mac_31_0[0x20];
2967 u8 reserved_at_c0[0x14];
2968 u8 roce_l3_type[0x4];
2969 u8 roce_version[0x8];
2971 u8 reserved_at_e0[0x20];
2974 union mlx5_ifc_hca_cap_union_bits {
2975 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2976 struct mlx5_ifc_odp_cap_bits odp_cap;
2977 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2978 struct mlx5_ifc_roce_cap_bits roce_cap;
2979 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2980 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2981 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2982 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2983 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2984 struct mlx5_ifc_qos_cap_bits qos_cap;
2985 struct mlx5_ifc_debug_cap_bits debug_cap;
2986 struct mlx5_ifc_fpga_cap_bits fpga_cap;
2987 struct mlx5_ifc_tls_cap_bits tls_cap;
2988 struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
2989 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
2990 u8 reserved_at_0[0x8000];
2994 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2995 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2996 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2997 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2998 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2999 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
3000 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
3001 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
3002 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3003 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
3004 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3005 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000,
3006 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000,
3010 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0,
3011 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1,
3012 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2,
3015 struct mlx5_ifc_vlan_bits {
3022 struct mlx5_ifc_flow_context_bits {
3023 struct mlx5_ifc_vlan_bits push_vlan;
3027 u8 reserved_at_40[0x8];
3030 u8 reserved_at_60[0x10];
3033 u8 extended_destination[0x1];
3034 u8 reserved_at_81[0x1];
3035 u8 flow_source[0x2];
3036 u8 reserved_at_84[0x4];
3037 u8 destination_list_size[0x18];
3039 u8 reserved_at_a0[0x8];
3040 u8 flow_counter_list_size[0x18];
3042 u8 packet_reformat_id[0x20];
3044 u8 modify_header_id[0x20];
3046 struct mlx5_ifc_vlan_bits push_vlan_2;
3048 u8 ipsec_obj_id[0x20];
3049 u8 reserved_at_140[0xc0];
3051 struct mlx5_ifc_fte_match_param_bits match_value;
3053 u8 reserved_at_1200[0x600];
3055 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
3059 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
3060 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
3063 struct mlx5_ifc_xrc_srqc_bits {
3065 u8 log_xrc_srq_size[0x4];
3066 u8 reserved_at_8[0x18];
3068 u8 wq_signature[0x1];
3070 u8 reserved_at_22[0x1];
3072 u8 basic_cyclic_rcv_wqe[0x1];
3073 u8 log_rq_stride[0x3];
3076 u8 page_offset[0x6];
3077 u8 reserved_at_46[0x1];
3078 u8 dbr_umem_valid[0x1];
3081 u8 reserved_at_60[0x20];
3083 u8 user_index_equal_xrc_srqn[0x1];
3084 u8 reserved_at_81[0x1];
3085 u8 log_page_size[0x6];
3086 u8 user_index[0x18];
3088 u8 reserved_at_a0[0x20];
3090 u8 reserved_at_c0[0x8];
3096 u8 reserved_at_100[0x40];
3098 u8 db_record_addr_h[0x20];
3100 u8 db_record_addr_l[0x1e];
3101 u8 reserved_at_17e[0x2];
3103 u8 reserved_at_180[0x80];
3106 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3107 u8 counter_error_queues[0x20];
3109 u8 total_error_queues[0x20];
3111 u8 send_queue_priority_update_flow[0x20];
3113 u8 reserved_at_60[0x20];
3115 u8 nic_receive_steering_discard[0x40];
3117 u8 receive_discard_vport_down[0x40];
3119 u8 transmit_discard_vport_down[0x40];
3121 u8 reserved_at_140[0xa0];
3123 u8 internal_rq_out_of_buffer[0x20];
3125 u8 reserved_at_200[0xe00];
3128 struct mlx5_ifc_traffic_counter_bits {
3134 struct mlx5_ifc_tisc_bits {
3135 u8 strict_lag_tx_port_affinity[0x1];
3137 u8 reserved_at_2[0x2];
3138 u8 lag_tx_port_affinity[0x04];
3140 u8 reserved_at_8[0x4];
3142 u8 reserved_at_10[0x10];
3144 u8 reserved_at_20[0x100];
3146 u8 reserved_at_120[0x8];
3147 u8 transport_domain[0x18];
3149 u8 reserved_at_140[0x8];
3150 u8 underlay_qpn[0x18];
3152 u8 reserved_at_160[0x8];
3155 u8 reserved_at_180[0x380];
3159 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
3160 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
3164 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
3165 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
3169 MLX5_RX_HASH_FN_NONE = 0x0,
3170 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
3171 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
3175 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
3176 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
3179 struct mlx5_ifc_tirc_bits {
3180 u8 reserved_at_0[0x20];
3184 u8 reserved_at_25[0x1b];
3186 u8 reserved_at_40[0x40];
3188 u8 reserved_at_80[0x4];
3189 u8 lro_timeout_period_usecs[0x10];
3190 u8 lro_enable_mask[0x4];
3191 u8 lro_max_ip_payload_size[0x8];
3193 u8 reserved_at_a0[0x40];
3195 u8 reserved_at_e0[0x8];
3196 u8 inline_rqn[0x18];
3198 u8 rx_hash_symmetric[0x1];
3199 u8 reserved_at_101[0x1];
3200 u8 tunneled_offload_en[0x1];
3201 u8 reserved_at_103[0x5];
3202 u8 indirect_table[0x18];
3205 u8 reserved_at_124[0x2];
3206 u8 self_lb_block[0x2];
3207 u8 transport_domain[0x18];
3209 u8 rx_hash_toeplitz_key[10][0x20];
3211 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3213 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3215 u8 reserved_at_2c0[0x4c0];
3219 MLX5_SRQC_STATE_GOOD = 0x0,
3220 MLX5_SRQC_STATE_ERROR = 0x1,
3223 struct mlx5_ifc_srqc_bits {
3225 u8 log_srq_size[0x4];
3226 u8 reserved_at_8[0x18];
3228 u8 wq_signature[0x1];
3230 u8 reserved_at_22[0x1];
3232 u8 reserved_at_24[0x1];
3233 u8 log_rq_stride[0x3];
3236 u8 page_offset[0x6];
3237 u8 reserved_at_46[0x2];
3240 u8 reserved_at_60[0x20];
3242 u8 reserved_at_80[0x2];
3243 u8 log_page_size[0x6];
3244 u8 reserved_at_88[0x18];
3246 u8 reserved_at_a0[0x20];
3248 u8 reserved_at_c0[0x8];
3254 u8 reserved_at_100[0x40];
3258 u8 reserved_at_180[0x80];
3262 MLX5_SQC_STATE_RST = 0x0,
3263 MLX5_SQC_STATE_RDY = 0x1,
3264 MLX5_SQC_STATE_ERR = 0x3,
3267 struct mlx5_ifc_sqc_bits {
3271 u8 flush_in_error_en[0x1];
3272 u8 allow_multi_pkt_send_wqe[0x1];
3273 u8 min_wqe_inline_mode[0x3];
3278 u8 reserved_at_f[0x11];
3280 u8 reserved_at_20[0x8];
3281 u8 user_index[0x18];
3283 u8 reserved_at_40[0x8];
3286 u8 reserved_at_60[0x8];
3287 u8 hairpin_peer_rq[0x18];
3289 u8 reserved_at_80[0x10];
3290 u8 hairpin_peer_vhca[0x10];
3292 u8 reserved_at_a0[0x50];
3294 u8 packet_pacing_rate_limit_index[0x10];
3295 u8 tis_lst_sz[0x10];
3296 u8 reserved_at_110[0x10];
3298 u8 reserved_at_120[0x40];
3300 u8 reserved_at_160[0x8];
3303 struct mlx5_ifc_wq_bits wq;
3307 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3308 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3309 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3310 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3314 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0,
3315 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1,
3316 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2,
3317 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3,
3320 struct mlx5_ifc_scheduling_context_bits {
3321 u8 element_type[0x8];
3322 u8 reserved_at_8[0x18];
3324 u8 element_attributes[0x20];
3326 u8 parent_element_id[0x20];
3328 u8 reserved_at_60[0x40];
3332 u8 max_average_bw[0x20];
3334 u8 reserved_at_e0[0x120];
3337 struct mlx5_ifc_rqtc_bits {
3338 u8 reserved_at_0[0xa0];
3340 u8 reserved_at_a0[0x5];
3341 u8 list_q_type[0x3];
3342 u8 reserved_at_a8[0x8];
3343 u8 rqt_max_size[0x10];
3345 u8 rq_vhca_id_format[0x1];
3346 u8 reserved_at_c1[0xf];
3347 u8 rqt_actual_size[0x10];
3349 u8 reserved_at_e0[0x6a0];
3351 struct mlx5_ifc_rq_num_bits rq_num[];
3355 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
3356 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
3360 MLX5_RQC_STATE_RST = 0x0,
3361 MLX5_RQC_STATE_RDY = 0x1,
3362 MLX5_RQC_STATE_ERR = 0x3,
3365 struct mlx5_ifc_rqc_bits {
3367 u8 delay_drop_en[0x1];
3368 u8 scatter_fcs[0x1];
3370 u8 mem_rq_type[0x4];
3372 u8 reserved_at_c[0x1];
3373 u8 flush_in_error_en[0x1];
3375 u8 reserved_at_f[0x11];
3377 u8 reserved_at_20[0x8];
3378 u8 user_index[0x18];
3380 u8 reserved_at_40[0x8];
3383 u8 counter_set_id[0x8];
3384 u8 reserved_at_68[0x18];
3386 u8 reserved_at_80[0x8];
3389 u8 reserved_at_a0[0x8];
3390 u8 hairpin_peer_sq[0x18];
3392 u8 reserved_at_c0[0x10];
3393 u8 hairpin_peer_vhca[0x10];
3395 u8 reserved_at_e0[0xa0];
3397 struct mlx5_ifc_wq_bits wq;
3401 MLX5_RMPC_STATE_RDY = 0x1,
3402 MLX5_RMPC_STATE_ERR = 0x3,
3405 struct mlx5_ifc_rmpc_bits {
3406 u8 reserved_at_0[0x8];
3408 u8 reserved_at_c[0x14];
3410 u8 basic_cyclic_rcv_wqe[0x1];
3411 u8 reserved_at_21[0x1f];
3413 u8 reserved_at_40[0x140];
3415 struct mlx5_ifc_wq_bits wq;
3418 struct mlx5_ifc_nic_vport_context_bits {
3419 u8 reserved_at_0[0x5];
3420 u8 min_wqe_inline_mode[0x3];
3421 u8 reserved_at_8[0x15];
3422 u8 disable_mc_local_lb[0x1];
3423 u8 disable_uc_local_lb[0x1];
3426 u8 arm_change_event[0x1];
3427 u8 reserved_at_21[0x1a];
3428 u8 event_on_mtu[0x1];
3429 u8 event_on_promisc_change[0x1];
3430 u8 event_on_vlan_change[0x1];
3431 u8 event_on_mc_address_change[0x1];
3432 u8 event_on_uc_address_change[0x1];
3434 u8 reserved_at_40[0xc];
3436 u8 affiliation_criteria[0x4];
3437 u8 affiliated_vhca_id[0x10];
3439 u8 reserved_at_60[0xd0];
3443 u8 system_image_guid[0x40];
3447 u8 reserved_at_200[0x140];
3448 u8 qkey_violation_counter[0x10];
3449 u8 reserved_at_350[0x430];
3453 u8 promisc_all[0x1];
3454 u8 reserved_at_783[0x2];
3455 u8 allowed_list_type[0x3];
3456 u8 reserved_at_788[0xc];
3457 u8 allowed_list_size[0xc];
3459 struct mlx5_ifc_mac_address_layout_bits permanent_address;
3461 u8 reserved_at_7e0[0x20];
3463 u8 current_uc_mac_address[][0x40];
3467 MLX5_MKC_ACCESS_MODE_PA = 0x0,
3468 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
3469 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
3470 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
3471 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3472 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3475 struct mlx5_ifc_mkc_bits {
3476 u8 reserved_at_0[0x1];
3478 u8 reserved_at_2[0x1];
3479 u8 access_mode_4_2[0x3];
3480 u8 reserved_at_6[0x7];
3481 u8 relaxed_ordering_write[0x1];
3482 u8 reserved_at_e[0x1];
3483 u8 small_fence_on_rdma_read_response[0x1];
3490 u8 access_mode_1_0[0x2];
3491 u8 reserved_at_18[0x8];
3496 u8 reserved_at_40[0x20];
3501 u8 reserved_at_63[0x2];
3502 u8 expected_sigerr_count[0x1];
3503 u8 reserved_at_66[0x1];
3507 u8 start_addr[0x40];
3511 u8 bsf_octword_size[0x20];
3513 u8 reserved_at_120[0x80];
3515 u8 translations_octword_size[0x20];
3517 u8 reserved_at_1c0[0x19];
3518 u8 relaxed_ordering_read[0x1];
3519 u8 reserved_at_1d9[0x1];
3520 u8 log_page_size[0x5];
3522 u8 reserved_at_1e0[0x20];
3525 struct mlx5_ifc_pkey_bits {
3526 u8 reserved_at_0[0x10];
3530 struct mlx5_ifc_array128_auto_bits {
3531 u8 array128_auto[16][0x8];
3534 struct mlx5_ifc_hca_vport_context_bits {
3535 u8 field_select[0x20];
3537 u8 reserved_at_20[0xe0];
3539 u8 sm_virt_aware[0x1];
3542 u8 grh_required[0x1];
3543 u8 reserved_at_104[0xc];
3544 u8 port_physical_state[0x4];
3545 u8 vport_state_policy[0x4];
3547 u8 vport_state[0x4];
3549 u8 reserved_at_120[0x20];
3551 u8 system_image_guid[0x40];
3559 u8 cap_mask1_field_select[0x20];
3563 u8 cap_mask2_field_select[0x20];
3565 u8 reserved_at_280[0x80];
3568 u8 reserved_at_310[0x4];
3569 u8 init_type_reply[0x4];
3571 u8 subnet_timeout[0x5];
3575 u8 reserved_at_334[0xc];
3577 u8 qkey_violation_counter[0x10];
3578 u8 pkey_violation_counter[0x10];
3580 u8 reserved_at_360[0xca0];
3583 struct mlx5_ifc_esw_vport_context_bits {
3584 u8 fdb_to_vport_reg_c[0x1];
3585 u8 reserved_at_1[0x2];
3586 u8 vport_svlan_strip[0x1];
3587 u8 vport_cvlan_strip[0x1];
3588 u8 vport_svlan_insert[0x1];
3589 u8 vport_cvlan_insert[0x2];
3590 u8 fdb_to_vport_reg_c_id[0x8];
3591 u8 reserved_at_10[0x10];
3593 u8 reserved_at_20[0x20];
3602 u8 reserved_at_60[0x720];
3604 u8 sw_steering_vport_icm_address_rx[0x40];
3606 u8 sw_steering_vport_icm_address_tx[0x40];
3610 MLX5_EQC_STATUS_OK = 0x0,
3611 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
3615 MLX5_EQC_ST_ARMED = 0x9,
3616 MLX5_EQC_ST_FIRED = 0xa,
3619 struct mlx5_ifc_eqc_bits {
3621 u8 reserved_at_4[0x9];
3624 u8 reserved_at_f[0x5];
3626 u8 reserved_at_18[0x8];
3628 u8 reserved_at_20[0x20];
3630 u8 reserved_at_40[0x14];
3631 u8 page_offset[0x6];
3632 u8 reserved_at_5a[0x6];
3634 u8 reserved_at_60[0x3];
3635 u8 log_eq_size[0x5];
3638 u8 reserved_at_80[0x20];
3640 u8 reserved_at_a0[0x18];
3643 u8 reserved_at_c0[0x3];
3644 u8 log_page_size[0x5];
3645 u8 reserved_at_c8[0x18];
3647 u8 reserved_at_e0[0x60];
3649 u8 reserved_at_140[0x8];
3650 u8 consumer_counter[0x18];
3652 u8 reserved_at_160[0x8];
3653 u8 producer_counter[0x18];
3655 u8 reserved_at_180[0x80];
3659 MLX5_DCTC_STATE_ACTIVE = 0x0,
3660 MLX5_DCTC_STATE_DRAINING = 0x1,
3661 MLX5_DCTC_STATE_DRAINED = 0x2,
3665 MLX5_DCTC_CS_RES_DISABLE = 0x0,
3666 MLX5_DCTC_CS_RES_NA = 0x1,
3667 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
3671 MLX5_DCTC_MTU_256_BYTES = 0x1,
3672 MLX5_DCTC_MTU_512_BYTES = 0x2,
3673 MLX5_DCTC_MTU_1K_BYTES = 0x3,
3674 MLX5_DCTC_MTU_2K_BYTES = 0x4,
3675 MLX5_DCTC_MTU_4K_BYTES = 0x5,
3678 struct mlx5_ifc_dctc_bits {
3679 u8 reserved_at_0[0x4];
3681 u8 reserved_at_8[0x18];
3683 u8 reserved_at_20[0x8];
3684 u8 user_index[0x18];
3686 u8 reserved_at_40[0x8];
3689 u8 counter_set_id[0x8];
3690 u8 atomic_mode[0x4];
3694 u8 atomic_like_write_en[0x1];
3695 u8 latency_sensitive[0x1];
3698 u8 reserved_at_73[0xd];
3700 u8 reserved_at_80[0x8];
3702 u8 reserved_at_90[0x3];
3703 u8 min_rnr_nak[0x5];
3704 u8 reserved_at_98[0x8];
3706 u8 reserved_at_a0[0x8];
3709 u8 reserved_at_c0[0x8];
3713 u8 reserved_at_e8[0x4];
3714 u8 flow_label[0x14];
3716 u8 dc_access_key[0x40];
3718 u8 reserved_at_140[0x5];
3721 u8 pkey_index[0x10];
3723 u8 reserved_at_160[0x8];
3724 u8 my_addr_index[0x8];
3725 u8 reserved_at_170[0x8];
3728 u8 dc_access_key_violation_count[0x20];
3730 u8 reserved_at_1a0[0x14];
3736 u8 reserved_at_1c0[0x20];
3741 MLX5_CQC_STATUS_OK = 0x0,
3742 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3743 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3747 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3748 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3752 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3753 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3754 MLX5_CQC_ST_FIRED = 0xa,
3758 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3759 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3760 MLX5_CQ_PERIOD_NUM_MODES
3763 struct mlx5_ifc_cqc_bits {
3765 u8 reserved_at_4[0x2];
3766 u8 dbr_umem_valid[0x1];
3767 u8 reserved_at_7[0x1];
3770 u8 reserved_at_c[0x1];
3771 u8 scqe_break_moderation_en[0x1];
3773 u8 cq_period_mode[0x2];
3774 u8 cqe_comp_en[0x1];
3775 u8 mini_cqe_res_format[0x2];
3777 u8 reserved_at_18[0x8];
3779 u8 reserved_at_20[0x20];
3781 u8 reserved_at_40[0x14];
3782 u8 page_offset[0x6];
3783 u8 reserved_at_5a[0x6];
3785 u8 reserved_at_60[0x3];
3786 u8 log_cq_size[0x5];
3789 u8 reserved_at_80[0x4];
3791 u8 cq_max_count[0x10];
3793 u8 reserved_at_a0[0x18];
3796 u8 reserved_at_c0[0x3];
3797 u8 log_page_size[0x5];
3798 u8 reserved_at_c8[0x18];
3800 u8 reserved_at_e0[0x20];
3802 u8 reserved_at_100[0x8];
3803 u8 last_notified_index[0x18];
3805 u8 reserved_at_120[0x8];
3806 u8 last_solicit_index[0x18];
3808 u8 reserved_at_140[0x8];
3809 u8 consumer_counter[0x18];
3811 u8 reserved_at_160[0x8];
3812 u8 producer_counter[0x18];
3814 u8 reserved_at_180[0x40];
3819 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3820 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3821 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3822 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3823 u8 reserved_at_0[0x800];
3826 struct mlx5_ifc_query_adapter_param_block_bits {
3827 u8 reserved_at_0[0xc0];
3829 u8 reserved_at_c0[0x8];
3830 u8 ieee_vendor_id[0x18];
3832 u8 reserved_at_e0[0x10];
3833 u8 vsd_vendor_id[0x10];
3837 u8 vsd_contd_psid[16][0x8];
3841 MLX5_XRQC_STATE_GOOD = 0x0,
3842 MLX5_XRQC_STATE_ERROR = 0x1,
3846 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3847 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3851 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3854 struct mlx5_ifc_tag_matching_topology_context_bits {
3855 u8 log_matching_list_sz[0x4];
3856 u8 reserved_at_4[0xc];
3857 u8 append_next_index[0x10];
3859 u8 sw_phase_cnt[0x10];
3860 u8 hw_phase_cnt[0x10];
3862 u8 reserved_at_40[0x40];
3865 struct mlx5_ifc_xrqc_bits {
3868 u8 reserved_at_5[0xf];
3870 u8 reserved_at_18[0x4];
3873 u8 reserved_at_20[0x8];
3874 u8 user_index[0x18];
3876 u8 reserved_at_40[0x8];
3879 u8 reserved_at_60[0xa0];
3881 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3883 u8 reserved_at_180[0x280];
3885 struct mlx5_ifc_wq_bits wq;
3888 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3889 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3890 struct mlx5_ifc_resize_field_select_bits resize_field_select;
3891 u8 reserved_at_0[0x20];
3894 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3895 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3896 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3897 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3898 u8 reserved_at_0[0x20];
3901 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3902 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3903 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3904 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3905 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3906 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3907 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3908 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
3909 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
3910 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3911 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3912 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3913 u8 reserved_at_0[0x7c0];
3916 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3917 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3918 u8 reserved_at_0[0x7c0];
3921 union mlx5_ifc_event_auto_bits {
3922 struct mlx5_ifc_comp_event_bits comp_event;
3923 struct mlx5_ifc_dct_events_bits dct_events;
3924 struct mlx5_ifc_qp_events_bits qp_events;
3925 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3926 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3927 struct mlx5_ifc_cq_error_bits cq_error;
3928 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3929 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3930 struct mlx5_ifc_gpio_event_bits gpio_event;
3931 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3932 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3933 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3934 u8 reserved_at_0[0xe0];
3937 struct mlx5_ifc_health_buffer_bits {
3938 u8 reserved_at_0[0x100];
3940 u8 assert_existptr[0x20];
3942 u8 assert_callra[0x20];
3944 u8 reserved_at_140[0x40];
3946 u8 fw_version[0x20];
3950 u8 reserved_at_1c0[0x20];
3952 u8 irisc_index[0x8];
3957 struct mlx5_ifc_register_loopback_control_bits {
3959 u8 reserved_at_1[0x7];
3961 u8 reserved_at_10[0x10];
3963 u8 reserved_at_20[0x60];
3966 struct mlx5_ifc_vport_tc_element_bits {
3967 u8 traffic_class[0x4];
3968 u8 reserved_at_4[0xc];
3969 u8 vport_number[0x10];
3972 struct mlx5_ifc_vport_element_bits {
3973 u8 reserved_at_0[0x10];
3974 u8 vport_number[0x10];
3978 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3979 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3980 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3983 struct mlx5_ifc_tsar_element_bits {
3984 u8 reserved_at_0[0x8];
3986 u8 reserved_at_10[0x10];
3990 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3991 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3994 struct mlx5_ifc_teardown_hca_out_bits {
3996 u8 reserved_at_8[0x18];
4000 u8 reserved_at_40[0x3f];
4006 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
4007 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
4008 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4011 struct mlx5_ifc_teardown_hca_in_bits {
4013 u8 reserved_at_10[0x10];
4015 u8 reserved_at_20[0x10];
4018 u8 reserved_at_40[0x10];
4021 u8 reserved_at_60[0x20];
4024 struct mlx5_ifc_sqerr2rts_qp_out_bits {
4026 u8 reserved_at_8[0x18];
4030 u8 reserved_at_40[0x40];
4033 struct mlx5_ifc_sqerr2rts_qp_in_bits {
4037 u8 reserved_at_20[0x10];
4040 u8 reserved_at_40[0x8];
4043 u8 reserved_at_60[0x20];
4045 u8 opt_param_mask[0x20];
4047 u8 reserved_at_a0[0x20];
4049 struct mlx5_ifc_qpc_bits qpc;
4051 u8 reserved_at_800[0x80];
4054 struct mlx5_ifc_sqd2rts_qp_out_bits {
4056 u8 reserved_at_8[0x18];
4060 u8 reserved_at_40[0x40];
4063 struct mlx5_ifc_sqd2rts_qp_in_bits {
4067 u8 reserved_at_20[0x10];
4070 u8 reserved_at_40[0x8];
4073 u8 reserved_at_60[0x20];
4075 u8 opt_param_mask[0x20];
4077 u8 reserved_at_a0[0x20];
4079 struct mlx5_ifc_qpc_bits qpc;
4081 u8 reserved_at_800[0x80];
4084 struct mlx5_ifc_set_roce_address_out_bits {
4086 u8 reserved_at_8[0x18];
4090 u8 reserved_at_40[0x40];
4093 struct mlx5_ifc_set_roce_address_in_bits {
4095 u8 reserved_at_10[0x10];
4097 u8 reserved_at_20[0x10];
4100 u8 roce_address_index[0x10];
4101 u8 reserved_at_50[0xc];
4102 u8 vhca_port_num[0x4];
4104 u8 reserved_at_60[0x20];
4106 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4109 struct mlx5_ifc_set_mad_demux_out_bits {
4111 u8 reserved_at_8[0x18];
4115 u8 reserved_at_40[0x40];
4119 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
4120 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
4123 struct mlx5_ifc_set_mad_demux_in_bits {
4125 u8 reserved_at_10[0x10];
4127 u8 reserved_at_20[0x10];
4130 u8 reserved_at_40[0x20];
4132 u8 reserved_at_60[0x6];
4134 u8 reserved_at_68[0x18];
4137 struct mlx5_ifc_set_l2_table_entry_out_bits {
4139 u8 reserved_at_8[0x18];
4143 u8 reserved_at_40[0x40];
4146 struct mlx5_ifc_set_l2_table_entry_in_bits {
4148 u8 reserved_at_10[0x10];
4150 u8 reserved_at_20[0x10];
4153 u8 reserved_at_40[0x60];
4155 u8 reserved_at_a0[0x8];
4156 u8 table_index[0x18];
4158 u8 reserved_at_c0[0x20];
4160 u8 reserved_at_e0[0x13];
4164 struct mlx5_ifc_mac_address_layout_bits mac_address;
4166 u8 reserved_at_140[0xc0];
4169 struct mlx5_ifc_set_issi_out_bits {
4171 u8 reserved_at_8[0x18];
4175 u8 reserved_at_40[0x40];
4178 struct mlx5_ifc_set_issi_in_bits {
4180 u8 reserved_at_10[0x10];
4182 u8 reserved_at_20[0x10];
4185 u8 reserved_at_40[0x10];
4186 u8 current_issi[0x10];
4188 u8 reserved_at_60[0x20];
4191 struct mlx5_ifc_set_hca_cap_out_bits {
4193 u8 reserved_at_8[0x18];
4197 u8 reserved_at_40[0x40];
4200 struct mlx5_ifc_set_hca_cap_in_bits {
4202 u8 reserved_at_10[0x10];
4204 u8 reserved_at_20[0x10];
4207 u8 reserved_at_40[0x40];
4209 union mlx5_ifc_hca_cap_union_bits capability;
4213 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
4214 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
4215 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
4216 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3,
4217 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4
4220 struct mlx5_ifc_set_fte_out_bits {
4222 u8 reserved_at_8[0x18];
4226 u8 reserved_at_40[0x40];
4229 struct mlx5_ifc_set_fte_in_bits {
4231 u8 reserved_at_10[0x10];
4233 u8 reserved_at_20[0x10];
4236 u8 other_vport[0x1];
4237 u8 reserved_at_41[0xf];
4238 u8 vport_number[0x10];
4240 u8 reserved_at_60[0x20];
4243 u8 reserved_at_88[0x18];
4245 u8 reserved_at_a0[0x8];
4248 u8 ignore_flow_level[0x1];
4249 u8 reserved_at_c1[0x17];
4250 u8 modify_enable_mask[0x8];
4252 u8 reserved_at_e0[0x20];
4254 u8 flow_index[0x20];
4256 u8 reserved_at_120[0xe0];
4258 struct mlx5_ifc_flow_context_bits flow_context;
4261 struct mlx5_ifc_rts2rts_qp_out_bits {
4263 u8 reserved_at_8[0x18];
4267 u8 reserved_at_40[0x20];
4271 struct mlx5_ifc_rts2rts_qp_in_bits {
4275 u8 reserved_at_20[0x10];
4278 u8 reserved_at_40[0x8];
4281 u8 reserved_at_60[0x20];
4283 u8 opt_param_mask[0x20];
4287 struct mlx5_ifc_qpc_bits qpc;
4289 u8 reserved_at_800[0x80];
4292 struct mlx5_ifc_rtr2rts_qp_out_bits {
4294 u8 reserved_at_8[0x18];
4298 u8 reserved_at_40[0x20];
4302 struct mlx5_ifc_rtr2rts_qp_in_bits {
4306 u8 reserved_at_20[0x10];
4309 u8 reserved_at_40[0x8];
4312 u8 reserved_at_60[0x20];
4314 u8 opt_param_mask[0x20];
4318 struct mlx5_ifc_qpc_bits qpc;
4320 u8 reserved_at_800[0x80];
4323 struct mlx5_ifc_rst2init_qp_out_bits {
4325 u8 reserved_at_8[0x18];
4329 u8 reserved_at_40[0x20];
4333 struct mlx5_ifc_rst2init_qp_in_bits {
4337 u8 reserved_at_20[0x10];
4340 u8 reserved_at_40[0x8];
4343 u8 reserved_at_60[0x20];
4345 u8 opt_param_mask[0x20];
4349 struct mlx5_ifc_qpc_bits qpc;
4351 u8 reserved_at_800[0x80];
4354 struct mlx5_ifc_query_xrq_out_bits {
4356 u8 reserved_at_8[0x18];
4360 u8 reserved_at_40[0x40];
4362 struct mlx5_ifc_xrqc_bits xrq_context;
4365 struct mlx5_ifc_query_xrq_in_bits {
4367 u8 reserved_at_10[0x10];
4369 u8 reserved_at_20[0x10];
4372 u8 reserved_at_40[0x8];
4375 u8 reserved_at_60[0x20];
4378 struct mlx5_ifc_query_xrc_srq_out_bits {
4380 u8 reserved_at_8[0x18];
4384 u8 reserved_at_40[0x40];
4386 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4388 u8 reserved_at_280[0x600];
4393 struct mlx5_ifc_query_xrc_srq_in_bits {
4395 u8 reserved_at_10[0x10];
4397 u8 reserved_at_20[0x10];
4400 u8 reserved_at_40[0x8];
4403 u8 reserved_at_60[0x20];
4407 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
4408 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
4411 struct mlx5_ifc_query_vport_state_out_bits {
4413 u8 reserved_at_8[0x18];
4417 u8 reserved_at_40[0x20];
4419 u8 reserved_at_60[0x18];
4420 u8 admin_state[0x4];
4425 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
4426 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
4427 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2,
4430 struct mlx5_ifc_arm_monitor_counter_in_bits {
4434 u8 reserved_at_20[0x10];
4437 u8 reserved_at_40[0x20];
4439 u8 reserved_at_60[0x20];
4442 struct mlx5_ifc_arm_monitor_counter_out_bits {
4444 u8 reserved_at_8[0x18];
4448 u8 reserved_at_40[0x40];
4452 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
4453 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4456 enum mlx5_monitor_counter_ppcnt {
4457 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
4458 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
4459 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
4460 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4461 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
4462 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
4466 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
4469 struct mlx5_ifc_monitor_counter_output_bits {
4470 u8 reserved_at_0[0x4];
4472 u8 reserved_at_8[0x8];
4475 u8 counter_group_id[0x20];
4478 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4479 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
4480 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4481 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4483 struct mlx5_ifc_set_monitor_counter_in_bits {
4487 u8 reserved_at_20[0x10];
4490 u8 reserved_at_40[0x10];
4491 u8 num_of_counters[0x10];
4493 u8 reserved_at_60[0x20];
4495 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4498 struct mlx5_ifc_set_monitor_counter_out_bits {
4500 u8 reserved_at_8[0x18];
4504 u8 reserved_at_40[0x40];
4507 struct mlx5_ifc_query_vport_state_in_bits {
4509 u8 reserved_at_10[0x10];
4511 u8 reserved_at_20[0x10];
4514 u8 other_vport[0x1];
4515 u8 reserved_at_41[0xf];
4516 u8 vport_number[0x10];
4518 u8 reserved_at_60[0x20];
4521 struct mlx5_ifc_query_vnic_env_out_bits {
4523 u8 reserved_at_8[0x18];
4527 u8 reserved_at_40[0x40];
4529 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4533 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
4536 struct mlx5_ifc_query_vnic_env_in_bits {
4538 u8 reserved_at_10[0x10];
4540 u8 reserved_at_20[0x10];
4543 u8 other_vport[0x1];
4544 u8 reserved_at_41[0xf];
4545 u8 vport_number[0x10];
4547 u8 reserved_at_60[0x20];
4550 struct mlx5_ifc_query_vport_counter_out_bits {
4552 u8 reserved_at_8[0x18];
4556 u8 reserved_at_40[0x40];
4558 struct mlx5_ifc_traffic_counter_bits received_errors;
4560 struct mlx5_ifc_traffic_counter_bits transmit_errors;
4562 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4564 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4566 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4568 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4570 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4572 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4574 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4576 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4578 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4580 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4582 u8 reserved_at_680[0xa00];
4586 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
4589 struct mlx5_ifc_query_vport_counter_in_bits {
4591 u8 reserved_at_10[0x10];
4593 u8 reserved_at_20[0x10];
4596 u8 other_vport[0x1];
4597 u8 reserved_at_41[0xb];
4599 u8 vport_number[0x10];
4601 u8 reserved_at_60[0x60];
4604 u8 reserved_at_c1[0x1f];
4606 u8 reserved_at_e0[0x20];
4609 struct mlx5_ifc_query_tis_out_bits {
4611 u8 reserved_at_8[0x18];
4615 u8 reserved_at_40[0x40];
4617 struct mlx5_ifc_tisc_bits tis_context;
4620 struct mlx5_ifc_query_tis_in_bits {
4622 u8 reserved_at_10[0x10];
4624 u8 reserved_at_20[0x10];
4627 u8 reserved_at_40[0x8];
4630 u8 reserved_at_60[0x20];
4633 struct mlx5_ifc_query_tir_out_bits {
4635 u8 reserved_at_8[0x18];
4639 u8 reserved_at_40[0xc0];
4641 struct mlx5_ifc_tirc_bits tir_context;
4644 struct mlx5_ifc_query_tir_in_bits {
4646 u8 reserved_at_10[0x10];
4648 u8 reserved_at_20[0x10];
4651 u8 reserved_at_40[0x8];
4654 u8 reserved_at_60[0x20];
4657 struct mlx5_ifc_query_srq_out_bits {
4659 u8 reserved_at_8[0x18];
4663 u8 reserved_at_40[0x40];
4665 struct mlx5_ifc_srqc_bits srq_context_entry;
4667 u8 reserved_at_280[0x600];
4672 struct mlx5_ifc_query_srq_in_bits {
4674 u8 reserved_at_10[0x10];
4676 u8 reserved_at_20[0x10];
4679 u8 reserved_at_40[0x8];
4682 u8 reserved_at_60[0x20];
4685 struct mlx5_ifc_query_sq_out_bits {
4687 u8 reserved_at_8[0x18];
4691 u8 reserved_at_40[0xc0];
4693 struct mlx5_ifc_sqc_bits sq_context;
4696 struct mlx5_ifc_query_sq_in_bits {
4698 u8 reserved_at_10[0x10];
4700 u8 reserved_at_20[0x10];
4703 u8 reserved_at_40[0x8];
4706 u8 reserved_at_60[0x20];
4709 struct mlx5_ifc_query_special_contexts_out_bits {
4711 u8 reserved_at_8[0x18];
4715 u8 dump_fill_mkey[0x20];
4721 u8 reserved_at_a0[0x60];
4724 struct mlx5_ifc_query_special_contexts_in_bits {
4726 u8 reserved_at_10[0x10];
4728 u8 reserved_at_20[0x10];
4731 u8 reserved_at_40[0x40];
4734 struct mlx5_ifc_query_scheduling_element_out_bits {
4736 u8 reserved_at_10[0x10];
4738 u8 reserved_at_20[0x10];
4741 u8 reserved_at_40[0xc0];
4743 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4745 u8 reserved_at_300[0x100];
4749 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4752 struct mlx5_ifc_query_scheduling_element_in_bits {
4754 u8 reserved_at_10[0x10];
4756 u8 reserved_at_20[0x10];
4759 u8 scheduling_hierarchy[0x8];
4760 u8 reserved_at_48[0x18];
4762 u8 scheduling_element_id[0x20];
4764 u8 reserved_at_80[0x180];
4767 struct mlx5_ifc_query_rqt_out_bits {
4769 u8 reserved_at_8[0x18];
4773 u8 reserved_at_40[0xc0];
4775 struct mlx5_ifc_rqtc_bits rqt_context;
4778 struct mlx5_ifc_query_rqt_in_bits {
4780 u8 reserved_at_10[0x10];
4782 u8 reserved_at_20[0x10];
4785 u8 reserved_at_40[0x8];
4788 u8 reserved_at_60[0x20];
4791 struct mlx5_ifc_query_rq_out_bits {
4793 u8 reserved_at_8[0x18];
4797 u8 reserved_at_40[0xc0];
4799 struct mlx5_ifc_rqc_bits rq_context;
4802 struct mlx5_ifc_query_rq_in_bits {
4804 u8 reserved_at_10[0x10];
4806 u8 reserved_at_20[0x10];
4809 u8 reserved_at_40[0x8];
4812 u8 reserved_at_60[0x20];
4815 struct mlx5_ifc_query_roce_address_out_bits {
4817 u8 reserved_at_8[0x18];
4821 u8 reserved_at_40[0x40];
4823 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4826 struct mlx5_ifc_query_roce_address_in_bits {
4828 u8 reserved_at_10[0x10];
4830 u8 reserved_at_20[0x10];
4833 u8 roce_address_index[0x10];
4834 u8 reserved_at_50[0xc];
4835 u8 vhca_port_num[0x4];
4837 u8 reserved_at_60[0x20];
4840 struct mlx5_ifc_query_rmp_out_bits {
4842 u8 reserved_at_8[0x18];
4846 u8 reserved_at_40[0xc0];
4848 struct mlx5_ifc_rmpc_bits rmp_context;
4851 struct mlx5_ifc_query_rmp_in_bits {
4853 u8 reserved_at_10[0x10];
4855 u8 reserved_at_20[0x10];
4858 u8 reserved_at_40[0x8];
4861 u8 reserved_at_60[0x20];
4864 struct mlx5_ifc_query_qp_out_bits {
4866 u8 reserved_at_8[0x18];
4870 u8 reserved_at_40[0x20];
4873 u8 opt_param_mask[0x20];
4875 u8 reserved_at_a0[0x20];
4877 struct mlx5_ifc_qpc_bits qpc;
4879 u8 reserved_at_800[0x80];
4884 struct mlx5_ifc_query_qp_in_bits {
4886 u8 reserved_at_10[0x10];
4888 u8 reserved_at_20[0x10];
4891 u8 reserved_at_40[0x8];
4894 u8 reserved_at_60[0x20];
4897 struct mlx5_ifc_query_q_counter_out_bits {
4899 u8 reserved_at_8[0x18];
4903 u8 reserved_at_40[0x40];
4905 u8 rx_write_requests[0x20];
4907 u8 reserved_at_a0[0x20];
4909 u8 rx_read_requests[0x20];
4911 u8 reserved_at_e0[0x20];
4913 u8 rx_atomic_requests[0x20];
4915 u8 reserved_at_120[0x20];
4917 u8 rx_dct_connect[0x20];
4919 u8 reserved_at_160[0x20];
4921 u8 out_of_buffer[0x20];
4923 u8 reserved_at_1a0[0x20];
4925 u8 out_of_sequence[0x20];
4927 u8 reserved_at_1e0[0x20];
4929 u8 duplicate_request[0x20];
4931 u8 reserved_at_220[0x20];
4933 u8 rnr_nak_retry_err[0x20];
4935 u8 reserved_at_260[0x20];
4937 u8 packet_seq_err[0x20];
4939 u8 reserved_at_2a0[0x20];
4941 u8 implied_nak_seq_err[0x20];
4943 u8 reserved_at_2e0[0x20];
4945 u8 local_ack_timeout_err[0x20];
4947 u8 reserved_at_320[0xa0];
4949 u8 resp_local_length_error[0x20];
4951 u8 req_local_length_error[0x20];
4953 u8 resp_local_qp_error[0x20];
4955 u8 local_operation_error[0x20];
4957 u8 resp_local_protection[0x20];
4959 u8 req_local_protection[0x20];
4961 u8 resp_cqe_error[0x20];
4963 u8 req_cqe_error[0x20];
4965 u8 req_mw_binding[0x20];
4967 u8 req_bad_response[0x20];
4969 u8 req_remote_invalid_request[0x20];
4971 u8 resp_remote_invalid_request[0x20];
4973 u8 req_remote_access_errors[0x20];
4975 u8 resp_remote_access_errors[0x20];
4977 u8 req_remote_operation_errors[0x20];
4979 u8 req_transport_retries_exceeded[0x20];
4981 u8 cq_overflow[0x20];
4983 u8 resp_cqe_flush_error[0x20];
4985 u8 req_cqe_flush_error[0x20];
4987 u8 reserved_at_620[0x20];
4989 u8 roce_adp_retrans[0x20];
4991 u8 roce_adp_retrans_to[0x20];
4993 u8 roce_slow_restart[0x20];
4995 u8 roce_slow_restart_cnps[0x20];
4997 u8 roce_slow_restart_trans[0x20];
4999 u8 reserved_at_6e0[0x120];
5002 struct mlx5_ifc_query_q_counter_in_bits {
5004 u8 reserved_at_10[0x10];
5006 u8 reserved_at_20[0x10];
5009 u8 reserved_at_40[0x80];
5012 u8 reserved_at_c1[0x1f];
5014 u8 reserved_at_e0[0x18];
5015 u8 counter_set_id[0x8];
5018 struct mlx5_ifc_query_pages_out_bits {
5020 u8 reserved_at_8[0x18];
5024 u8 embedded_cpu_function[0x1];
5025 u8 reserved_at_41[0xf];
5026 u8 function_id[0x10];
5032 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
5033 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
5034 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
5037 struct mlx5_ifc_query_pages_in_bits {
5039 u8 reserved_at_10[0x10];
5041 u8 reserved_at_20[0x10];
5044 u8 embedded_cpu_function[0x1];
5045 u8 reserved_at_41[0xf];
5046 u8 function_id[0x10];
5048 u8 reserved_at_60[0x20];
5051 struct mlx5_ifc_query_nic_vport_context_out_bits {
5053 u8 reserved_at_8[0x18];
5057 u8 reserved_at_40[0x40];
5059 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5062 struct mlx5_ifc_query_nic_vport_context_in_bits {
5064 u8 reserved_at_10[0x10];
5066 u8 reserved_at_20[0x10];
5069 u8 other_vport[0x1];
5070 u8 reserved_at_41[0xf];
5071 u8 vport_number[0x10];
5073 u8 reserved_at_60[0x5];
5074 u8 allowed_list_type[0x3];
5075 u8 reserved_at_68[0x18];
5078 struct mlx5_ifc_query_mkey_out_bits {
5080 u8 reserved_at_8[0x18];
5084 u8 reserved_at_40[0x40];
5086 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5088 u8 reserved_at_280[0x600];
5090 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
5092 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
5095 struct mlx5_ifc_query_mkey_in_bits {
5097 u8 reserved_at_10[0x10];
5099 u8 reserved_at_20[0x10];
5102 u8 reserved_at_40[0x8];
5103 u8 mkey_index[0x18];
5106 u8 reserved_at_61[0x1f];
5109 struct mlx5_ifc_query_mad_demux_out_bits {
5111 u8 reserved_at_8[0x18];
5115 u8 reserved_at_40[0x40];
5117 u8 mad_dumux_parameters_block[0x20];
5120 struct mlx5_ifc_query_mad_demux_in_bits {
5122 u8 reserved_at_10[0x10];
5124 u8 reserved_at_20[0x10];
5127 u8 reserved_at_40[0x40];
5130 struct mlx5_ifc_query_l2_table_entry_out_bits {
5132 u8 reserved_at_8[0x18];
5136 u8 reserved_at_40[0xa0];
5138 u8 reserved_at_e0[0x13];
5142 struct mlx5_ifc_mac_address_layout_bits mac_address;
5144 u8 reserved_at_140[0xc0];
5147 struct mlx5_ifc_query_l2_table_entry_in_bits {
5149 u8 reserved_at_10[0x10];
5151 u8 reserved_at_20[0x10];
5154 u8 reserved_at_40[0x60];
5156 u8 reserved_at_a0[0x8];
5157 u8 table_index[0x18];
5159 u8 reserved_at_c0[0x140];
5162 struct mlx5_ifc_query_issi_out_bits {
5164 u8 reserved_at_8[0x18];
5168 u8 reserved_at_40[0x10];
5169 u8 current_issi[0x10];
5171 u8 reserved_at_60[0xa0];
5173 u8 reserved_at_100[76][0x8];
5174 u8 supported_issi_dw0[0x20];
5177 struct mlx5_ifc_query_issi_in_bits {
5179 u8 reserved_at_10[0x10];
5181 u8 reserved_at_20[0x10];
5184 u8 reserved_at_40[0x40];
5187 struct mlx5_ifc_set_driver_version_out_bits {
5189 u8 reserved_0[0x18];
5192 u8 reserved_1[0x40];
5195 struct mlx5_ifc_set_driver_version_in_bits {
5197 u8 reserved_0[0x10];
5199 u8 reserved_1[0x10];
5202 u8 reserved_2[0x40];
5203 u8 driver_version[64][0x8];
5206 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5208 u8 reserved_at_8[0x18];
5212 u8 reserved_at_40[0x40];
5214 struct mlx5_ifc_pkey_bits pkey[];
5217 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5219 u8 reserved_at_10[0x10];
5221 u8 reserved_at_20[0x10];
5224 u8 other_vport[0x1];
5225 u8 reserved_at_41[0xb];
5227 u8 vport_number[0x10];
5229 u8 reserved_at_60[0x10];
5230 u8 pkey_index[0x10];
5234 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
5235 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
5236 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5239 struct mlx5_ifc_query_hca_vport_gid_out_bits {
5241 u8 reserved_at_8[0x18];
5245 u8 reserved_at_40[0x20];
5248 u8 reserved_at_70[0x10];
5250 struct mlx5_ifc_array128_auto_bits gid[];
5253 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5255 u8 reserved_at_10[0x10];
5257 u8 reserved_at_20[0x10];
5260 u8 other_vport[0x1];
5261 u8 reserved_at_41[0xb];
5263 u8 vport_number[0x10];
5265 u8 reserved_at_60[0x10];
5269 struct mlx5_ifc_query_hca_vport_context_out_bits {
5271 u8 reserved_at_8[0x18];
5275 u8 reserved_at_40[0x40];
5277 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5280 struct mlx5_ifc_query_hca_vport_context_in_bits {
5282 u8 reserved_at_10[0x10];
5284 u8 reserved_at_20[0x10];
5287 u8 other_vport[0x1];
5288 u8 reserved_at_41[0xb];
5290 u8 vport_number[0x10];
5292 u8 reserved_at_60[0x20];
5295 struct mlx5_ifc_query_hca_cap_out_bits {
5297 u8 reserved_at_8[0x18];
5301 u8 reserved_at_40[0x40];
5303 union mlx5_ifc_hca_cap_union_bits capability;
5306 struct mlx5_ifc_query_hca_cap_in_bits {
5308 u8 reserved_at_10[0x10];
5310 u8 reserved_at_20[0x10];
5313 u8 other_function[0x1];
5314 u8 reserved_at_41[0xf];
5315 u8 function_id[0x10];
5317 u8 reserved_at_60[0x20];
5320 struct mlx5_ifc_other_hca_cap_bits {
5322 u8 reserved_at_1[0x27f];
5325 struct mlx5_ifc_query_other_hca_cap_out_bits {
5327 u8 reserved_at_8[0x18];
5331 u8 reserved_at_40[0x40];
5333 struct mlx5_ifc_other_hca_cap_bits other_capability;
5336 struct mlx5_ifc_query_other_hca_cap_in_bits {
5338 u8 reserved_at_10[0x10];
5340 u8 reserved_at_20[0x10];
5343 u8 reserved_at_40[0x10];
5344 u8 function_id[0x10];
5346 u8 reserved_at_60[0x20];
5349 struct mlx5_ifc_modify_other_hca_cap_out_bits {
5351 u8 reserved_at_8[0x18];
5355 u8 reserved_at_40[0x40];
5358 struct mlx5_ifc_modify_other_hca_cap_in_bits {
5360 u8 reserved_at_10[0x10];
5362 u8 reserved_at_20[0x10];
5365 u8 reserved_at_40[0x10];
5366 u8 function_id[0x10];
5367 u8 field_select[0x20];
5369 struct mlx5_ifc_other_hca_cap_bits other_capability;
5372 struct mlx5_ifc_flow_table_context_bits {
5373 u8 reformat_en[0x1];
5376 u8 termination_table[0x1];
5377 u8 table_miss_action[0x4];
5379 u8 reserved_at_10[0x8];
5382 u8 reserved_at_20[0x8];
5383 u8 table_miss_id[0x18];
5385 u8 reserved_at_40[0x8];
5386 u8 lag_master_next_table_id[0x18];
5388 u8 reserved_at_60[0x60];
5390 u8 sw_owner_icm_root_1[0x40];
5392 u8 sw_owner_icm_root_0[0x40];
5396 struct mlx5_ifc_query_flow_table_out_bits {
5398 u8 reserved_at_8[0x18];
5402 u8 reserved_at_40[0x80];
5404 struct mlx5_ifc_flow_table_context_bits flow_table_context;
5407 struct mlx5_ifc_query_flow_table_in_bits {
5409 u8 reserved_at_10[0x10];
5411 u8 reserved_at_20[0x10];
5414 u8 reserved_at_40[0x40];
5417 u8 reserved_at_88[0x18];
5419 u8 reserved_at_a0[0x8];
5422 u8 reserved_at_c0[0x140];
5425 struct mlx5_ifc_query_fte_out_bits {
5427 u8 reserved_at_8[0x18];
5431 u8 reserved_at_40[0x1c0];
5433 struct mlx5_ifc_flow_context_bits flow_context;
5436 struct mlx5_ifc_query_fte_in_bits {
5438 u8 reserved_at_10[0x10];
5440 u8 reserved_at_20[0x10];
5443 u8 reserved_at_40[0x40];
5446 u8 reserved_at_88[0x18];
5448 u8 reserved_at_a0[0x8];
5451 u8 reserved_at_c0[0x40];
5453 u8 flow_index[0x20];
5455 u8 reserved_at_120[0xe0];
5459 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5460 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5461 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5462 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
5463 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
5466 struct mlx5_ifc_query_flow_group_out_bits {
5468 u8 reserved_at_8[0x18];
5472 u8 reserved_at_40[0xa0];
5474 u8 start_flow_index[0x20];
5476 u8 reserved_at_100[0x20];
5478 u8 end_flow_index[0x20];
5480 u8 reserved_at_140[0xa0];
5482 u8 reserved_at_1e0[0x18];
5483 u8 match_criteria_enable[0x8];
5485 struct mlx5_ifc_fte_match_param_bits match_criteria;
5487 u8 reserved_at_1200[0xe00];
5490 struct mlx5_ifc_query_flow_group_in_bits {
5492 u8 reserved_at_10[0x10];
5494 u8 reserved_at_20[0x10];
5497 u8 reserved_at_40[0x40];
5500 u8 reserved_at_88[0x18];
5502 u8 reserved_at_a0[0x8];
5507 u8 reserved_at_e0[0x120];
5510 struct mlx5_ifc_query_flow_counter_out_bits {
5512 u8 reserved_at_8[0x18];
5516 u8 reserved_at_40[0x40];
5518 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
5521 struct mlx5_ifc_query_flow_counter_in_bits {
5523 u8 reserved_at_10[0x10];
5525 u8 reserved_at_20[0x10];
5528 u8 reserved_at_40[0x80];
5531 u8 reserved_at_c1[0xf];
5532 u8 num_of_counters[0x10];
5534 u8 flow_counter_id[0x20];
5537 struct mlx5_ifc_query_esw_vport_context_out_bits {
5539 u8 reserved_at_8[0x18];
5543 u8 reserved_at_40[0x40];
5545 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5548 struct mlx5_ifc_query_esw_vport_context_in_bits {
5550 u8 reserved_at_10[0x10];
5552 u8 reserved_at_20[0x10];
5555 u8 other_vport[0x1];
5556 u8 reserved_at_41[0xf];
5557 u8 vport_number[0x10];
5559 u8 reserved_at_60[0x20];
5562 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5564 u8 reserved_at_8[0x18];
5568 u8 reserved_at_40[0x40];
5571 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5572 u8 reserved_at_0[0x1b];
5573 u8 fdb_to_vport_reg_c_id[0x1];
5574 u8 vport_cvlan_insert[0x1];
5575 u8 vport_svlan_insert[0x1];
5576 u8 vport_cvlan_strip[0x1];
5577 u8 vport_svlan_strip[0x1];
5580 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5582 u8 reserved_at_10[0x10];
5584 u8 reserved_at_20[0x10];
5587 u8 other_vport[0x1];
5588 u8 reserved_at_41[0xf];
5589 u8 vport_number[0x10];
5591 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5593 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5596 struct mlx5_ifc_query_eq_out_bits {
5598 u8 reserved_at_8[0x18];
5602 u8 reserved_at_40[0x40];
5604 struct mlx5_ifc_eqc_bits eq_context_entry;
5606 u8 reserved_at_280[0x40];
5608 u8 event_bitmask[0x40];
5610 u8 reserved_at_300[0x580];
5615 struct mlx5_ifc_query_eq_in_bits {
5617 u8 reserved_at_10[0x10];
5619 u8 reserved_at_20[0x10];
5622 u8 reserved_at_40[0x18];
5625 u8 reserved_at_60[0x20];
5628 struct mlx5_ifc_packet_reformat_context_in_bits {
5629 u8 reserved_at_0[0x5];
5630 u8 reformat_type[0x3];
5631 u8 reserved_at_8[0xe];
5632 u8 reformat_data_size[0xa];
5634 u8 reserved_at_20[0x10];
5635 u8 reformat_data[2][0x8];
5637 u8 more_reformat_data[][0x8];
5640 struct mlx5_ifc_query_packet_reformat_context_out_bits {
5642 u8 reserved_at_8[0x18];
5646 u8 reserved_at_40[0xa0];
5648 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
5651 struct mlx5_ifc_query_packet_reformat_context_in_bits {
5653 u8 reserved_at_10[0x10];
5655 u8 reserved_at_20[0x10];
5658 u8 packet_reformat_id[0x20];
5660 u8 reserved_at_60[0xa0];
5663 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5665 u8 reserved_at_8[0x18];
5669 u8 packet_reformat_id[0x20];
5671 u8 reserved_at_60[0x20];
5674 enum mlx5_reformat_ctx_type {
5675 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5676 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5677 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5678 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5679 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5682 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5684 u8 reserved_at_10[0x10];
5686 u8 reserved_at_20[0x10];
5689 u8 reserved_at_40[0xa0];
5691 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5694 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5696 u8 reserved_at_8[0x18];
5700 u8 reserved_at_40[0x40];
5703 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5705 u8 reserved_at_10[0x10];
5707 u8 reserved_20[0x10];
5710 u8 packet_reformat_id[0x20];
5712 u8 reserved_60[0x20];
5715 struct mlx5_ifc_set_action_in_bits {
5716 u8 action_type[0x4];
5718 u8 reserved_at_10[0x3];
5720 u8 reserved_at_18[0x3];
5726 struct mlx5_ifc_add_action_in_bits {
5727 u8 action_type[0x4];
5729 u8 reserved_at_10[0x10];
5734 struct mlx5_ifc_copy_action_in_bits {
5735 u8 action_type[0x4];
5737 u8 reserved_at_10[0x3];
5739 u8 reserved_at_18[0x3];
5742 u8 reserved_at_20[0x4];
5744 u8 reserved_at_30[0x3];
5746 u8 reserved_at_38[0x8];
5749 union mlx5_ifc_set_add_copy_action_in_auto_bits {
5750 struct mlx5_ifc_set_action_in_bits set_action_in;
5751 struct mlx5_ifc_add_action_in_bits add_action_in;
5752 struct mlx5_ifc_copy_action_in_bits copy_action_in;
5753 u8 reserved_at_0[0x40];
5757 MLX5_ACTION_TYPE_SET = 0x1,
5758 MLX5_ACTION_TYPE_ADD = 0x2,
5759 MLX5_ACTION_TYPE_COPY = 0x3,
5763 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
5764 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
5765 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
5766 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
5767 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
5768 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
5769 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
5770 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
5771 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
5772 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
5773 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
5774 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
5775 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
5776 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
5777 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
5778 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
5779 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
5780 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
5781 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
5782 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
5783 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
5784 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
5785 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
5786 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5787 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49,
5788 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50,
5789 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
5790 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52,
5791 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53,
5792 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
5793 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
5794 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
5795 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57,
5796 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58,
5797 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
5798 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
5799 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D,
5802 struct mlx5_ifc_alloc_modify_header_context_out_bits {
5804 u8 reserved_at_8[0x18];
5808 u8 modify_header_id[0x20];
5810 u8 reserved_at_60[0x20];
5813 struct mlx5_ifc_alloc_modify_header_context_in_bits {
5815 u8 reserved_at_10[0x10];
5817 u8 reserved_at_20[0x10];
5820 u8 reserved_at_40[0x20];
5823 u8 reserved_at_68[0x10];
5824 u8 num_of_actions[0x8];
5826 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[0];
5829 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5831 u8 reserved_at_8[0x18];
5835 u8 reserved_at_40[0x40];
5838 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5840 u8 reserved_at_10[0x10];
5842 u8 reserved_at_20[0x10];
5845 u8 modify_header_id[0x20];
5847 u8 reserved_at_60[0x20];
5850 struct mlx5_ifc_query_dct_out_bits {
5852 u8 reserved_at_8[0x18];
5856 u8 reserved_at_40[0x40];
5858 struct mlx5_ifc_dctc_bits dct_context_entry;
5860 u8 reserved_at_280[0x180];
5863 struct mlx5_ifc_query_dct_in_bits {
5865 u8 reserved_at_10[0x10];
5867 u8 reserved_at_20[0x10];
5870 u8 reserved_at_40[0x8];
5873 u8 reserved_at_60[0x20];
5876 struct mlx5_ifc_query_cq_out_bits {
5878 u8 reserved_at_8[0x18];
5882 u8 reserved_at_40[0x40];
5884 struct mlx5_ifc_cqc_bits cq_context;
5886 u8 reserved_at_280[0x600];
5891 struct mlx5_ifc_query_cq_in_bits {
5893 u8 reserved_at_10[0x10];
5895 u8 reserved_at_20[0x10];
5898 u8 reserved_at_40[0x8];
5901 u8 reserved_at_60[0x20];
5904 struct mlx5_ifc_query_cong_status_out_bits {
5906 u8 reserved_at_8[0x18];
5910 u8 reserved_at_40[0x20];
5914 u8 reserved_at_62[0x1e];
5917 struct mlx5_ifc_query_cong_status_in_bits {
5919 u8 reserved_at_10[0x10];
5921 u8 reserved_at_20[0x10];
5924 u8 reserved_at_40[0x18];
5926 u8 cong_protocol[0x4];
5928 u8 reserved_at_60[0x20];
5931 struct mlx5_ifc_query_cong_statistics_out_bits {
5933 u8 reserved_at_8[0x18];
5937 u8 reserved_at_40[0x40];
5939 u8 rp_cur_flows[0x20];
5943 u8 rp_cnp_ignored_high[0x20];
5945 u8 rp_cnp_ignored_low[0x20];
5947 u8 rp_cnp_handled_high[0x20];
5949 u8 rp_cnp_handled_low[0x20];
5951 u8 reserved_at_140[0x100];
5953 u8 time_stamp_high[0x20];
5955 u8 time_stamp_low[0x20];
5957 u8 accumulators_period[0x20];
5959 u8 np_ecn_marked_roce_packets_high[0x20];
5961 u8 np_ecn_marked_roce_packets_low[0x20];
5963 u8 np_cnp_sent_high[0x20];
5965 u8 np_cnp_sent_low[0x20];
5967 u8 reserved_at_320[0x560];
5970 struct mlx5_ifc_query_cong_statistics_in_bits {
5972 u8 reserved_at_10[0x10];
5974 u8 reserved_at_20[0x10];
5978 u8 reserved_at_41[0x1f];
5980 u8 reserved_at_60[0x20];
5983 struct mlx5_ifc_query_cong_params_out_bits {
5985 u8 reserved_at_8[0x18];
5989 u8 reserved_at_40[0x40];
5991 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5994 struct mlx5_ifc_query_cong_params_in_bits {
5996 u8 reserved_at_10[0x10];
5998 u8 reserved_at_20[0x10];
6001 u8 reserved_at_40[0x1c];
6002 u8 cong_protocol[0x4];
6004 u8 reserved_at_60[0x20];
6007 struct mlx5_ifc_query_adapter_out_bits {
6009 u8 reserved_at_8[0x18];
6013 u8 reserved_at_40[0x40];
6015 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
6018 struct mlx5_ifc_query_adapter_in_bits {
6020 u8 reserved_at_10[0x10];
6022 u8 reserved_at_20[0x10];
6025 u8 reserved_at_40[0x40];
6028 struct mlx5_ifc_qp_2rst_out_bits {
6030 u8 reserved_at_8[0x18];
6034 u8 reserved_at_40[0x40];
6037 struct mlx5_ifc_qp_2rst_in_bits {
6041 u8 reserved_at_20[0x10];
6044 u8 reserved_at_40[0x8];
6047 u8 reserved_at_60[0x20];
6050 struct mlx5_ifc_qp_2err_out_bits {
6052 u8 reserved_at_8[0x18];
6056 u8 reserved_at_40[0x40];
6059 struct mlx5_ifc_qp_2err_in_bits {
6063 u8 reserved_at_20[0x10];
6066 u8 reserved_at_40[0x8];
6069 u8 reserved_at_60[0x20];
6072 struct mlx5_ifc_page_fault_resume_out_bits {
6074 u8 reserved_at_8[0x18];
6078 u8 reserved_at_40[0x40];
6081 struct mlx5_ifc_page_fault_resume_in_bits {
6083 u8 reserved_at_10[0x10];
6085 u8 reserved_at_20[0x10];
6089 u8 reserved_at_41[0x4];
6090 u8 page_fault_type[0x3];
6093 u8 reserved_at_60[0x8];
6097 struct mlx5_ifc_nop_out_bits {
6099 u8 reserved_at_8[0x18];
6103 u8 reserved_at_40[0x40];
6106 struct mlx5_ifc_nop_in_bits {
6108 u8 reserved_at_10[0x10];
6110 u8 reserved_at_20[0x10];
6113 u8 reserved_at_40[0x40];
6116 struct mlx5_ifc_modify_vport_state_out_bits {
6118 u8 reserved_at_8[0x18];
6122 u8 reserved_at_40[0x40];
6125 struct mlx5_ifc_modify_vport_state_in_bits {
6127 u8 reserved_at_10[0x10];
6129 u8 reserved_at_20[0x10];
6132 u8 other_vport[0x1];
6133 u8 reserved_at_41[0xf];
6134 u8 vport_number[0x10];
6136 u8 reserved_at_60[0x18];
6137 u8 admin_state[0x4];
6138 u8 reserved_at_7c[0x4];
6141 struct mlx5_ifc_modify_tis_out_bits {
6143 u8 reserved_at_8[0x18];
6147 u8 reserved_at_40[0x40];
6150 struct mlx5_ifc_modify_tis_bitmask_bits {
6151 u8 reserved_at_0[0x20];
6153 u8 reserved_at_20[0x1d];
6154 u8 lag_tx_port_affinity[0x1];
6155 u8 strict_lag_tx_port_affinity[0x1];
6159 struct mlx5_ifc_modify_tis_in_bits {
6163 u8 reserved_at_20[0x10];
6166 u8 reserved_at_40[0x8];
6169 u8 reserved_at_60[0x20];
6171 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
6173 u8 reserved_at_c0[0x40];
6175 struct mlx5_ifc_tisc_bits ctx;
6178 struct mlx5_ifc_modify_tir_bitmask_bits {
6179 u8 reserved_at_0[0x20];
6181 u8 reserved_at_20[0x1b];
6183 u8 reserved_at_3c[0x1];
6185 u8 reserved_at_3e[0x1];
6189 struct mlx5_ifc_modify_tir_out_bits {
6191 u8 reserved_at_8[0x18];
6195 u8 reserved_at_40[0x40];
6198 struct mlx5_ifc_modify_tir_in_bits {
6202 u8 reserved_at_20[0x10];
6205 u8 reserved_at_40[0x8];
6208 u8 reserved_at_60[0x20];
6210 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
6212 u8 reserved_at_c0[0x40];
6214 struct mlx5_ifc_tirc_bits ctx;
6217 struct mlx5_ifc_modify_sq_out_bits {
6219 u8 reserved_at_8[0x18];
6223 u8 reserved_at_40[0x40];
6226 struct mlx5_ifc_modify_sq_in_bits {
6230 u8 reserved_at_20[0x10];
6234 u8 reserved_at_44[0x4];
6237 u8 reserved_at_60[0x20];
6239 u8 modify_bitmask[0x40];
6241 u8 reserved_at_c0[0x40];
6243 struct mlx5_ifc_sqc_bits ctx;
6246 struct mlx5_ifc_modify_scheduling_element_out_bits {
6248 u8 reserved_at_8[0x18];
6252 u8 reserved_at_40[0x1c0];
6256 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
6257 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
6260 struct mlx5_ifc_modify_scheduling_element_in_bits {
6262 u8 reserved_at_10[0x10];
6264 u8 reserved_at_20[0x10];
6267 u8 scheduling_hierarchy[0x8];
6268 u8 reserved_at_48[0x18];
6270 u8 scheduling_element_id[0x20];
6272 u8 reserved_at_80[0x20];
6274 u8 modify_bitmask[0x20];
6276 u8 reserved_at_c0[0x40];
6278 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6280 u8 reserved_at_300[0x100];
6283 struct mlx5_ifc_modify_rqt_out_bits {
6285 u8 reserved_at_8[0x18];
6289 u8 reserved_at_40[0x40];
6292 struct mlx5_ifc_rqt_bitmask_bits {
6293 u8 reserved_at_0[0x20];
6295 u8 reserved_at_20[0x1f];
6299 struct mlx5_ifc_modify_rqt_in_bits {
6303 u8 reserved_at_20[0x10];
6306 u8 reserved_at_40[0x8];
6309 u8 reserved_at_60[0x20];
6311 struct mlx5_ifc_rqt_bitmask_bits bitmask;
6313 u8 reserved_at_c0[0x40];
6315 struct mlx5_ifc_rqtc_bits ctx;
6318 struct mlx5_ifc_modify_rq_out_bits {
6320 u8 reserved_at_8[0x18];
6324 u8 reserved_at_40[0x40];
6328 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
6329 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
6330 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
6333 struct mlx5_ifc_modify_rq_in_bits {
6337 u8 reserved_at_20[0x10];
6341 u8 reserved_at_44[0x4];
6344 u8 reserved_at_60[0x20];
6346 u8 modify_bitmask[0x40];
6348 u8 reserved_at_c0[0x40];
6350 struct mlx5_ifc_rqc_bits ctx;
6353 struct mlx5_ifc_modify_rmp_out_bits {
6355 u8 reserved_at_8[0x18];
6359 u8 reserved_at_40[0x40];
6362 struct mlx5_ifc_rmp_bitmask_bits {
6363 u8 reserved_at_0[0x20];
6365 u8 reserved_at_20[0x1f];
6369 struct mlx5_ifc_modify_rmp_in_bits {
6373 u8 reserved_at_20[0x10];
6377 u8 reserved_at_44[0x4];
6380 u8 reserved_at_60[0x20];
6382 struct mlx5_ifc_rmp_bitmask_bits bitmask;
6384 u8 reserved_at_c0[0x40];
6386 struct mlx5_ifc_rmpc_bits ctx;
6389 struct mlx5_ifc_modify_nic_vport_context_out_bits {
6391 u8 reserved_at_8[0x18];
6395 u8 reserved_at_40[0x40];
6398 struct mlx5_ifc_modify_nic_vport_field_select_bits {
6399 u8 reserved_at_0[0x12];
6400 u8 affiliation[0x1];
6401 u8 reserved_at_13[0x1];
6402 u8 disable_uc_local_lb[0x1];
6403 u8 disable_mc_local_lb[0x1];
6408 u8 change_event[0x1];
6410 u8 permanent_address[0x1];
6411 u8 addresses_list[0x1];
6413 u8 reserved_at_1f[0x1];
6416 struct mlx5_ifc_modify_nic_vport_context_in_bits {
6418 u8 reserved_at_10[0x10];
6420 u8 reserved_at_20[0x10];
6423 u8 other_vport[0x1];
6424 u8 reserved_at_41[0xf];
6425 u8 vport_number[0x10];
6427 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
6429 u8 reserved_at_80[0x780];
6431 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6434 struct mlx5_ifc_modify_hca_vport_context_out_bits {
6436 u8 reserved_at_8[0x18];
6440 u8 reserved_at_40[0x40];
6443 struct mlx5_ifc_modify_hca_vport_context_in_bits {
6445 u8 reserved_at_10[0x10];
6447 u8 reserved_at_20[0x10];
6450 u8 other_vport[0x1];
6451 u8 reserved_at_41[0xb];
6453 u8 vport_number[0x10];
6455 u8 reserved_at_60[0x20];
6457 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6460 struct mlx5_ifc_modify_cq_out_bits {
6462 u8 reserved_at_8[0x18];
6466 u8 reserved_at_40[0x40];
6470 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
6471 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
6474 struct mlx5_ifc_modify_cq_in_bits {
6478 u8 reserved_at_20[0x10];
6481 u8 reserved_at_40[0x8];
6484 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
6486 struct mlx5_ifc_cqc_bits cq_context;
6488 u8 reserved_at_280[0x60];
6490 u8 cq_umem_valid[0x1];
6491 u8 reserved_at_2e1[0x1f];
6493 u8 reserved_at_300[0x580];
6498 struct mlx5_ifc_modify_cong_status_out_bits {
6500 u8 reserved_at_8[0x18];
6504 u8 reserved_at_40[0x40];
6507 struct mlx5_ifc_modify_cong_status_in_bits {
6509 u8 reserved_at_10[0x10];
6511 u8 reserved_at_20[0x10];
6514 u8 reserved_at_40[0x18];
6516 u8 cong_protocol[0x4];
6520 u8 reserved_at_62[0x1e];
6523 struct mlx5_ifc_modify_cong_params_out_bits {
6525 u8 reserved_at_8[0x18];
6529 u8 reserved_at_40[0x40];
6532 struct mlx5_ifc_modify_cong_params_in_bits {
6534 u8 reserved_at_10[0x10];
6536 u8 reserved_at_20[0x10];
6539 u8 reserved_at_40[0x1c];
6540 u8 cong_protocol[0x4];
6542 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6544 u8 reserved_at_80[0x80];
6546 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6549 struct mlx5_ifc_manage_pages_out_bits {
6551 u8 reserved_at_8[0x18];
6555 u8 output_num_entries[0x20];
6557 u8 reserved_at_60[0x20];
6563 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
6564 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
6565 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
6568 struct mlx5_ifc_manage_pages_in_bits {
6570 u8 reserved_at_10[0x10];
6572 u8 reserved_at_20[0x10];
6575 u8 embedded_cpu_function[0x1];
6576 u8 reserved_at_41[0xf];
6577 u8 function_id[0x10];
6579 u8 input_num_entries[0x20];
6584 struct mlx5_ifc_mad_ifc_out_bits {
6586 u8 reserved_at_8[0x18];
6590 u8 reserved_at_40[0x40];
6592 u8 response_mad_packet[256][0x8];
6595 struct mlx5_ifc_mad_ifc_in_bits {
6597 u8 reserved_at_10[0x10];
6599 u8 reserved_at_20[0x10];
6602 u8 remote_lid[0x10];
6603 u8 reserved_at_50[0x8];
6606 u8 reserved_at_60[0x20];
6611 struct mlx5_ifc_init_hca_out_bits {
6613 u8 reserved_at_8[0x18];
6617 u8 reserved_at_40[0x40];
6620 struct mlx5_ifc_init_hca_in_bits {
6622 u8 reserved_at_10[0x10];
6624 u8 reserved_at_20[0x10];
6627 u8 reserved_at_40[0x40];
6628 u8 sw_owner_id[4][0x20];
6631 struct mlx5_ifc_init2rtr_qp_out_bits {
6633 u8 reserved_at_8[0x18];
6637 u8 reserved_at_40[0x20];
6641 struct mlx5_ifc_init2rtr_qp_in_bits {
6645 u8 reserved_at_20[0x10];
6648 u8 reserved_at_40[0x8];
6651 u8 reserved_at_60[0x20];
6653 u8 opt_param_mask[0x20];
6657 struct mlx5_ifc_qpc_bits qpc;
6659 u8 reserved_at_800[0x80];
6662 struct mlx5_ifc_init2init_qp_out_bits {
6664 u8 reserved_at_8[0x18];
6668 u8 reserved_at_40[0x20];
6672 struct mlx5_ifc_init2init_qp_in_bits {
6676 u8 reserved_at_20[0x10];
6679 u8 reserved_at_40[0x8];
6682 u8 reserved_at_60[0x20];
6684 u8 opt_param_mask[0x20];
6688 struct mlx5_ifc_qpc_bits qpc;
6690 u8 reserved_at_800[0x80];
6693 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6695 u8 reserved_at_8[0x18];
6699 u8 reserved_at_40[0x40];
6701 u8 packet_headers_log[128][0x8];
6703 u8 packet_syndrome[64][0x8];
6706 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6708 u8 reserved_at_10[0x10];
6710 u8 reserved_at_20[0x10];
6713 u8 reserved_at_40[0x40];
6716 struct mlx5_ifc_gen_eqe_in_bits {
6718 u8 reserved_at_10[0x10];
6720 u8 reserved_at_20[0x10];
6723 u8 reserved_at_40[0x18];
6726 u8 reserved_at_60[0x20];
6731 struct mlx5_ifc_gen_eq_out_bits {
6733 u8 reserved_at_8[0x18];
6737 u8 reserved_at_40[0x40];
6740 struct mlx5_ifc_enable_hca_out_bits {
6742 u8 reserved_at_8[0x18];
6746 u8 reserved_at_40[0x20];
6749 struct mlx5_ifc_enable_hca_in_bits {
6751 u8 reserved_at_10[0x10];
6753 u8 reserved_at_20[0x10];
6756 u8 embedded_cpu_function[0x1];
6757 u8 reserved_at_41[0xf];
6758 u8 function_id[0x10];
6760 u8 reserved_at_60[0x20];
6763 struct mlx5_ifc_drain_dct_out_bits {
6765 u8 reserved_at_8[0x18];
6769 u8 reserved_at_40[0x40];
6772 struct mlx5_ifc_drain_dct_in_bits {
6776 u8 reserved_at_20[0x10];
6779 u8 reserved_at_40[0x8];
6782 u8 reserved_at_60[0x20];
6785 struct mlx5_ifc_disable_hca_out_bits {
6787 u8 reserved_at_8[0x18];
6791 u8 reserved_at_40[0x20];
6794 struct mlx5_ifc_disable_hca_in_bits {
6796 u8 reserved_at_10[0x10];
6798 u8 reserved_at_20[0x10];
6801 u8 embedded_cpu_function[0x1];
6802 u8 reserved_at_41[0xf];
6803 u8 function_id[0x10];
6805 u8 reserved_at_60[0x20];
6808 struct mlx5_ifc_detach_from_mcg_out_bits {
6810 u8 reserved_at_8[0x18];
6814 u8 reserved_at_40[0x40];
6817 struct mlx5_ifc_detach_from_mcg_in_bits {
6821 u8 reserved_at_20[0x10];
6824 u8 reserved_at_40[0x8];
6827 u8 reserved_at_60[0x20];
6829 u8 multicast_gid[16][0x8];
6832 struct mlx5_ifc_destroy_xrq_out_bits {
6834 u8 reserved_at_8[0x18];
6838 u8 reserved_at_40[0x40];
6841 struct mlx5_ifc_destroy_xrq_in_bits {
6845 u8 reserved_at_20[0x10];
6848 u8 reserved_at_40[0x8];
6851 u8 reserved_at_60[0x20];
6854 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6856 u8 reserved_at_8[0x18];
6860 u8 reserved_at_40[0x40];
6863 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6867 u8 reserved_at_20[0x10];
6870 u8 reserved_at_40[0x8];
6873 u8 reserved_at_60[0x20];
6876 struct mlx5_ifc_destroy_tis_out_bits {
6878 u8 reserved_at_8[0x18];
6882 u8 reserved_at_40[0x40];
6885 struct mlx5_ifc_destroy_tis_in_bits {
6889 u8 reserved_at_20[0x10];
6892 u8 reserved_at_40[0x8];
6895 u8 reserved_at_60[0x20];
6898 struct mlx5_ifc_destroy_tir_out_bits {
6900 u8 reserved_at_8[0x18];
6904 u8 reserved_at_40[0x40];
6907 struct mlx5_ifc_destroy_tir_in_bits {
6911 u8 reserved_at_20[0x10];
6914 u8 reserved_at_40[0x8];
6917 u8 reserved_at_60[0x20];
6920 struct mlx5_ifc_destroy_srq_out_bits {
6922 u8 reserved_at_8[0x18];
6926 u8 reserved_at_40[0x40];
6929 struct mlx5_ifc_destroy_srq_in_bits {
6933 u8 reserved_at_20[0x10];
6936 u8 reserved_at_40[0x8];
6939 u8 reserved_at_60[0x20];
6942 struct mlx5_ifc_destroy_sq_out_bits {
6944 u8 reserved_at_8[0x18];
6948 u8 reserved_at_40[0x40];
6951 struct mlx5_ifc_destroy_sq_in_bits {
6955 u8 reserved_at_20[0x10];
6958 u8 reserved_at_40[0x8];
6961 u8 reserved_at_60[0x20];
6964 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6966 u8 reserved_at_8[0x18];
6970 u8 reserved_at_40[0x1c0];
6973 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6975 u8 reserved_at_10[0x10];
6977 u8 reserved_at_20[0x10];
6980 u8 scheduling_hierarchy[0x8];
6981 u8 reserved_at_48[0x18];
6983 u8 scheduling_element_id[0x20];
6985 u8 reserved_at_80[0x180];
6988 struct mlx5_ifc_destroy_rqt_out_bits {
6990 u8 reserved_at_8[0x18];
6994 u8 reserved_at_40[0x40];
6997 struct mlx5_ifc_destroy_rqt_in_bits {
7001 u8 reserved_at_20[0x10];
7004 u8 reserved_at_40[0x8];
7007 u8 reserved_at_60[0x20];
7010 struct mlx5_ifc_destroy_rq_out_bits {
7012 u8 reserved_at_8[0x18];
7016 u8 reserved_at_40[0x40];
7019 struct mlx5_ifc_destroy_rq_in_bits {
7023 u8 reserved_at_20[0x10];
7026 u8 reserved_at_40[0x8];
7029 u8 reserved_at_60[0x20];
7032 struct mlx5_ifc_set_delay_drop_params_in_bits {
7034 u8 reserved_at_10[0x10];
7036 u8 reserved_at_20[0x10];
7039 u8 reserved_at_40[0x20];
7041 u8 reserved_at_60[0x10];
7042 u8 delay_drop_timeout[0x10];
7045 struct mlx5_ifc_set_delay_drop_params_out_bits {
7047 u8 reserved_at_8[0x18];
7051 u8 reserved_at_40[0x40];
7054 struct mlx5_ifc_destroy_rmp_out_bits {
7056 u8 reserved_at_8[0x18];
7060 u8 reserved_at_40[0x40];
7063 struct mlx5_ifc_destroy_rmp_in_bits {
7067 u8 reserved_at_20[0x10];
7070 u8 reserved_at_40[0x8];
7073 u8 reserved_at_60[0x20];
7076 struct mlx5_ifc_destroy_qp_out_bits {
7078 u8 reserved_at_8[0x18];
7082 u8 reserved_at_40[0x40];
7085 struct mlx5_ifc_destroy_qp_in_bits {
7089 u8 reserved_at_20[0x10];
7092 u8 reserved_at_40[0x8];
7095 u8 reserved_at_60[0x20];
7098 struct mlx5_ifc_destroy_psv_out_bits {
7100 u8 reserved_at_8[0x18];
7104 u8 reserved_at_40[0x40];
7107 struct mlx5_ifc_destroy_psv_in_bits {
7109 u8 reserved_at_10[0x10];
7111 u8 reserved_at_20[0x10];
7114 u8 reserved_at_40[0x8];
7117 u8 reserved_at_60[0x20];
7120 struct mlx5_ifc_destroy_mkey_out_bits {
7122 u8 reserved_at_8[0x18];
7126 u8 reserved_at_40[0x40];
7129 struct mlx5_ifc_destroy_mkey_in_bits {
7133 u8 reserved_at_20[0x10];
7136 u8 reserved_at_40[0x8];
7137 u8 mkey_index[0x18];
7139 u8 reserved_at_60[0x20];
7142 struct mlx5_ifc_destroy_flow_table_out_bits {
7144 u8 reserved_at_8[0x18];
7148 u8 reserved_at_40[0x40];
7151 struct mlx5_ifc_destroy_flow_table_in_bits {
7153 u8 reserved_at_10[0x10];
7155 u8 reserved_at_20[0x10];
7158 u8 other_vport[0x1];
7159 u8 reserved_at_41[0xf];
7160 u8 vport_number[0x10];
7162 u8 reserved_at_60[0x20];
7165 u8 reserved_at_88[0x18];
7167 u8 reserved_at_a0[0x8];
7170 u8 reserved_at_c0[0x140];
7173 struct mlx5_ifc_destroy_flow_group_out_bits {
7175 u8 reserved_at_8[0x18];
7179 u8 reserved_at_40[0x40];
7182 struct mlx5_ifc_destroy_flow_group_in_bits {
7184 u8 reserved_at_10[0x10];
7186 u8 reserved_at_20[0x10];
7189 u8 other_vport[0x1];
7190 u8 reserved_at_41[0xf];
7191 u8 vport_number[0x10];
7193 u8 reserved_at_60[0x20];
7196 u8 reserved_at_88[0x18];
7198 u8 reserved_at_a0[0x8];
7203 u8 reserved_at_e0[0x120];
7206 struct mlx5_ifc_destroy_eq_out_bits {
7208 u8 reserved_at_8[0x18];
7212 u8 reserved_at_40[0x40];
7215 struct mlx5_ifc_destroy_eq_in_bits {
7217 u8 reserved_at_10[0x10];
7219 u8 reserved_at_20[0x10];
7222 u8 reserved_at_40[0x18];
7225 u8 reserved_at_60[0x20];
7228 struct mlx5_ifc_destroy_dct_out_bits {
7230 u8 reserved_at_8[0x18];
7234 u8 reserved_at_40[0x40];
7237 struct mlx5_ifc_destroy_dct_in_bits {
7241 u8 reserved_at_20[0x10];
7244 u8 reserved_at_40[0x8];
7247 u8 reserved_at_60[0x20];
7250 struct mlx5_ifc_destroy_cq_out_bits {
7252 u8 reserved_at_8[0x18];
7256 u8 reserved_at_40[0x40];
7259 struct mlx5_ifc_destroy_cq_in_bits {
7263 u8 reserved_at_20[0x10];
7266 u8 reserved_at_40[0x8];
7269 u8 reserved_at_60[0x20];
7272 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
7274 u8 reserved_at_8[0x18];
7278 u8 reserved_at_40[0x40];
7281 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7283 u8 reserved_at_10[0x10];
7285 u8 reserved_at_20[0x10];
7288 u8 reserved_at_40[0x20];
7290 u8 reserved_at_60[0x10];
7291 u8 vxlan_udp_port[0x10];
7294 struct mlx5_ifc_delete_l2_table_entry_out_bits {
7296 u8 reserved_at_8[0x18];
7300 u8 reserved_at_40[0x40];
7303 struct mlx5_ifc_delete_l2_table_entry_in_bits {
7305 u8 reserved_at_10[0x10];
7307 u8 reserved_at_20[0x10];
7310 u8 reserved_at_40[0x60];
7312 u8 reserved_at_a0[0x8];
7313 u8 table_index[0x18];
7315 u8 reserved_at_c0[0x140];
7318 struct mlx5_ifc_delete_fte_out_bits {
7320 u8 reserved_at_8[0x18];
7324 u8 reserved_at_40[0x40];
7327 struct mlx5_ifc_delete_fte_in_bits {
7329 u8 reserved_at_10[0x10];
7331 u8 reserved_at_20[0x10];
7334 u8 other_vport[0x1];
7335 u8 reserved_at_41[0xf];
7336 u8 vport_number[0x10];
7338 u8 reserved_at_60[0x20];
7341 u8 reserved_at_88[0x18];
7343 u8 reserved_at_a0[0x8];
7346 u8 reserved_at_c0[0x40];
7348 u8 flow_index[0x20];
7350 u8 reserved_at_120[0xe0];
7353 struct mlx5_ifc_dealloc_xrcd_out_bits {
7355 u8 reserved_at_8[0x18];
7359 u8 reserved_at_40[0x40];
7362 struct mlx5_ifc_dealloc_xrcd_in_bits {
7366 u8 reserved_at_20[0x10];
7369 u8 reserved_at_40[0x8];
7372 u8 reserved_at_60[0x20];
7375 struct mlx5_ifc_dealloc_uar_out_bits {
7377 u8 reserved_at_8[0x18];
7381 u8 reserved_at_40[0x40];
7384 struct mlx5_ifc_dealloc_uar_in_bits {
7386 u8 reserved_at_10[0x10];
7388 u8 reserved_at_20[0x10];
7391 u8 reserved_at_40[0x8];
7394 u8 reserved_at_60[0x20];
7397 struct mlx5_ifc_dealloc_transport_domain_out_bits {
7399 u8 reserved_at_8[0x18];
7403 u8 reserved_at_40[0x40];
7406 struct mlx5_ifc_dealloc_transport_domain_in_bits {
7410 u8 reserved_at_20[0x10];
7413 u8 reserved_at_40[0x8];
7414 u8 transport_domain[0x18];
7416 u8 reserved_at_60[0x20];
7419 struct mlx5_ifc_dealloc_q_counter_out_bits {
7421 u8 reserved_at_8[0x18];
7425 u8 reserved_at_40[0x40];
7428 struct mlx5_ifc_dealloc_q_counter_in_bits {
7430 u8 reserved_at_10[0x10];
7432 u8 reserved_at_20[0x10];
7435 u8 reserved_at_40[0x18];
7436 u8 counter_set_id[0x8];
7438 u8 reserved_at_60[0x20];
7441 struct mlx5_ifc_dealloc_pd_out_bits {
7443 u8 reserved_at_8[0x18];
7447 u8 reserved_at_40[0x40];
7450 struct mlx5_ifc_dealloc_pd_in_bits {
7454 u8 reserved_at_20[0x10];
7457 u8 reserved_at_40[0x8];
7460 u8 reserved_at_60[0x20];
7463 struct mlx5_ifc_dealloc_flow_counter_out_bits {
7465 u8 reserved_at_8[0x18];
7469 u8 reserved_at_40[0x40];
7472 struct mlx5_ifc_dealloc_flow_counter_in_bits {
7474 u8 reserved_at_10[0x10];
7476 u8 reserved_at_20[0x10];
7479 u8 flow_counter_id[0x20];
7481 u8 reserved_at_60[0x20];
7484 struct mlx5_ifc_create_xrq_out_bits {
7486 u8 reserved_at_8[0x18];
7490 u8 reserved_at_40[0x8];
7493 u8 reserved_at_60[0x20];
7496 struct mlx5_ifc_create_xrq_in_bits {
7500 u8 reserved_at_20[0x10];
7503 u8 reserved_at_40[0x40];
7505 struct mlx5_ifc_xrqc_bits xrq_context;
7508 struct mlx5_ifc_create_xrc_srq_out_bits {
7510 u8 reserved_at_8[0x18];
7514 u8 reserved_at_40[0x8];
7517 u8 reserved_at_60[0x20];
7520 struct mlx5_ifc_create_xrc_srq_in_bits {
7524 u8 reserved_at_20[0x10];
7527 u8 reserved_at_40[0x40];
7529 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7531 u8 reserved_at_280[0x60];
7533 u8 xrc_srq_umem_valid[0x1];
7534 u8 reserved_at_2e1[0x1f];
7536 u8 reserved_at_300[0x580];
7541 struct mlx5_ifc_create_tis_out_bits {
7543 u8 reserved_at_8[0x18];
7547 u8 reserved_at_40[0x8];
7550 u8 reserved_at_60[0x20];
7553 struct mlx5_ifc_create_tis_in_bits {
7557 u8 reserved_at_20[0x10];
7560 u8 reserved_at_40[0xc0];
7562 struct mlx5_ifc_tisc_bits ctx;
7565 struct mlx5_ifc_create_tir_out_bits {
7567 u8 icm_address_63_40[0x18];
7571 u8 icm_address_39_32[0x8];
7574 u8 icm_address_31_0[0x20];
7577 struct mlx5_ifc_create_tir_in_bits {
7581 u8 reserved_at_20[0x10];
7584 u8 reserved_at_40[0xc0];
7586 struct mlx5_ifc_tirc_bits ctx;
7589 struct mlx5_ifc_create_srq_out_bits {
7591 u8 reserved_at_8[0x18];
7595 u8 reserved_at_40[0x8];
7598 u8 reserved_at_60[0x20];
7601 struct mlx5_ifc_create_srq_in_bits {
7605 u8 reserved_at_20[0x10];
7608 u8 reserved_at_40[0x40];
7610 struct mlx5_ifc_srqc_bits srq_context_entry;
7612 u8 reserved_at_280[0x600];
7617 struct mlx5_ifc_create_sq_out_bits {
7619 u8 reserved_at_8[0x18];
7623 u8 reserved_at_40[0x8];
7626 u8 reserved_at_60[0x20];
7629 struct mlx5_ifc_create_sq_in_bits {
7633 u8 reserved_at_20[0x10];
7636 u8 reserved_at_40[0xc0];
7638 struct mlx5_ifc_sqc_bits ctx;
7641 struct mlx5_ifc_create_scheduling_element_out_bits {
7643 u8 reserved_at_8[0x18];
7647 u8 reserved_at_40[0x40];
7649 u8 scheduling_element_id[0x20];
7651 u8 reserved_at_a0[0x160];
7654 struct mlx5_ifc_create_scheduling_element_in_bits {
7656 u8 reserved_at_10[0x10];
7658 u8 reserved_at_20[0x10];
7661 u8 scheduling_hierarchy[0x8];
7662 u8 reserved_at_48[0x18];
7664 u8 reserved_at_60[0xa0];
7666 struct mlx5_ifc_scheduling_context_bits scheduling_context;
7668 u8 reserved_at_300[0x100];
7671 struct mlx5_ifc_create_rqt_out_bits {
7673 u8 reserved_at_8[0x18];
7677 u8 reserved_at_40[0x8];
7680 u8 reserved_at_60[0x20];
7683 struct mlx5_ifc_create_rqt_in_bits {
7687 u8 reserved_at_20[0x10];
7690 u8 reserved_at_40[0xc0];
7692 struct mlx5_ifc_rqtc_bits rqt_context;
7695 struct mlx5_ifc_create_rq_out_bits {
7697 u8 reserved_at_8[0x18];
7701 u8 reserved_at_40[0x8];
7704 u8 reserved_at_60[0x20];
7707 struct mlx5_ifc_create_rq_in_bits {
7711 u8 reserved_at_20[0x10];
7714 u8 reserved_at_40[0xc0];
7716 struct mlx5_ifc_rqc_bits ctx;
7719 struct mlx5_ifc_create_rmp_out_bits {
7721 u8 reserved_at_8[0x18];
7725 u8 reserved_at_40[0x8];
7728 u8 reserved_at_60[0x20];
7731 struct mlx5_ifc_create_rmp_in_bits {
7735 u8 reserved_at_20[0x10];
7738 u8 reserved_at_40[0xc0];
7740 struct mlx5_ifc_rmpc_bits ctx;
7743 struct mlx5_ifc_create_qp_out_bits {
7745 u8 reserved_at_8[0x18];
7749 u8 reserved_at_40[0x8];
7755 struct mlx5_ifc_create_qp_in_bits {
7759 u8 reserved_at_20[0x10];
7762 u8 reserved_at_40[0x8];
7765 u8 reserved_at_60[0x20];
7766 u8 opt_param_mask[0x20];
7770 struct mlx5_ifc_qpc_bits qpc;
7772 u8 reserved_at_800[0x60];
7774 u8 wq_umem_valid[0x1];
7775 u8 reserved_at_861[0x1f];
7780 struct mlx5_ifc_create_psv_out_bits {
7782 u8 reserved_at_8[0x18];
7786 u8 reserved_at_40[0x40];
7788 u8 reserved_at_80[0x8];
7789 u8 psv0_index[0x18];
7791 u8 reserved_at_a0[0x8];
7792 u8 psv1_index[0x18];
7794 u8 reserved_at_c0[0x8];
7795 u8 psv2_index[0x18];
7797 u8 reserved_at_e0[0x8];
7798 u8 psv3_index[0x18];
7801 struct mlx5_ifc_create_psv_in_bits {
7803 u8 reserved_at_10[0x10];
7805 u8 reserved_at_20[0x10];
7809 u8 reserved_at_44[0x4];
7812 u8 reserved_at_60[0x20];
7815 struct mlx5_ifc_create_mkey_out_bits {
7817 u8 reserved_at_8[0x18];
7821 u8 reserved_at_40[0x8];
7822 u8 mkey_index[0x18];
7824 u8 reserved_at_60[0x20];
7827 struct mlx5_ifc_create_mkey_in_bits {
7831 u8 reserved_at_20[0x10];
7834 u8 reserved_at_40[0x20];
7837 u8 mkey_umem_valid[0x1];
7838 u8 reserved_at_62[0x1e];
7840 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7842 u8 reserved_at_280[0x80];
7844 u8 translations_octword_actual_size[0x20];
7846 u8 reserved_at_320[0x560];
7848 u8 klm_pas_mtt[][0x20];
7852 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0,
7853 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1,
7854 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2,
7855 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3,
7856 MLX5_FLOW_TABLE_TYPE_FDB = 0X4,
7857 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5,
7858 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6,
7861 struct mlx5_ifc_create_flow_table_out_bits {
7863 u8 icm_address_63_40[0x18];
7867 u8 icm_address_39_32[0x8];
7870 u8 icm_address_31_0[0x20];
7873 struct mlx5_ifc_create_flow_table_in_bits {
7875 u8 reserved_at_10[0x10];
7877 u8 reserved_at_20[0x10];
7880 u8 other_vport[0x1];
7881 u8 reserved_at_41[0xf];
7882 u8 vport_number[0x10];
7884 u8 reserved_at_60[0x20];
7887 u8 reserved_at_88[0x18];
7889 u8 reserved_at_a0[0x20];
7891 struct mlx5_ifc_flow_table_context_bits flow_table_context;
7894 struct mlx5_ifc_create_flow_group_out_bits {
7896 u8 reserved_at_8[0x18];
7900 u8 reserved_at_40[0x8];
7903 u8 reserved_at_60[0x20];
7907 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
7908 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
7909 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
7910 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7913 struct mlx5_ifc_create_flow_group_in_bits {
7915 u8 reserved_at_10[0x10];
7917 u8 reserved_at_20[0x10];
7920 u8 other_vport[0x1];
7921 u8 reserved_at_41[0xf];
7922 u8 vport_number[0x10];
7924 u8 reserved_at_60[0x20];
7927 u8 reserved_at_88[0x18];
7929 u8 reserved_at_a0[0x8];
7932 u8 source_eswitch_owner_vhca_id_valid[0x1];
7934 u8 reserved_at_c1[0x1f];
7936 u8 start_flow_index[0x20];
7938 u8 reserved_at_100[0x20];
7940 u8 end_flow_index[0x20];
7942 u8 reserved_at_140[0xa0];
7944 u8 reserved_at_1e0[0x18];
7945 u8 match_criteria_enable[0x8];
7947 struct mlx5_ifc_fte_match_param_bits match_criteria;
7949 u8 reserved_at_1200[0xe00];
7952 struct mlx5_ifc_create_eq_out_bits {
7954 u8 reserved_at_8[0x18];
7958 u8 reserved_at_40[0x18];
7961 u8 reserved_at_60[0x20];
7964 struct mlx5_ifc_create_eq_in_bits {
7968 u8 reserved_at_20[0x10];
7971 u8 reserved_at_40[0x40];
7973 struct mlx5_ifc_eqc_bits eq_context_entry;
7975 u8 reserved_at_280[0x40];
7977 u8 event_bitmask[4][0x40];
7979 u8 reserved_at_3c0[0x4c0];
7984 struct mlx5_ifc_create_dct_out_bits {
7986 u8 reserved_at_8[0x18];
7990 u8 reserved_at_40[0x8];
7996 struct mlx5_ifc_create_dct_in_bits {
8000 u8 reserved_at_20[0x10];
8003 u8 reserved_at_40[0x40];
8005 struct mlx5_ifc_dctc_bits dct_context_entry;
8007 u8 reserved_at_280[0x180];
8010 struct mlx5_ifc_create_cq_out_bits {
8012 u8 reserved_at_8[0x18];
8016 u8 reserved_at_40[0x8];
8019 u8 reserved_at_60[0x20];
8022 struct mlx5_ifc_create_cq_in_bits {
8026 u8 reserved_at_20[0x10];
8029 u8 reserved_at_40[0x40];
8031 struct mlx5_ifc_cqc_bits cq_context;
8033 u8 reserved_at_280[0x60];
8035 u8 cq_umem_valid[0x1];
8036 u8 reserved_at_2e1[0x59f];
8041 struct mlx5_ifc_config_int_moderation_out_bits {
8043 u8 reserved_at_8[0x18];
8047 u8 reserved_at_40[0x4];
8049 u8 int_vector[0x10];
8051 u8 reserved_at_60[0x20];
8055 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
8056 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
8059 struct mlx5_ifc_config_int_moderation_in_bits {
8061 u8 reserved_at_10[0x10];
8063 u8 reserved_at_20[0x10];
8066 u8 reserved_at_40[0x4];
8068 u8 int_vector[0x10];
8070 u8 reserved_at_60[0x20];
8073 struct mlx5_ifc_attach_to_mcg_out_bits {
8075 u8 reserved_at_8[0x18];
8079 u8 reserved_at_40[0x40];
8082 struct mlx5_ifc_attach_to_mcg_in_bits {
8086 u8 reserved_at_20[0x10];
8089 u8 reserved_at_40[0x8];
8092 u8 reserved_at_60[0x20];
8094 u8 multicast_gid[16][0x8];
8097 struct mlx5_ifc_arm_xrq_out_bits {
8099 u8 reserved_at_8[0x18];
8103 u8 reserved_at_40[0x40];
8106 struct mlx5_ifc_arm_xrq_in_bits {
8108 u8 reserved_at_10[0x10];
8110 u8 reserved_at_20[0x10];
8113 u8 reserved_at_40[0x8];
8116 u8 reserved_at_60[0x10];
8120 struct mlx5_ifc_arm_xrc_srq_out_bits {
8122 u8 reserved_at_8[0x18];
8126 u8 reserved_at_40[0x40];
8130 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
8133 struct mlx5_ifc_arm_xrc_srq_in_bits {
8137 u8 reserved_at_20[0x10];
8140 u8 reserved_at_40[0x8];
8143 u8 reserved_at_60[0x10];
8147 struct mlx5_ifc_arm_rq_out_bits {
8149 u8 reserved_at_8[0x18];
8153 u8 reserved_at_40[0x40];
8157 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8158 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
8161 struct mlx5_ifc_arm_rq_in_bits {
8165 u8 reserved_at_20[0x10];
8168 u8 reserved_at_40[0x8];
8169 u8 srq_number[0x18];
8171 u8 reserved_at_60[0x10];
8175 struct mlx5_ifc_arm_dct_out_bits {
8177 u8 reserved_at_8[0x18];
8181 u8 reserved_at_40[0x40];
8184 struct mlx5_ifc_arm_dct_in_bits {
8186 u8 reserved_at_10[0x10];
8188 u8 reserved_at_20[0x10];
8191 u8 reserved_at_40[0x8];
8192 u8 dct_number[0x18];
8194 u8 reserved_at_60[0x20];
8197 struct mlx5_ifc_alloc_xrcd_out_bits {
8199 u8 reserved_at_8[0x18];
8203 u8 reserved_at_40[0x8];
8206 u8 reserved_at_60[0x20];
8209 struct mlx5_ifc_alloc_xrcd_in_bits {
8213 u8 reserved_at_20[0x10];
8216 u8 reserved_at_40[0x40];
8219 struct mlx5_ifc_alloc_uar_out_bits {
8221 u8 reserved_at_8[0x18];
8225 u8 reserved_at_40[0x8];
8228 u8 reserved_at_60[0x20];
8231 struct mlx5_ifc_alloc_uar_in_bits {
8233 u8 reserved_at_10[0x10];
8235 u8 reserved_at_20[0x10];
8238 u8 reserved_at_40[0x40];
8241 struct mlx5_ifc_alloc_transport_domain_out_bits {
8243 u8 reserved_at_8[0x18];
8247 u8 reserved_at_40[0x8];
8248 u8 transport_domain[0x18];
8250 u8 reserved_at_60[0x20];
8253 struct mlx5_ifc_alloc_transport_domain_in_bits {
8257 u8 reserved_at_20[0x10];
8260 u8 reserved_at_40[0x40];
8263 struct mlx5_ifc_alloc_q_counter_out_bits {
8265 u8 reserved_at_8[0x18];
8269 u8 reserved_at_40[0x18];
8270 u8 counter_set_id[0x8];
8272 u8 reserved_at_60[0x20];
8275 struct mlx5_ifc_alloc_q_counter_in_bits {
8279 u8 reserved_at_20[0x10];
8282 u8 reserved_at_40[0x40];
8285 struct mlx5_ifc_alloc_pd_out_bits {
8287 u8 reserved_at_8[0x18];
8291 u8 reserved_at_40[0x8];
8294 u8 reserved_at_60[0x20];
8297 struct mlx5_ifc_alloc_pd_in_bits {
8301 u8 reserved_at_20[0x10];
8304 u8 reserved_at_40[0x40];
8307 struct mlx5_ifc_alloc_flow_counter_out_bits {
8309 u8 reserved_at_8[0x18];
8313 u8 flow_counter_id[0x20];
8315 u8 reserved_at_60[0x20];
8318 struct mlx5_ifc_alloc_flow_counter_in_bits {
8320 u8 reserved_at_10[0x10];
8322 u8 reserved_at_20[0x10];
8325 u8 reserved_at_40[0x38];
8326 u8 flow_counter_bulk[0x8];
8329 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8331 u8 reserved_at_8[0x18];
8335 u8 reserved_at_40[0x40];
8338 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8340 u8 reserved_at_10[0x10];
8342 u8 reserved_at_20[0x10];
8345 u8 reserved_at_40[0x20];
8347 u8 reserved_at_60[0x10];
8348 u8 vxlan_udp_port[0x10];
8351 struct mlx5_ifc_set_pp_rate_limit_out_bits {
8353 u8 reserved_at_8[0x18];
8357 u8 reserved_at_40[0x40];
8360 struct mlx5_ifc_set_pp_rate_limit_context_bits {
8361 u8 rate_limit[0x20];
8363 u8 burst_upper_bound[0x20];
8365 u8 reserved_at_40[0x10];
8366 u8 typical_packet_size[0x10];
8368 u8 reserved_at_60[0x120];
8371 struct mlx5_ifc_set_pp_rate_limit_in_bits {
8375 u8 reserved_at_20[0x10];
8378 u8 reserved_at_40[0x10];
8379 u8 rate_limit_index[0x10];
8381 u8 reserved_at_60[0x20];
8383 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
8386 struct mlx5_ifc_access_register_out_bits {
8388 u8 reserved_at_8[0x18];
8392 u8 reserved_at_40[0x40];
8394 u8 register_data[][0x20];
8398 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
8399 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
8402 struct mlx5_ifc_access_register_in_bits {
8404 u8 reserved_at_10[0x10];
8406 u8 reserved_at_20[0x10];
8409 u8 reserved_at_40[0x10];
8410 u8 register_id[0x10];
8414 u8 register_data[][0x20];
8417 struct mlx5_ifc_sltp_reg_bits {
8422 u8 reserved_at_12[0x2];
8424 u8 reserved_at_18[0x8];
8426 u8 reserved_at_20[0x20];
8428 u8 reserved_at_40[0x7];
8434 u8 reserved_at_60[0xc];
8435 u8 ob_preemp_mode[0x4];
8439 u8 reserved_at_80[0x20];
8442 struct mlx5_ifc_slrg_reg_bits {
8447 u8 reserved_at_12[0x2];
8449 u8 reserved_at_18[0x8];
8451 u8 time_to_link_up[0x10];
8452 u8 reserved_at_30[0xc];
8453 u8 grade_lane_speed[0x4];
8455 u8 grade_version[0x8];
8458 u8 reserved_at_60[0x4];
8459 u8 height_grade_type[0x4];
8460 u8 height_grade[0x18];
8465 u8 reserved_at_a0[0x10];
8466 u8 height_sigma[0x10];
8468 u8 reserved_at_c0[0x20];
8470 u8 reserved_at_e0[0x4];
8471 u8 phase_grade_type[0x4];
8472 u8 phase_grade[0x18];
8474 u8 reserved_at_100[0x8];
8475 u8 phase_eo_pos[0x8];
8476 u8 reserved_at_110[0x8];
8477 u8 phase_eo_neg[0x8];
8479 u8 ffe_set_tested[0x10];
8480 u8 test_errors_per_lane[0x10];
8483 struct mlx5_ifc_pvlc_reg_bits {
8484 u8 reserved_at_0[0x8];
8486 u8 reserved_at_10[0x10];
8488 u8 reserved_at_20[0x1c];
8491 u8 reserved_at_40[0x1c];
8494 u8 reserved_at_60[0x1c];
8495 u8 vl_operational[0x4];
8498 struct mlx5_ifc_pude_reg_bits {
8501 u8 reserved_at_10[0x4];
8502 u8 admin_status[0x4];
8503 u8 reserved_at_18[0x4];
8504 u8 oper_status[0x4];
8506 u8 reserved_at_20[0x60];
8509 struct mlx5_ifc_ptys_reg_bits {
8510 u8 reserved_at_0[0x1];
8511 u8 an_disable_admin[0x1];
8512 u8 an_disable_cap[0x1];
8513 u8 reserved_at_3[0x5];
8515 u8 reserved_at_10[0xd];
8519 u8 reserved_at_24[0xc];
8520 u8 data_rate_oper[0x10];
8522 u8 ext_eth_proto_capability[0x20];
8524 u8 eth_proto_capability[0x20];
8526 u8 ib_link_width_capability[0x10];
8527 u8 ib_proto_capability[0x10];
8529 u8 ext_eth_proto_admin[0x20];
8531 u8 eth_proto_admin[0x20];
8533 u8 ib_link_width_admin[0x10];
8534 u8 ib_proto_admin[0x10];
8536 u8 ext_eth_proto_oper[0x20];
8538 u8 eth_proto_oper[0x20];
8540 u8 ib_link_width_oper[0x10];
8541 u8 ib_proto_oper[0x10];
8543 u8 reserved_at_160[0x1c];
8544 u8 connector_type[0x4];
8546 u8 eth_proto_lp_advertise[0x20];
8548 u8 reserved_at_1a0[0x60];
8551 struct mlx5_ifc_mlcr_reg_bits {
8552 u8 reserved_at_0[0x8];
8554 u8 reserved_at_10[0x20];
8556 u8 beacon_duration[0x10];
8557 u8 reserved_at_40[0x10];
8559 u8 beacon_remain[0x10];
8562 struct mlx5_ifc_ptas_reg_bits {
8563 u8 reserved_at_0[0x20];
8565 u8 algorithm_options[0x10];
8566 u8 reserved_at_30[0x4];
8567 u8 repetitions_mode[0x4];
8568 u8 num_of_repetitions[0x8];
8570 u8 grade_version[0x8];
8571 u8 height_grade_type[0x4];
8572 u8 phase_grade_type[0x4];
8573 u8 height_grade_weight[0x8];
8574 u8 phase_grade_weight[0x8];
8576 u8 gisim_measure_bits[0x10];
8577 u8 adaptive_tap_measure_bits[0x10];
8579 u8 ber_bath_high_error_threshold[0x10];
8580 u8 ber_bath_mid_error_threshold[0x10];
8582 u8 ber_bath_low_error_threshold[0x10];
8583 u8 one_ratio_high_threshold[0x10];
8585 u8 one_ratio_high_mid_threshold[0x10];
8586 u8 one_ratio_low_mid_threshold[0x10];
8588 u8 one_ratio_low_threshold[0x10];
8589 u8 ndeo_error_threshold[0x10];
8591 u8 mixer_offset_step_size[0x10];
8592 u8 reserved_at_110[0x8];
8593 u8 mix90_phase_for_voltage_bath[0x8];
8595 u8 mixer_offset_start[0x10];
8596 u8 mixer_offset_end[0x10];
8598 u8 reserved_at_140[0x15];
8599 u8 ber_test_time[0xb];
8602 struct mlx5_ifc_pspa_reg_bits {
8606 u8 reserved_at_18[0x8];
8608 u8 reserved_at_20[0x20];
8611 struct mlx5_ifc_pqdr_reg_bits {
8612 u8 reserved_at_0[0x8];
8614 u8 reserved_at_10[0x5];
8616 u8 reserved_at_18[0x6];
8619 u8 reserved_at_20[0x20];
8621 u8 reserved_at_40[0x10];
8622 u8 min_threshold[0x10];
8624 u8 reserved_at_60[0x10];
8625 u8 max_threshold[0x10];
8627 u8 reserved_at_80[0x10];
8628 u8 mark_probability_denominator[0x10];
8630 u8 reserved_at_a0[0x60];
8633 struct mlx5_ifc_ppsc_reg_bits {
8634 u8 reserved_at_0[0x8];
8636 u8 reserved_at_10[0x10];
8638 u8 reserved_at_20[0x60];
8640 u8 reserved_at_80[0x1c];
8643 u8 reserved_at_a0[0x1c];
8644 u8 wrps_status[0x4];
8646 u8 reserved_at_c0[0x8];
8647 u8 up_threshold[0x8];
8648 u8 reserved_at_d0[0x8];
8649 u8 down_threshold[0x8];
8651 u8 reserved_at_e0[0x20];
8653 u8 reserved_at_100[0x1c];
8656 u8 reserved_at_120[0x1c];
8657 u8 srps_status[0x4];
8659 u8 reserved_at_140[0x40];
8662 struct mlx5_ifc_pplr_reg_bits {
8663 u8 reserved_at_0[0x8];
8665 u8 reserved_at_10[0x10];
8667 u8 reserved_at_20[0x8];
8669 u8 reserved_at_30[0x8];
8673 struct mlx5_ifc_pplm_reg_bits {
8674 u8 reserved_at_0[0x8];
8676 u8 reserved_at_10[0x10];
8678 u8 reserved_at_20[0x20];
8680 u8 port_profile_mode[0x8];
8681 u8 static_port_profile[0x8];
8682 u8 active_port_profile[0x8];
8683 u8 reserved_at_58[0x8];
8685 u8 retransmission_active[0x8];
8686 u8 fec_mode_active[0x18];
8688 u8 rs_fec_correction_bypass_cap[0x4];
8689 u8 reserved_at_84[0x8];
8690 u8 fec_override_cap_56g[0x4];
8691 u8 fec_override_cap_100g[0x4];
8692 u8 fec_override_cap_50g[0x4];
8693 u8 fec_override_cap_25g[0x4];
8694 u8 fec_override_cap_10g_40g[0x4];
8696 u8 rs_fec_correction_bypass_admin[0x4];
8697 u8 reserved_at_a4[0x8];
8698 u8 fec_override_admin_56g[0x4];
8699 u8 fec_override_admin_100g[0x4];
8700 u8 fec_override_admin_50g[0x4];
8701 u8 fec_override_admin_25g[0x4];
8702 u8 fec_override_admin_10g_40g[0x4];
8704 u8 fec_override_cap_400g_8x[0x10];
8705 u8 fec_override_cap_200g_4x[0x10];
8707 u8 fec_override_cap_100g_2x[0x10];
8708 u8 fec_override_cap_50g_1x[0x10];
8710 u8 fec_override_admin_400g_8x[0x10];
8711 u8 fec_override_admin_200g_4x[0x10];
8713 u8 fec_override_admin_100g_2x[0x10];
8714 u8 fec_override_admin_50g_1x[0x10];
8717 struct mlx5_ifc_ppcnt_reg_bits {
8721 u8 reserved_at_12[0x8];
8725 u8 reserved_at_21[0x1c];
8728 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8731 struct mlx5_ifc_mpein_reg_bits {
8732 u8 reserved_at_0[0x2];
8736 u8 reserved_at_18[0x8];
8738 u8 capability_mask[0x20];
8740 u8 reserved_at_40[0x8];
8741 u8 link_width_enabled[0x8];
8742 u8 link_speed_enabled[0x10];
8744 u8 lane0_physical_position[0x8];
8745 u8 link_width_active[0x8];
8746 u8 link_speed_active[0x10];
8748 u8 num_of_pfs[0x10];
8749 u8 num_of_vfs[0x10];
8752 u8 reserved_at_b0[0x10];
8754 u8 max_read_request_size[0x4];
8755 u8 max_payload_size[0x4];
8756 u8 reserved_at_c8[0x5];
8759 u8 reserved_at_d4[0xb];
8760 u8 lane_reversal[0x1];
8762 u8 reserved_at_e0[0x14];
8765 u8 reserved_at_100[0x20];
8767 u8 device_status[0x10];
8769 u8 reserved_at_138[0x8];
8771 u8 reserved_at_140[0x10];
8772 u8 receiver_detect_result[0x10];
8774 u8 reserved_at_160[0x20];
8777 struct mlx5_ifc_mpcnt_reg_bits {
8778 u8 reserved_at_0[0x8];
8780 u8 reserved_at_10[0xa];
8784 u8 reserved_at_21[0x1f];
8786 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8789 struct mlx5_ifc_ppad_reg_bits {
8790 u8 reserved_at_0[0x3];
8792 u8 reserved_at_4[0x4];
8798 u8 reserved_at_40[0x40];
8801 struct mlx5_ifc_pmtu_reg_bits {
8802 u8 reserved_at_0[0x8];
8804 u8 reserved_at_10[0x10];
8807 u8 reserved_at_30[0x10];
8810 u8 reserved_at_50[0x10];
8813 u8 reserved_at_70[0x10];
8816 struct mlx5_ifc_pmpr_reg_bits {
8817 u8 reserved_at_0[0x8];
8819 u8 reserved_at_10[0x10];
8821 u8 reserved_at_20[0x18];
8822 u8 attenuation_5g[0x8];
8824 u8 reserved_at_40[0x18];
8825 u8 attenuation_7g[0x8];
8827 u8 reserved_at_60[0x18];
8828 u8 attenuation_12g[0x8];
8831 struct mlx5_ifc_pmpe_reg_bits {
8832 u8 reserved_at_0[0x8];
8834 u8 reserved_at_10[0xc];
8835 u8 module_status[0x4];
8837 u8 reserved_at_20[0x60];
8840 struct mlx5_ifc_pmpc_reg_bits {
8841 u8 module_state_updated[32][0x8];
8844 struct mlx5_ifc_pmlpn_reg_bits {
8845 u8 reserved_at_0[0x4];
8846 u8 mlpn_status[0x4];
8848 u8 reserved_at_10[0x10];
8851 u8 reserved_at_21[0x1f];
8854 struct mlx5_ifc_pmlp_reg_bits {
8856 u8 reserved_at_1[0x7];
8858 u8 reserved_at_10[0x8];
8861 u8 lane0_module_mapping[0x20];
8863 u8 lane1_module_mapping[0x20];
8865 u8 lane2_module_mapping[0x20];
8867 u8 lane3_module_mapping[0x20];
8869 u8 reserved_at_a0[0x160];
8872 struct mlx5_ifc_pmaos_reg_bits {
8873 u8 reserved_at_0[0x8];
8875 u8 reserved_at_10[0x4];
8876 u8 admin_status[0x4];
8877 u8 reserved_at_18[0x4];
8878 u8 oper_status[0x4];
8882 u8 reserved_at_22[0x1c];
8885 u8 reserved_at_40[0x40];
8888 struct mlx5_ifc_plpc_reg_bits {
8889 u8 reserved_at_0[0x4];
8891 u8 reserved_at_10[0x4];
8893 u8 reserved_at_18[0x8];
8895 u8 reserved_at_20[0x10];
8896 u8 lane_speed[0x10];
8898 u8 reserved_at_40[0x17];
8900 u8 fec_mode_policy[0x8];
8902 u8 retransmission_capability[0x8];
8903 u8 fec_mode_capability[0x18];
8905 u8 retransmission_support_admin[0x8];
8906 u8 fec_mode_support_admin[0x18];
8908 u8 retransmission_request_admin[0x8];
8909 u8 fec_mode_request_admin[0x18];
8911 u8 reserved_at_c0[0x80];
8914 struct mlx5_ifc_plib_reg_bits {
8915 u8 reserved_at_0[0x8];
8917 u8 reserved_at_10[0x8];
8920 u8 reserved_at_20[0x60];
8923 struct mlx5_ifc_plbf_reg_bits {
8924 u8 reserved_at_0[0x8];
8926 u8 reserved_at_10[0xd];
8929 u8 reserved_at_20[0x20];
8932 struct mlx5_ifc_pipg_reg_bits {
8933 u8 reserved_at_0[0x8];
8935 u8 reserved_at_10[0x10];
8938 u8 reserved_at_21[0x19];
8940 u8 reserved_at_3e[0x2];
8943 struct mlx5_ifc_pifr_reg_bits {
8944 u8 reserved_at_0[0x8];
8946 u8 reserved_at_10[0x10];
8948 u8 reserved_at_20[0xe0];
8950 u8 port_filter[8][0x20];
8952 u8 port_filter_update_en[8][0x20];
8955 struct mlx5_ifc_pfcc_reg_bits {
8956 u8 reserved_at_0[0x8];
8958 u8 reserved_at_10[0xb];
8959 u8 ppan_mask_n[0x1];
8960 u8 minor_stall_mask[0x1];
8961 u8 critical_stall_mask[0x1];
8962 u8 reserved_at_1e[0x2];
8965 u8 reserved_at_24[0x4];
8966 u8 prio_mask_tx[0x8];
8967 u8 reserved_at_30[0x8];
8968 u8 prio_mask_rx[0x8];
8972 u8 pptx_mask_n[0x1];
8973 u8 reserved_at_43[0x5];
8975 u8 reserved_at_50[0x10];
8979 u8 pprx_mask_n[0x1];
8980 u8 reserved_at_63[0x5];
8982 u8 reserved_at_70[0x10];
8984 u8 device_stall_minor_watermark[0x10];
8985 u8 device_stall_critical_watermark[0x10];
8987 u8 reserved_at_a0[0x60];
8990 struct mlx5_ifc_pelc_reg_bits {
8992 u8 reserved_at_4[0x4];
8994 u8 reserved_at_10[0x10];
8997 u8 op_capability[0x8];
9003 u8 capability[0x40];
9009 u8 reserved_at_140[0x80];
9012 struct mlx5_ifc_peir_reg_bits {
9013 u8 reserved_at_0[0x8];
9015 u8 reserved_at_10[0x10];
9017 u8 reserved_at_20[0xc];
9018 u8 error_count[0x4];
9019 u8 reserved_at_30[0x10];
9021 u8 reserved_at_40[0xc];
9023 u8 reserved_at_50[0x8];
9027 struct mlx5_ifc_mpegc_reg_bits {
9028 u8 reserved_at_0[0x30];
9029 u8 field_select[0x10];
9031 u8 tx_overflow_sense[0x1];
9034 u8 reserved_at_43[0x1b];
9035 u8 tx_lossy_overflow_oper[0x2];
9037 u8 reserved_at_60[0x100];
9040 struct mlx5_ifc_pcam_enhanced_features_bits {
9041 u8 reserved_at_0[0x68];
9042 u8 fec_50G_per_lane_in_pplm[0x1];
9043 u8 reserved_at_69[0x4];
9044 u8 rx_icrc_encapsulated_counter[0x1];
9045 u8 reserved_at_6e[0x4];
9046 u8 ptys_extended_ethernet[0x1];
9047 u8 reserved_at_73[0x3];
9049 u8 reserved_at_77[0x3];
9050 u8 per_lane_error_counters[0x1];
9051 u8 rx_buffer_fullness_counters[0x1];
9052 u8 ptys_connector_type[0x1];
9053 u8 reserved_at_7d[0x1];
9054 u8 ppcnt_discard_group[0x1];
9055 u8 ppcnt_statistical_group[0x1];
9058 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
9059 u8 port_access_reg_cap_mask_127_to_96[0x20];
9060 u8 port_access_reg_cap_mask_95_to_64[0x20];
9062 u8 port_access_reg_cap_mask_63_to_36[0x1c];
9064 u8 port_access_reg_cap_mask_34_to_32[0x3];
9066 u8 port_access_reg_cap_mask_31_to_13[0x13];
9069 u8 port_access_reg_cap_mask_10_to_09[0x2];
9071 u8 port_access_reg_cap_mask_07_to_00[0x8];
9074 struct mlx5_ifc_pcam_reg_bits {
9075 u8 reserved_at_0[0x8];
9076 u8 feature_group[0x8];
9077 u8 reserved_at_10[0x8];
9078 u8 access_reg_group[0x8];
9080 u8 reserved_at_20[0x20];
9083 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
9084 u8 reserved_at_0[0x80];
9085 } port_access_reg_cap_mask;
9087 u8 reserved_at_c0[0x80];
9090 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9091 u8 reserved_at_0[0x80];
9094 u8 reserved_at_1c0[0xc0];
9097 struct mlx5_ifc_mcam_enhanced_features_bits {
9098 u8 reserved_at_0[0x6e];
9099 u8 pci_status_and_power[0x1];
9100 u8 reserved_at_6f[0x5];
9101 u8 mark_tx_action_cnp[0x1];
9102 u8 mark_tx_action_cqe[0x1];
9103 u8 dynamic_tx_overflow[0x1];
9104 u8 reserved_at_77[0x4];
9105 u8 pcie_outbound_stalled[0x1];
9106 u8 tx_overflow_buffer_pkt[0x1];
9107 u8 mtpps_enh_out_per_adj[0x1];
9109 u8 pcie_performance_group[0x1];
9112 struct mlx5_ifc_mcam_access_reg_bits {
9113 u8 reserved_at_0[0x1c];
9119 u8 regs_95_to_87[0x9];
9121 u8 regs_85_to_68[0x12];
9122 u8 tracer_registers[0x4];
9124 u8 regs_63_to_32[0x20];
9125 u8 regs_31_to_0[0x20];
9128 struct mlx5_ifc_mcam_access_reg_bits1 {
9129 u8 regs_127_to_96[0x20];
9131 u8 regs_95_to_64[0x20];
9133 u8 regs_63_to_32[0x20];
9135 u8 regs_31_to_0[0x20];
9138 struct mlx5_ifc_mcam_access_reg_bits2 {
9139 u8 regs_127_to_99[0x1d];
9141 u8 regs_97_to_96[0x2];
9143 u8 regs_95_to_64[0x20];
9145 u8 regs_63_to_32[0x20];
9147 u8 regs_31_to_0[0x20];
9150 struct mlx5_ifc_mcam_reg_bits {
9151 u8 reserved_at_0[0x8];
9152 u8 feature_group[0x8];
9153 u8 reserved_at_10[0x8];
9154 u8 access_reg_group[0x8];
9156 u8 reserved_at_20[0x20];
9159 struct mlx5_ifc_mcam_access_reg_bits access_regs;
9160 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
9161 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
9162 u8 reserved_at_0[0x80];
9163 } mng_access_reg_cap_mask;
9165 u8 reserved_at_c0[0x80];
9168 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9169 u8 reserved_at_0[0x80];
9170 } mng_feature_cap_mask;
9172 u8 reserved_at_1c0[0x80];
9175 struct mlx5_ifc_qcam_access_reg_cap_mask {
9176 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
9178 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
9182 u8 qcam_access_reg_cap_mask_0[0x1];
9185 struct mlx5_ifc_qcam_qos_feature_cap_mask {
9186 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
9187 u8 qpts_trust_both[0x1];
9190 struct mlx5_ifc_qcam_reg_bits {
9191 u8 reserved_at_0[0x8];
9192 u8 feature_group[0x8];
9193 u8 reserved_at_10[0x8];
9194 u8 access_reg_group[0x8];
9195 u8 reserved_at_20[0x20];
9198 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9199 u8 reserved_at_0[0x80];
9200 } qos_access_reg_cap_mask;
9202 u8 reserved_at_c0[0x80];
9205 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9206 u8 reserved_at_0[0x80];
9207 } qos_feature_cap_mask;
9209 u8 reserved_at_1c0[0x80];
9212 struct mlx5_ifc_core_dump_reg_bits {
9213 u8 reserved_at_0[0x18];
9214 u8 core_dump_type[0x8];
9216 u8 reserved_at_20[0x30];
9219 u8 reserved_at_60[0x8];
9221 u8 reserved_at_80[0x180];
9224 struct mlx5_ifc_pcap_reg_bits {
9225 u8 reserved_at_0[0x8];
9227 u8 reserved_at_10[0x10];
9229 u8 port_capability_mask[4][0x20];
9232 struct mlx5_ifc_paos_reg_bits {
9235 u8 reserved_at_10[0x4];
9236 u8 admin_status[0x4];
9237 u8 reserved_at_18[0x4];
9238 u8 oper_status[0x4];
9242 u8 reserved_at_22[0x1c];
9245 u8 reserved_at_40[0x40];
9248 struct mlx5_ifc_pamp_reg_bits {
9249 u8 reserved_at_0[0x8];
9250 u8 opamp_group[0x8];
9251 u8 reserved_at_10[0xc];
9252 u8 opamp_group_type[0x4];
9254 u8 start_index[0x10];
9255 u8 reserved_at_30[0x4];
9256 u8 num_of_indices[0xc];
9258 u8 index_data[18][0x10];
9261 struct mlx5_ifc_pcmr_reg_bits {
9262 u8 reserved_at_0[0x8];
9264 u8 reserved_at_10[0x10];
9265 u8 entropy_force_cap[0x1];
9266 u8 entropy_calc_cap[0x1];
9267 u8 entropy_gre_calc_cap[0x1];
9268 u8 reserved_at_23[0x1b];
9270 u8 reserved_at_3f[0x1];
9271 u8 entropy_force[0x1];
9272 u8 entropy_calc[0x1];
9273 u8 entropy_gre_calc[0x1];
9274 u8 reserved_at_43[0x1b];
9276 u8 reserved_at_5f[0x1];
9279 struct mlx5_ifc_lane_2_module_mapping_bits {
9280 u8 reserved_at_0[0x6];
9282 u8 reserved_at_8[0x6];
9284 u8 reserved_at_10[0x8];
9288 struct mlx5_ifc_bufferx_reg_bits {
9289 u8 reserved_at_0[0x6];
9292 u8 reserved_at_8[0xc];
9295 u8 xoff_threshold[0x10];
9296 u8 xon_threshold[0x10];
9299 struct mlx5_ifc_set_node_in_bits {
9300 u8 node_description[64][0x8];
9303 struct mlx5_ifc_register_power_settings_bits {
9304 u8 reserved_at_0[0x18];
9305 u8 power_settings_level[0x8];
9307 u8 reserved_at_20[0x60];
9310 struct mlx5_ifc_register_host_endianness_bits {
9312 u8 reserved_at_1[0x1f];
9314 u8 reserved_at_20[0x60];
9317 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9318 u8 reserved_at_0[0x20];
9322 u8 addressh_63_32[0x20];
9324 u8 addressl_31_0[0x20];
9327 struct mlx5_ifc_ud_adrs_vector_bits {
9331 u8 reserved_at_41[0x7];
9332 u8 destination_qp_dct[0x18];
9334 u8 static_rate[0x4];
9335 u8 sl_eth_prio[0x4];
9338 u8 rlid_udp_sport[0x10];
9340 u8 reserved_at_80[0x20];
9342 u8 rmac_47_16[0x20];
9348 u8 reserved_at_e0[0x1];
9350 u8 reserved_at_e2[0x2];
9351 u8 src_addr_index[0x8];
9352 u8 flow_label[0x14];
9354 u8 rgid_rip[16][0x8];
9357 struct mlx5_ifc_pages_req_event_bits {
9358 u8 reserved_at_0[0x10];
9359 u8 function_id[0x10];
9363 u8 reserved_at_40[0xa0];
9366 struct mlx5_ifc_eqe_bits {
9367 u8 reserved_at_0[0x8];
9369 u8 reserved_at_10[0x8];
9370 u8 event_sub_type[0x8];
9372 u8 reserved_at_20[0xe0];
9374 union mlx5_ifc_event_auto_bits event_data;
9376 u8 reserved_at_1e0[0x10];
9378 u8 reserved_at_1f8[0x7];
9383 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
9386 struct mlx5_ifc_cmd_queue_entry_bits {
9388 u8 reserved_at_8[0x18];
9390 u8 input_length[0x20];
9392 u8 input_mailbox_pointer_63_32[0x20];
9394 u8 input_mailbox_pointer_31_9[0x17];
9395 u8 reserved_at_77[0x9];
9397 u8 command_input_inline_data[16][0x8];
9399 u8 command_output_inline_data[16][0x8];
9401 u8 output_mailbox_pointer_63_32[0x20];
9403 u8 output_mailbox_pointer_31_9[0x17];
9404 u8 reserved_at_1b7[0x9];
9406 u8 output_length[0x20];
9410 u8 reserved_at_1f0[0x8];
9415 struct mlx5_ifc_cmd_out_bits {
9417 u8 reserved_at_8[0x18];
9421 u8 command_output[0x20];
9424 struct mlx5_ifc_cmd_in_bits {
9426 u8 reserved_at_10[0x10];
9428 u8 reserved_at_20[0x10];
9434 struct mlx5_ifc_cmd_if_box_bits {
9435 u8 mailbox_data[512][0x8];
9437 u8 reserved_at_1000[0x180];
9439 u8 next_pointer_63_32[0x20];
9441 u8 next_pointer_31_10[0x16];
9442 u8 reserved_at_11b6[0xa];
9444 u8 block_number[0x20];
9446 u8 reserved_at_11e0[0x8];
9448 u8 ctrl_signature[0x8];
9452 struct mlx5_ifc_mtt_bits {
9453 u8 ptag_63_32[0x20];
9456 u8 reserved_at_38[0x6];
9461 struct mlx5_ifc_query_wol_rol_out_bits {
9463 u8 reserved_at_8[0x18];
9467 u8 reserved_at_40[0x10];
9471 u8 reserved_at_60[0x20];
9474 struct mlx5_ifc_query_wol_rol_in_bits {
9476 u8 reserved_at_10[0x10];
9478 u8 reserved_at_20[0x10];
9481 u8 reserved_at_40[0x40];
9484 struct mlx5_ifc_set_wol_rol_out_bits {
9486 u8 reserved_at_8[0x18];
9490 u8 reserved_at_40[0x40];
9493 struct mlx5_ifc_set_wol_rol_in_bits {
9495 u8 reserved_at_10[0x10];
9497 u8 reserved_at_20[0x10];
9500 u8 rol_mode_valid[0x1];
9501 u8 wol_mode_valid[0x1];
9502 u8 reserved_at_42[0xe];
9506 u8 reserved_at_60[0x20];
9510 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
9511 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
9512 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
9516 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
9517 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
9518 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
9522 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
9523 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
9524 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
9525 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
9526 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
9527 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
9528 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
9529 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
9530 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
9531 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
9532 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
9535 struct mlx5_ifc_initial_seg_bits {
9536 u8 fw_rev_minor[0x10];
9537 u8 fw_rev_major[0x10];
9539 u8 cmd_interface_rev[0x10];
9540 u8 fw_rev_subminor[0x10];
9542 u8 reserved_at_40[0x40];
9544 u8 cmdq_phy_addr_63_32[0x20];
9546 u8 cmdq_phy_addr_31_12[0x14];
9547 u8 reserved_at_b4[0x2];
9548 u8 nic_interface[0x2];
9549 u8 log_cmdq_size[0x4];
9550 u8 log_cmdq_stride[0x4];
9552 u8 command_doorbell_vector[0x20];
9554 u8 reserved_at_e0[0xf00];
9556 u8 initializing[0x1];
9557 u8 reserved_at_fe1[0x4];
9558 u8 nic_interface_supported[0x3];
9559 u8 embedded_cpu[0x1];
9560 u8 reserved_at_fe9[0x17];
9562 struct mlx5_ifc_health_buffer_bits health_buffer;
9564 u8 no_dram_nic_offset[0x20];
9566 u8 reserved_at_1220[0x6e40];
9568 u8 reserved_at_8060[0x1f];
9571 u8 health_syndrome[0x8];
9572 u8 health_counter[0x18];
9574 u8 reserved_at_80a0[0x17fc0];
9577 struct mlx5_ifc_mtpps_reg_bits {
9578 u8 reserved_at_0[0xc];
9579 u8 cap_number_of_pps_pins[0x4];
9580 u8 reserved_at_10[0x4];
9581 u8 cap_max_num_of_pps_in_pins[0x4];
9582 u8 reserved_at_18[0x4];
9583 u8 cap_max_num_of_pps_out_pins[0x4];
9585 u8 reserved_at_20[0x24];
9586 u8 cap_pin_3_mode[0x4];
9587 u8 reserved_at_48[0x4];
9588 u8 cap_pin_2_mode[0x4];
9589 u8 reserved_at_50[0x4];
9590 u8 cap_pin_1_mode[0x4];
9591 u8 reserved_at_58[0x4];
9592 u8 cap_pin_0_mode[0x4];
9594 u8 reserved_at_60[0x4];
9595 u8 cap_pin_7_mode[0x4];
9596 u8 reserved_at_68[0x4];
9597 u8 cap_pin_6_mode[0x4];
9598 u8 reserved_at_70[0x4];
9599 u8 cap_pin_5_mode[0x4];
9600 u8 reserved_at_78[0x4];
9601 u8 cap_pin_4_mode[0x4];
9603 u8 field_select[0x20];
9604 u8 reserved_at_a0[0x60];
9607 u8 reserved_at_101[0xb];
9609 u8 reserved_at_110[0x4];
9613 u8 reserved_at_120[0x20];
9615 u8 time_stamp[0x40];
9617 u8 out_pulse_duration[0x10];
9618 u8 out_periodic_adjustment[0x10];
9619 u8 enhanced_out_periodic_adjustment[0x20];
9621 u8 reserved_at_1c0[0x20];
9624 struct mlx5_ifc_mtppse_reg_bits {
9625 u8 reserved_at_0[0x18];
9628 u8 reserved_at_21[0x1b];
9629 u8 event_generation_mode[0x4];
9630 u8 reserved_at_40[0x40];
9633 struct mlx5_ifc_mcqs_reg_bits {
9634 u8 last_index_flag[0x1];
9635 u8 reserved_at_1[0x7];
9637 u8 component_index[0x10];
9639 u8 reserved_at_20[0x10];
9640 u8 identifier[0x10];
9642 u8 reserved_at_40[0x17];
9643 u8 component_status[0x5];
9644 u8 component_update_state[0x4];
9646 u8 last_update_state_changer_type[0x4];
9647 u8 last_update_state_changer_host_id[0x4];
9648 u8 reserved_at_68[0x18];
9651 struct mlx5_ifc_mcqi_cap_bits {
9652 u8 supported_info_bitmask[0x20];
9654 u8 component_size[0x20];
9656 u8 max_component_size[0x20];
9658 u8 log_mcda_word_size[0x4];
9659 u8 reserved_at_64[0xc];
9660 u8 mcda_max_write_size[0x10];
9663 u8 reserved_at_81[0x1];
9664 u8 match_chip_id[0x1];
9666 u8 check_user_timestamp[0x1];
9667 u8 match_base_guid_mac[0x1];
9668 u8 reserved_at_86[0x1a];
9671 struct mlx5_ifc_mcqi_version_bits {
9672 u8 reserved_at_0[0x2];
9673 u8 build_time_valid[0x1];
9674 u8 user_defined_time_valid[0x1];
9675 u8 reserved_at_4[0x14];
9676 u8 version_string_length[0x8];
9680 u8 build_time[0x40];
9682 u8 user_defined_time[0x40];
9684 u8 build_tool_version[0x20];
9686 u8 reserved_at_e0[0x20];
9688 u8 version_string[92][0x8];
9691 struct mlx5_ifc_mcqi_activation_method_bits {
9692 u8 pending_server_ac_power_cycle[0x1];
9693 u8 pending_server_dc_power_cycle[0x1];
9694 u8 pending_server_reboot[0x1];
9695 u8 pending_fw_reset[0x1];
9696 u8 auto_activate[0x1];
9697 u8 all_hosts_sync[0x1];
9698 u8 device_hw_reset[0x1];
9699 u8 reserved_at_7[0x19];
9702 union mlx5_ifc_mcqi_reg_data_bits {
9703 struct mlx5_ifc_mcqi_cap_bits mcqi_caps;
9704 struct mlx5_ifc_mcqi_version_bits mcqi_version;
9705 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9708 struct mlx5_ifc_mcqi_reg_bits {
9709 u8 read_pending_component[0x1];
9710 u8 reserved_at_1[0xf];
9711 u8 component_index[0x10];
9713 u8 reserved_at_20[0x20];
9715 u8 reserved_at_40[0x1b];
9722 u8 reserved_at_a0[0x10];
9725 union mlx5_ifc_mcqi_reg_data_bits data[];
9728 struct mlx5_ifc_mcc_reg_bits {
9729 u8 reserved_at_0[0x4];
9730 u8 time_elapsed_since_last_cmd[0xc];
9731 u8 reserved_at_10[0x8];
9732 u8 instruction[0x8];
9734 u8 reserved_at_20[0x10];
9735 u8 component_index[0x10];
9737 u8 reserved_at_40[0x8];
9738 u8 update_handle[0x18];
9740 u8 handle_owner_type[0x4];
9741 u8 handle_owner_host_id[0x4];
9742 u8 reserved_at_68[0x1];
9743 u8 control_progress[0x7];
9745 u8 reserved_at_78[0x4];
9746 u8 control_state[0x4];
9748 u8 component_size[0x20];
9750 u8 reserved_at_a0[0x60];
9753 struct mlx5_ifc_mcda_reg_bits {
9754 u8 reserved_at_0[0x8];
9755 u8 update_handle[0x18];
9759 u8 reserved_at_40[0x10];
9762 u8 reserved_at_60[0x20];
9768 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
9769 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
9773 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
9774 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
9775 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
9778 struct mlx5_ifc_mfrl_reg_bits {
9779 u8 reserved_at_0[0x20];
9781 u8 reserved_at_20[0x2];
9782 u8 pci_sync_for_fw_update_start[0x1];
9783 u8 pci_sync_for_fw_update_resp[0x2];
9784 u8 rst_type_sel[0x3];
9785 u8 reserved_at_28[0x8];
9787 u8 reset_level[0x8];
9790 struct mlx5_ifc_mirc_reg_bits {
9791 u8 reserved_at_0[0x18];
9792 u8 status_code[0x8];
9794 u8 reserved_at_20[0x20];
9797 union mlx5_ifc_ports_control_registers_document_bits {
9798 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9799 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9800 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9801 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9802 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9803 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9804 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9805 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
9806 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
9807 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9808 struct mlx5_ifc_pamp_reg_bits pamp_reg;
9809 struct mlx5_ifc_paos_reg_bits paos_reg;
9810 struct mlx5_ifc_pcap_reg_bits pcap_reg;
9811 struct mlx5_ifc_peir_reg_bits peir_reg;
9812 struct mlx5_ifc_pelc_reg_bits pelc_reg;
9813 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9814 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
9815 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9816 struct mlx5_ifc_pifr_reg_bits pifr_reg;
9817 struct mlx5_ifc_pipg_reg_bits pipg_reg;
9818 struct mlx5_ifc_plbf_reg_bits plbf_reg;
9819 struct mlx5_ifc_plib_reg_bits plib_reg;
9820 struct mlx5_ifc_plpc_reg_bits plpc_reg;
9821 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9822 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9823 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9824 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9825 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9826 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9827 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9828 struct mlx5_ifc_ppad_reg_bits ppad_reg;
9829 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9830 struct mlx5_ifc_mpein_reg_bits mpein_reg;
9831 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
9832 struct mlx5_ifc_pplm_reg_bits pplm_reg;
9833 struct mlx5_ifc_pplr_reg_bits pplr_reg;
9834 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9835 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
9836 struct mlx5_ifc_pspa_reg_bits pspa_reg;
9837 struct mlx5_ifc_ptas_reg_bits ptas_reg;
9838 struct mlx5_ifc_ptys_reg_bits ptys_reg;
9839 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
9840 struct mlx5_ifc_pude_reg_bits pude_reg;
9841 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9842 struct mlx5_ifc_slrg_reg_bits slrg_reg;
9843 struct mlx5_ifc_sltp_reg_bits sltp_reg;
9844 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
9845 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
9846 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
9847 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
9848 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
9849 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
9850 struct mlx5_ifc_mcc_reg_bits mcc_reg;
9851 struct mlx5_ifc_mcda_reg_bits mcda_reg;
9852 struct mlx5_ifc_mirc_reg_bits mirc_reg;
9853 struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
9854 u8 reserved_at_0[0x60e0];
9857 union mlx5_ifc_debug_enhancements_document_bits {
9858 struct mlx5_ifc_health_buffer_bits health_buffer;
9859 u8 reserved_at_0[0x200];
9862 union mlx5_ifc_uplink_pci_interface_document_bits {
9863 struct mlx5_ifc_initial_seg_bits initial_seg;
9864 u8 reserved_at_0[0x20060];
9867 struct mlx5_ifc_set_flow_table_root_out_bits {
9869 u8 reserved_at_8[0x18];
9873 u8 reserved_at_40[0x40];
9876 struct mlx5_ifc_set_flow_table_root_in_bits {
9878 u8 reserved_at_10[0x10];
9880 u8 reserved_at_20[0x10];
9883 u8 other_vport[0x1];
9884 u8 reserved_at_41[0xf];
9885 u8 vport_number[0x10];
9887 u8 reserved_at_60[0x20];
9890 u8 reserved_at_88[0x18];
9892 u8 reserved_at_a0[0x8];
9895 u8 reserved_at_c0[0x8];
9896 u8 underlay_qpn[0x18];
9897 u8 reserved_at_e0[0x120];
9901 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
9902 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
9905 struct mlx5_ifc_modify_flow_table_out_bits {
9907 u8 reserved_at_8[0x18];
9911 u8 reserved_at_40[0x40];
9914 struct mlx5_ifc_modify_flow_table_in_bits {
9916 u8 reserved_at_10[0x10];
9918 u8 reserved_at_20[0x10];
9921 u8 other_vport[0x1];
9922 u8 reserved_at_41[0xf];
9923 u8 vport_number[0x10];
9925 u8 reserved_at_60[0x10];
9926 u8 modify_field_select[0x10];
9929 u8 reserved_at_88[0x18];
9931 u8 reserved_at_a0[0x8];
9934 struct mlx5_ifc_flow_table_context_bits flow_table_context;
9937 struct mlx5_ifc_ets_tcn_config_reg_bits {
9941 u8 reserved_at_3[0x9];
9943 u8 reserved_at_10[0x9];
9944 u8 bw_allocation[0x7];
9946 u8 reserved_at_20[0xc];
9947 u8 max_bw_units[0x4];
9948 u8 reserved_at_30[0x8];
9949 u8 max_bw_value[0x8];
9952 struct mlx5_ifc_ets_global_config_reg_bits {
9953 u8 reserved_at_0[0x2];
9955 u8 reserved_at_3[0x1d];
9957 u8 reserved_at_20[0xc];
9958 u8 max_bw_units[0x4];
9959 u8 reserved_at_30[0x8];
9960 u8 max_bw_value[0x8];
9963 struct mlx5_ifc_qetc_reg_bits {
9964 u8 reserved_at_0[0x8];
9965 u8 port_number[0x8];
9966 u8 reserved_at_10[0x30];
9968 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
9969 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9972 struct mlx5_ifc_qpdpm_dscp_reg_bits {
9974 u8 reserved_at_01[0x0b];
9978 struct mlx5_ifc_qpdpm_reg_bits {
9979 u8 reserved_at_0[0x8];
9981 u8 reserved_at_10[0x10];
9982 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
9985 struct mlx5_ifc_qpts_reg_bits {
9986 u8 reserved_at_0[0x8];
9988 u8 reserved_at_10[0x2d];
9989 u8 trust_state[0x3];
9992 struct mlx5_ifc_pptb_reg_bits {
9993 u8 reserved_at_0[0x2];
9995 u8 reserved_at_4[0x4];
9997 u8 reserved_at_10[0x6];
10002 u8 prio_x_buff[0x20];
10005 u8 reserved_at_48[0x10];
10007 u8 untagged_buff[0x4];
10010 struct mlx5_ifc_sbcam_reg_bits {
10011 u8 reserved_at_0[0x8];
10012 u8 feature_group[0x8];
10013 u8 reserved_at_10[0x8];
10014 u8 access_reg_group[0x8];
10016 u8 reserved_at_20[0x20];
10018 u8 sb_access_reg_cap_mask[4][0x20];
10020 u8 reserved_at_c0[0x80];
10022 u8 sb_feature_cap_mask[4][0x20];
10024 u8 reserved_at_1c0[0x40];
10026 u8 cap_total_buffer_size[0x20];
10028 u8 cap_cell_size[0x10];
10029 u8 cap_max_pg_buffers[0x8];
10030 u8 cap_num_pool_supported[0x8];
10032 u8 reserved_at_240[0x8];
10033 u8 cap_sbsr_stat_size[0x8];
10034 u8 cap_max_tclass_data[0x8];
10035 u8 cap_max_cpu_ingress_tclass_sb[0x8];
10038 struct mlx5_ifc_pbmc_reg_bits {
10039 u8 reserved_at_0[0x8];
10040 u8 local_port[0x8];
10041 u8 reserved_at_10[0x10];
10043 u8 xoff_timer_value[0x10];
10044 u8 xoff_refresh[0x10];
10046 u8 reserved_at_40[0x9];
10047 u8 fullness_threshold[0x7];
10048 u8 port_buffer_size[0x10];
10050 struct mlx5_ifc_bufferx_reg_bits buffer[10];
10052 u8 reserved_at_2e0[0x40];
10055 struct mlx5_ifc_qtct_reg_bits {
10056 u8 reserved_at_0[0x8];
10057 u8 port_number[0x8];
10058 u8 reserved_at_10[0xd];
10061 u8 reserved_at_20[0x1d];
10065 struct mlx5_ifc_mcia_reg_bits {
10067 u8 reserved_at_1[0x7];
10069 u8 reserved_at_10[0x8];
10072 u8 i2c_device_address[0x8];
10073 u8 page_number[0x8];
10074 u8 device_address[0x10];
10076 u8 reserved_at_40[0x10];
10079 u8 reserved_at_60[0x20];
10095 struct mlx5_ifc_dcbx_param_bits {
10096 u8 dcbx_cee_cap[0x1];
10097 u8 dcbx_ieee_cap[0x1];
10098 u8 dcbx_standby_cap[0x1];
10099 u8 reserved_at_3[0x5];
10100 u8 port_number[0x8];
10101 u8 reserved_at_10[0xa];
10102 u8 max_application_table_size[6];
10103 u8 reserved_at_20[0x15];
10104 u8 version_oper[0x3];
10105 u8 reserved_at_38[5];
10106 u8 version_admin[0x3];
10107 u8 willing_admin[0x1];
10108 u8 reserved_at_41[0x3];
10109 u8 pfc_cap_oper[0x4];
10110 u8 reserved_at_48[0x4];
10111 u8 pfc_cap_admin[0x4];
10112 u8 reserved_at_50[0x4];
10113 u8 num_of_tc_oper[0x4];
10114 u8 reserved_at_58[0x4];
10115 u8 num_of_tc_admin[0x4];
10116 u8 remote_willing[0x1];
10117 u8 reserved_at_61[3];
10118 u8 remote_pfc_cap[4];
10119 u8 reserved_at_68[0x14];
10120 u8 remote_num_of_tc[0x4];
10121 u8 reserved_at_80[0x18];
10123 u8 reserved_at_a0[0x160];
10126 struct mlx5_ifc_lagc_bits {
10127 u8 reserved_at_0[0x1d];
10130 u8 reserved_at_20[0x14];
10131 u8 tx_remap_affinity_2[0x4];
10132 u8 reserved_at_38[0x4];
10133 u8 tx_remap_affinity_1[0x4];
10136 struct mlx5_ifc_create_lag_out_bits {
10138 u8 reserved_at_8[0x18];
10142 u8 reserved_at_40[0x40];
10145 struct mlx5_ifc_create_lag_in_bits {
10147 u8 reserved_at_10[0x10];
10149 u8 reserved_at_20[0x10];
10152 struct mlx5_ifc_lagc_bits ctx;
10155 struct mlx5_ifc_modify_lag_out_bits {
10157 u8 reserved_at_8[0x18];
10161 u8 reserved_at_40[0x40];
10164 struct mlx5_ifc_modify_lag_in_bits {
10166 u8 reserved_at_10[0x10];
10168 u8 reserved_at_20[0x10];
10171 u8 reserved_at_40[0x20];
10172 u8 field_select[0x20];
10174 struct mlx5_ifc_lagc_bits ctx;
10177 struct mlx5_ifc_query_lag_out_bits {
10179 u8 reserved_at_8[0x18];
10183 struct mlx5_ifc_lagc_bits ctx;
10186 struct mlx5_ifc_query_lag_in_bits {
10188 u8 reserved_at_10[0x10];
10190 u8 reserved_at_20[0x10];
10193 u8 reserved_at_40[0x40];
10196 struct mlx5_ifc_destroy_lag_out_bits {
10198 u8 reserved_at_8[0x18];
10202 u8 reserved_at_40[0x40];
10205 struct mlx5_ifc_destroy_lag_in_bits {
10207 u8 reserved_at_10[0x10];
10209 u8 reserved_at_20[0x10];
10212 u8 reserved_at_40[0x40];
10215 struct mlx5_ifc_create_vport_lag_out_bits {
10217 u8 reserved_at_8[0x18];
10221 u8 reserved_at_40[0x40];
10224 struct mlx5_ifc_create_vport_lag_in_bits {
10226 u8 reserved_at_10[0x10];
10228 u8 reserved_at_20[0x10];
10231 u8 reserved_at_40[0x40];
10234 struct mlx5_ifc_destroy_vport_lag_out_bits {
10236 u8 reserved_at_8[0x18];
10240 u8 reserved_at_40[0x40];
10243 struct mlx5_ifc_destroy_vport_lag_in_bits {
10245 u8 reserved_at_10[0x10];
10247 u8 reserved_at_20[0x10];
10250 u8 reserved_at_40[0x40];
10253 struct mlx5_ifc_alloc_memic_in_bits {
10255 u8 reserved_at_10[0x10];
10257 u8 reserved_at_20[0x10];
10260 u8 reserved_at_30[0x20];
10262 u8 reserved_at_40[0x18];
10263 u8 log_memic_addr_alignment[0x8];
10265 u8 range_start_addr[0x40];
10267 u8 range_size[0x20];
10269 u8 memic_size[0x20];
10272 struct mlx5_ifc_alloc_memic_out_bits {
10274 u8 reserved_at_8[0x18];
10278 u8 memic_start_addr[0x40];
10281 struct mlx5_ifc_dealloc_memic_in_bits {
10283 u8 reserved_at_10[0x10];
10285 u8 reserved_at_20[0x10];
10288 u8 reserved_at_40[0x40];
10290 u8 memic_start_addr[0x40];
10292 u8 memic_size[0x20];
10294 u8 reserved_at_e0[0x20];
10297 struct mlx5_ifc_dealloc_memic_out_bits {
10299 u8 reserved_at_8[0x18];
10303 u8 reserved_at_40[0x40];
10306 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
10310 u8 vhca_tunnel_id[0x10];
10315 u8 reserved_at_60[0x20];
10318 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
10320 u8 reserved_at_8[0x18];
10326 u8 reserved_at_60[0x20];
10329 struct mlx5_ifc_umem_bits {
10330 u8 reserved_at_0[0x80];
10332 u8 reserved_at_80[0x1b];
10333 u8 log_page_size[0x5];
10335 u8 page_offset[0x20];
10337 u8 num_of_mtt[0x40];
10339 struct mlx5_ifc_mtt_bits mtt[];
10342 struct mlx5_ifc_uctx_bits {
10345 u8 reserved_at_20[0x160];
10348 struct mlx5_ifc_sw_icm_bits {
10349 u8 modify_field_select[0x40];
10351 u8 reserved_at_40[0x18];
10352 u8 log_sw_icm_size[0x8];
10354 u8 reserved_at_60[0x20];
10356 u8 sw_icm_start_addr[0x40];
10358 u8 reserved_at_c0[0x140];
10361 struct mlx5_ifc_geneve_tlv_option_bits {
10362 u8 modify_field_select[0x40];
10364 u8 reserved_at_40[0x18];
10365 u8 geneve_option_fte_index[0x8];
10367 u8 option_class[0x10];
10368 u8 option_type[0x8];
10369 u8 reserved_at_78[0x3];
10370 u8 option_data_length[0x5];
10372 u8 reserved_at_80[0x180];
10375 struct mlx5_ifc_create_umem_in_bits {
10379 u8 reserved_at_20[0x10];
10382 u8 reserved_at_40[0x40];
10384 struct mlx5_ifc_umem_bits umem;
10387 struct mlx5_ifc_create_umem_out_bits {
10389 u8 reserved_at_8[0x18];
10393 u8 reserved_at_40[0x8];
10396 u8 reserved_at_60[0x20];
10399 struct mlx5_ifc_destroy_umem_in_bits {
10403 u8 reserved_at_20[0x10];
10406 u8 reserved_at_40[0x8];
10409 u8 reserved_at_60[0x20];
10412 struct mlx5_ifc_destroy_umem_out_bits {
10414 u8 reserved_at_8[0x18];
10418 u8 reserved_at_40[0x40];
10421 struct mlx5_ifc_create_uctx_in_bits {
10423 u8 reserved_at_10[0x10];
10425 u8 reserved_at_20[0x10];
10428 u8 reserved_at_40[0x40];
10430 struct mlx5_ifc_uctx_bits uctx;
10433 struct mlx5_ifc_create_uctx_out_bits {
10435 u8 reserved_at_8[0x18];
10439 u8 reserved_at_40[0x10];
10442 u8 reserved_at_60[0x20];
10445 struct mlx5_ifc_destroy_uctx_in_bits {
10447 u8 reserved_at_10[0x10];
10449 u8 reserved_at_20[0x10];
10452 u8 reserved_at_40[0x10];
10455 u8 reserved_at_60[0x20];
10458 struct mlx5_ifc_destroy_uctx_out_bits {
10460 u8 reserved_at_8[0x18];
10464 u8 reserved_at_40[0x40];
10467 struct mlx5_ifc_create_sw_icm_in_bits {
10468 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
10469 struct mlx5_ifc_sw_icm_bits sw_icm;
10472 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
10473 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
10474 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
10477 struct mlx5_ifc_mtrc_string_db_param_bits {
10478 u8 string_db_base_address[0x20];
10480 u8 reserved_at_20[0x8];
10481 u8 string_db_size[0x18];
10484 struct mlx5_ifc_mtrc_cap_bits {
10485 u8 trace_owner[0x1];
10486 u8 trace_to_memory[0x1];
10487 u8 reserved_at_2[0x4];
10489 u8 reserved_at_8[0x14];
10490 u8 num_string_db[0x4];
10492 u8 first_string_trace[0x8];
10493 u8 num_string_trace[0x8];
10494 u8 reserved_at_30[0x28];
10496 u8 log_max_trace_buffer_size[0x8];
10498 u8 reserved_at_60[0x20];
10500 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
10502 u8 reserved_at_280[0x180];
10505 struct mlx5_ifc_mtrc_conf_bits {
10506 u8 reserved_at_0[0x1c];
10507 u8 trace_mode[0x4];
10508 u8 reserved_at_20[0x18];
10509 u8 log_trace_buffer_size[0x8];
10510 u8 trace_mkey[0x20];
10511 u8 reserved_at_60[0x3a0];
10514 struct mlx5_ifc_mtrc_stdb_bits {
10515 u8 string_db_index[0x4];
10516 u8 reserved_at_4[0x4];
10517 u8 read_size[0x18];
10518 u8 start_offset[0x20];
10519 u8 string_db_data[];
10522 struct mlx5_ifc_mtrc_ctrl_bits {
10523 u8 trace_status[0x2];
10524 u8 reserved_at_2[0x2];
10526 u8 reserved_at_5[0xb];
10527 u8 modify_field_select[0x10];
10528 u8 reserved_at_20[0x2b];
10529 u8 current_timestamp52_32[0x15];
10530 u8 current_timestamp31_0[0x20];
10531 u8 reserved_at_80[0x180];
10534 struct mlx5_ifc_host_params_context_bits {
10535 u8 host_number[0x8];
10536 u8 reserved_at_8[0x7];
10537 u8 host_pf_disabled[0x1];
10538 u8 host_num_of_vfs[0x10];
10540 u8 host_total_vfs[0x10];
10541 u8 host_pci_bus[0x10];
10543 u8 reserved_at_40[0x10];
10544 u8 host_pci_device[0x10];
10546 u8 reserved_at_60[0x10];
10547 u8 host_pci_function[0x10];
10549 u8 reserved_at_80[0x180];
10552 struct mlx5_ifc_query_esw_functions_in_bits {
10554 u8 reserved_at_10[0x10];
10556 u8 reserved_at_20[0x10];
10559 u8 reserved_at_40[0x40];
10562 struct mlx5_ifc_query_esw_functions_out_bits {
10564 u8 reserved_at_8[0x18];
10568 u8 reserved_at_40[0x40];
10570 struct mlx5_ifc_host_params_context_bits host_params_context;
10572 u8 reserved_at_280[0x180];
10573 u8 host_sf_enable[][0x40];
10576 struct mlx5_ifc_sf_partition_bits {
10577 u8 reserved_at_0[0x10];
10578 u8 log_num_sf[0x8];
10579 u8 log_sf_bar_size[0x8];
10582 struct mlx5_ifc_query_sf_partitions_out_bits {
10584 u8 reserved_at_8[0x18];
10588 u8 reserved_at_40[0x18];
10589 u8 num_sf_partitions[0x8];
10591 u8 reserved_at_60[0x20];
10593 struct mlx5_ifc_sf_partition_bits sf_partition[];
10596 struct mlx5_ifc_query_sf_partitions_in_bits {
10598 u8 reserved_at_10[0x10];
10600 u8 reserved_at_20[0x10];
10603 u8 reserved_at_40[0x40];
10606 struct mlx5_ifc_dealloc_sf_out_bits {
10608 u8 reserved_at_8[0x18];
10612 u8 reserved_at_40[0x40];
10615 struct mlx5_ifc_dealloc_sf_in_bits {
10617 u8 reserved_at_10[0x10];
10619 u8 reserved_at_20[0x10];
10622 u8 reserved_at_40[0x10];
10623 u8 function_id[0x10];
10625 u8 reserved_at_60[0x20];
10628 struct mlx5_ifc_alloc_sf_out_bits {
10630 u8 reserved_at_8[0x18];
10634 u8 reserved_at_40[0x40];
10637 struct mlx5_ifc_alloc_sf_in_bits {
10639 u8 reserved_at_10[0x10];
10641 u8 reserved_at_20[0x10];
10644 u8 reserved_at_40[0x10];
10645 u8 function_id[0x10];
10647 u8 reserved_at_60[0x20];
10650 struct mlx5_ifc_affiliated_event_header_bits {
10651 u8 reserved_at_0[0x10];
10658 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
10659 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT(0x13),
10663 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
10664 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
10668 MLX5_IPSEC_OBJECT_ICV_LEN_16B,
10669 MLX5_IPSEC_OBJECT_ICV_LEN_12B,
10670 MLX5_IPSEC_OBJECT_ICV_LEN_8B,
10673 struct mlx5_ifc_ipsec_obj_bits {
10674 u8 modify_field_select[0x40];
10675 u8 full_offload[0x1];
10676 u8 reserved_at_41[0x1];
10678 u8 esn_overlap[0x1];
10679 u8 reserved_at_44[0x2];
10680 u8 icv_length[0x2];
10681 u8 reserved_at_48[0x4];
10682 u8 aso_return_reg[0x4];
10683 u8 reserved_at_50[0x10];
10687 u8 reserved_at_80[0x8];
10692 u8 implicit_iv[0x40];
10694 u8 reserved_at_100[0x700];
10697 struct mlx5_ifc_create_ipsec_obj_in_bits {
10698 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10699 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
10703 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
10704 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
10707 struct mlx5_ifc_query_ipsec_obj_out_bits {
10708 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
10709 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
10712 struct mlx5_ifc_modify_ipsec_obj_in_bits {
10713 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10714 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
10717 struct mlx5_ifc_encryption_key_obj_bits {
10718 u8 modify_field_select[0x40];
10720 u8 reserved_at_40[0x14];
10722 u8 reserved_at_58[0x4];
10725 u8 reserved_at_60[0x8];
10728 u8 reserved_at_80[0x180];
10731 u8 reserved_at_300[0x500];
10734 struct mlx5_ifc_create_encryption_key_in_bits {
10735 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10736 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
10740 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10741 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10745 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
10746 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
10749 struct mlx5_ifc_tls_static_params_bits {
10751 u8 tls_version[0x4];
10753 u8 reserved_at_8[0x14];
10754 u8 encryption_standard[0x4];
10756 u8 reserved_at_20[0x20];
10758 u8 initial_record_number[0x40];
10760 u8 resync_tcp_sn[0x20];
10764 u8 implicit_iv[0x40];
10766 u8 reserved_at_100[0x8];
10767 u8 dek_index[0x18];
10769 u8 reserved_at_120[0xe0];
10772 struct mlx5_ifc_tls_progress_params_bits {
10773 u8 next_record_tcp_sn[0x20];
10775 u8 hw_resync_tcp_sn[0x20];
10777 u8 record_tracker_state[0x2];
10778 u8 auth_state[0x2];
10779 u8 reserved_at_44[0x4];
10780 u8 hw_offset_record_number[0x18];
10784 MLX5_MTT_PERM_READ = 1 << 0,
10785 MLX5_MTT_PERM_WRITE = 1 << 1,
10786 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
10789 #endif /* MLX5_IFC_H */