2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include "mlx5_ifc_fpga.h"
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
66 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
67 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
68 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
69 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
74 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
78 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
79 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
80 MLX5_CMD_OP_INIT_HCA = 0x102,
81 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
82 MLX5_CMD_OP_ENABLE_HCA = 0x104,
83 MLX5_CMD_OP_DISABLE_HCA = 0x105,
84 MLX5_CMD_OP_QUERY_PAGES = 0x107,
85 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
86 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
87 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
88 MLX5_CMD_OP_SET_ISSI = 0x10b,
89 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
90 MLX5_CMD_OP_CREATE_MKEY = 0x200,
91 MLX5_CMD_OP_QUERY_MKEY = 0x201,
92 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
93 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
94 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
95 MLX5_CMD_OP_CREATE_EQ = 0x301,
96 MLX5_CMD_OP_DESTROY_EQ = 0x302,
97 MLX5_CMD_OP_QUERY_EQ = 0x303,
98 MLX5_CMD_OP_GEN_EQE = 0x304,
99 MLX5_CMD_OP_CREATE_CQ = 0x400,
100 MLX5_CMD_OP_DESTROY_CQ = 0x401,
101 MLX5_CMD_OP_QUERY_CQ = 0x402,
102 MLX5_CMD_OP_MODIFY_CQ = 0x403,
103 MLX5_CMD_OP_CREATE_QP = 0x500,
104 MLX5_CMD_OP_DESTROY_QP = 0x501,
105 MLX5_CMD_OP_RST2INIT_QP = 0x502,
106 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
107 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
108 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
109 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
110 MLX5_CMD_OP_2ERR_QP = 0x507,
111 MLX5_CMD_OP_2RST_QP = 0x50a,
112 MLX5_CMD_OP_QUERY_QP = 0x50b,
113 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
114 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
115 MLX5_CMD_OP_CREATE_PSV = 0x600,
116 MLX5_CMD_OP_DESTROY_PSV = 0x601,
117 MLX5_CMD_OP_CREATE_SRQ = 0x700,
118 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
119 MLX5_CMD_OP_QUERY_SRQ = 0x702,
120 MLX5_CMD_OP_ARM_RQ = 0x703,
121 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
122 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
123 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
124 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
125 MLX5_CMD_OP_CREATE_DCT = 0x710,
126 MLX5_CMD_OP_DESTROY_DCT = 0x711,
127 MLX5_CMD_OP_DRAIN_DCT = 0x712,
128 MLX5_CMD_OP_QUERY_DCT = 0x713,
129 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
130 MLX5_CMD_OP_CREATE_XRQ = 0x717,
131 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
132 MLX5_CMD_OP_QUERY_XRQ = 0x719,
133 MLX5_CMD_OP_ARM_XRQ = 0x71a,
134 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
135 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
136 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
137 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
138 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
139 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
140 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
141 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
142 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
143 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
144 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
145 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
146 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
147 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
148 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
149 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
150 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
151 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
152 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
153 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
154 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
155 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
156 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
157 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
158 MLX5_CMD_OP_ALLOC_PD = 0x800,
159 MLX5_CMD_OP_DEALLOC_PD = 0x801,
160 MLX5_CMD_OP_ALLOC_UAR = 0x802,
161 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
162 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
163 MLX5_CMD_OP_ACCESS_REG = 0x805,
164 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
165 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
166 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
167 MLX5_CMD_OP_MAD_IFC = 0x50d,
168 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
169 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
170 MLX5_CMD_OP_NOP = 0x80d,
171 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
172 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
173 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
174 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
175 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
176 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
177 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
178 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
179 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
180 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
181 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
182 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
183 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
184 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
185 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
186 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
187 MLX5_CMD_OP_CREATE_LAG = 0x840,
188 MLX5_CMD_OP_MODIFY_LAG = 0x841,
189 MLX5_CMD_OP_QUERY_LAG = 0x842,
190 MLX5_CMD_OP_DESTROY_LAG = 0x843,
191 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
192 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
193 MLX5_CMD_OP_CREATE_TIR = 0x900,
194 MLX5_CMD_OP_MODIFY_TIR = 0x901,
195 MLX5_CMD_OP_DESTROY_TIR = 0x902,
196 MLX5_CMD_OP_QUERY_TIR = 0x903,
197 MLX5_CMD_OP_CREATE_SQ = 0x904,
198 MLX5_CMD_OP_MODIFY_SQ = 0x905,
199 MLX5_CMD_OP_DESTROY_SQ = 0x906,
200 MLX5_CMD_OP_QUERY_SQ = 0x907,
201 MLX5_CMD_OP_CREATE_RQ = 0x908,
202 MLX5_CMD_OP_MODIFY_RQ = 0x909,
203 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
204 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
205 MLX5_CMD_OP_QUERY_RQ = 0x90b,
206 MLX5_CMD_OP_CREATE_RMP = 0x90c,
207 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
208 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
209 MLX5_CMD_OP_QUERY_RMP = 0x90f,
210 MLX5_CMD_OP_CREATE_TIS = 0x912,
211 MLX5_CMD_OP_MODIFY_TIS = 0x913,
212 MLX5_CMD_OP_DESTROY_TIS = 0x914,
213 MLX5_CMD_OP_QUERY_TIS = 0x915,
214 MLX5_CMD_OP_CREATE_RQT = 0x916,
215 MLX5_CMD_OP_MODIFY_RQT = 0x917,
216 MLX5_CMD_OP_DESTROY_RQT = 0x918,
217 MLX5_CMD_OP_QUERY_RQT = 0x919,
218 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
219 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
220 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
221 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
222 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
223 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
224 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
225 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
226 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
227 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
228 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
229 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
230 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
231 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
232 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
233 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
234 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
235 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
236 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
237 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
238 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
239 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
240 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
244 struct mlx5_ifc_flow_table_fields_supported_bits {
247 u8 outer_ether_type[0x1];
248 u8 outer_ip_version[0x1];
249 u8 outer_first_prio[0x1];
250 u8 outer_first_cfi[0x1];
251 u8 outer_first_vid[0x1];
252 u8 outer_ipv4_ttl[0x1];
253 u8 outer_second_prio[0x1];
254 u8 outer_second_cfi[0x1];
255 u8 outer_second_vid[0x1];
256 u8 reserved_at_b[0x1];
260 u8 outer_ip_protocol[0x1];
261 u8 outer_ip_ecn[0x1];
262 u8 outer_ip_dscp[0x1];
263 u8 outer_udp_sport[0x1];
264 u8 outer_udp_dport[0x1];
265 u8 outer_tcp_sport[0x1];
266 u8 outer_tcp_dport[0x1];
267 u8 outer_tcp_flags[0x1];
268 u8 outer_gre_protocol[0x1];
269 u8 outer_gre_key[0x1];
270 u8 outer_vxlan_vni[0x1];
271 u8 reserved_at_1a[0x5];
272 u8 source_eswitch_port[0x1];
276 u8 inner_ether_type[0x1];
277 u8 inner_ip_version[0x1];
278 u8 inner_first_prio[0x1];
279 u8 inner_first_cfi[0x1];
280 u8 inner_first_vid[0x1];
281 u8 reserved_at_27[0x1];
282 u8 inner_second_prio[0x1];
283 u8 inner_second_cfi[0x1];
284 u8 inner_second_vid[0x1];
285 u8 reserved_at_2b[0x1];
289 u8 inner_ip_protocol[0x1];
290 u8 inner_ip_ecn[0x1];
291 u8 inner_ip_dscp[0x1];
292 u8 inner_udp_sport[0x1];
293 u8 inner_udp_dport[0x1];
294 u8 inner_tcp_sport[0x1];
295 u8 inner_tcp_dport[0x1];
296 u8 inner_tcp_flags[0x1];
297 u8 reserved_at_37[0x9];
299 u8 reserved_at_40[0x40];
302 struct mlx5_ifc_flow_table_prop_layout_bits {
304 u8 reserved_at_1[0x1];
305 u8 flow_counter[0x1];
306 u8 flow_modify_en[0x1];
308 u8 identified_miss_table_mode[0x1];
309 u8 flow_table_modify[0x1];
312 u8 reserved_at_9[0x17];
314 u8 reserved_at_20[0x2];
315 u8 log_max_ft_size[0x6];
316 u8 log_max_modify_header_context[0x8];
317 u8 max_modify_header_actions[0x8];
318 u8 max_ft_level[0x8];
320 u8 reserved_at_40[0x20];
322 u8 reserved_at_60[0x18];
323 u8 log_max_ft_num[0x8];
325 u8 reserved_at_80[0x18];
326 u8 log_max_destination[0x8];
328 u8 reserved_at_a0[0x18];
329 u8 log_max_flow[0x8];
331 u8 reserved_at_c0[0x40];
333 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
335 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
338 struct mlx5_ifc_odp_per_transport_service_cap_bits {
345 u8 reserved_at_6[0x1a];
348 struct mlx5_ifc_ipv4_layout_bits {
349 u8 reserved_at_0[0x60];
354 struct mlx5_ifc_ipv6_layout_bits {
358 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
359 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
360 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
361 u8 reserved_at_0[0x80];
364 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
389 u8 reserved_at_c0[0x18];
390 u8 ttl_hoplimit[0x8];
395 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
397 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
400 struct mlx5_ifc_fte_match_set_misc_bits {
401 u8 reserved_at_0[0x8];
404 u8 reserved_at_20[0x10];
405 u8 source_port[0x10];
407 u8 outer_second_prio[0x3];
408 u8 outer_second_cfi[0x1];
409 u8 outer_second_vid[0xc];
410 u8 inner_second_prio[0x3];
411 u8 inner_second_cfi[0x1];
412 u8 inner_second_vid[0xc];
414 u8 outer_second_cvlan_tag[0x1];
415 u8 inner_second_cvlan_tag[0x1];
416 u8 outer_second_svlan_tag[0x1];
417 u8 inner_second_svlan_tag[0x1];
418 u8 reserved_at_64[0xc];
419 u8 gre_protocol[0x10];
425 u8 reserved_at_b8[0x8];
427 u8 reserved_at_c0[0x20];
429 u8 reserved_at_e0[0xc];
430 u8 outer_ipv6_flow_label[0x14];
432 u8 reserved_at_100[0xc];
433 u8 inner_ipv6_flow_label[0x14];
435 u8 reserved_at_120[0xe0];
438 struct mlx5_ifc_cmd_pas_bits {
442 u8 reserved_at_34[0xc];
445 struct mlx5_ifc_uint64_bits {
452 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
453 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
454 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
455 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
456 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
457 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
458 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
459 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
460 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
461 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
464 struct mlx5_ifc_ads_bits {
467 u8 reserved_at_2[0xe];
470 u8 reserved_at_20[0x8];
476 u8 reserved_at_45[0x3];
477 u8 src_addr_index[0x8];
478 u8 reserved_at_50[0x4];
482 u8 reserved_at_60[0x4];
486 u8 rgid_rip[16][0x8];
488 u8 reserved_at_100[0x4];
491 u8 reserved_at_106[0x1];
506 struct mlx5_ifc_flow_table_nic_cap_bits {
507 u8 nic_rx_multi_path_tirs[0x1];
508 u8 nic_rx_multi_path_tirs_fts[0x1];
509 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
510 u8 reserved_at_3[0x1fd];
512 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
514 u8 reserved_at_400[0x200];
516 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
518 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
520 u8 reserved_at_a00[0x200];
522 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
524 u8 reserved_at_e00[0x7200];
527 struct mlx5_ifc_flow_table_eswitch_cap_bits {
528 u8 reserved_at_0[0x200];
530 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
532 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
534 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
536 u8 reserved_at_800[0x7800];
539 struct mlx5_ifc_e_switch_cap_bits {
540 u8 vport_svlan_strip[0x1];
541 u8 vport_cvlan_strip[0x1];
542 u8 vport_svlan_insert[0x1];
543 u8 vport_cvlan_insert_if_not_exist[0x1];
544 u8 vport_cvlan_insert_overwrite[0x1];
545 u8 reserved_at_5[0x19];
546 u8 nic_vport_node_guid_modify[0x1];
547 u8 nic_vport_port_guid_modify[0x1];
549 u8 vxlan_encap_decap[0x1];
550 u8 nvgre_encap_decap[0x1];
551 u8 reserved_at_22[0x9];
552 u8 log_max_encap_headers[0x5];
554 u8 max_encap_header_size[0xa];
556 u8 reserved_40[0x7c0];
560 struct mlx5_ifc_qos_cap_bits {
561 u8 packet_pacing[0x1];
562 u8 esw_scheduling[0x1];
563 u8 esw_bw_share[0x1];
564 u8 esw_rate_limit[0x1];
565 u8 reserved_at_4[0x1c];
567 u8 reserved_at_20[0x20];
569 u8 packet_pacing_max_rate[0x20];
571 u8 packet_pacing_min_rate[0x20];
573 u8 reserved_at_80[0x10];
574 u8 packet_pacing_rate_table_size[0x10];
576 u8 esw_element_type[0x10];
577 u8 esw_tsar_type[0x10];
579 u8 reserved_at_c0[0x10];
580 u8 max_qos_para_vport[0x10];
582 u8 max_tsar_bw_share[0x20];
584 u8 reserved_at_100[0x700];
587 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
591 u8 lro_psh_flag[0x1];
592 u8 lro_time_stamp[0x1];
593 u8 reserved_at_5[0x2];
594 u8 wqe_vlan_insert[0x1];
595 u8 self_lb_en_modifiable[0x1];
596 u8 reserved_at_9[0x2];
598 u8 multi_pkt_send_wqe[0x2];
599 u8 wqe_inline_mode[0x2];
600 u8 rss_ind_tbl_cap[0x4];
603 u8 reserved_at_1a[0x1];
604 u8 tunnel_lso_const_out_ip_id[0x1];
605 u8 reserved_at_1c[0x2];
606 u8 tunnel_statless_gre[0x1];
607 u8 tunnel_stateless_vxlan[0x1];
612 u8 reserved_at_23[0x1d];
614 u8 reserved_at_40[0x10];
615 u8 lro_min_mss_size[0x10];
617 u8 reserved_at_60[0x120];
619 u8 lro_timer_supported_periods[4][0x20];
621 u8 reserved_at_200[0x600];
624 struct mlx5_ifc_roce_cap_bits {
626 u8 reserved_at_1[0x1f];
628 u8 reserved_at_20[0x60];
630 u8 reserved_at_80[0xc];
632 u8 reserved_at_90[0x8];
633 u8 roce_version[0x8];
635 u8 reserved_at_a0[0x10];
636 u8 r_roce_dest_udp_port[0x10];
638 u8 r_roce_max_src_udp_port[0x10];
639 u8 r_roce_min_src_udp_port[0x10];
641 u8 reserved_at_e0[0x10];
642 u8 roce_address_table_size[0x10];
644 u8 reserved_at_100[0x700];
648 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
649 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
650 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
651 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
652 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
653 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
654 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
655 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
656 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
660 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
661 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
662 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
663 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
664 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
665 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
666 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
667 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
668 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
671 struct mlx5_ifc_atomic_caps_bits {
672 u8 reserved_at_0[0x40];
674 u8 atomic_req_8B_endianness_mode[0x2];
675 u8 reserved_at_42[0x4];
676 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
678 u8 reserved_at_47[0x19];
680 u8 reserved_at_60[0x20];
682 u8 reserved_at_80[0x10];
683 u8 atomic_operations[0x10];
685 u8 reserved_at_a0[0x10];
686 u8 atomic_size_qp[0x10];
688 u8 reserved_at_c0[0x10];
689 u8 atomic_size_dc[0x10];
691 u8 reserved_at_e0[0x720];
694 struct mlx5_ifc_odp_cap_bits {
695 u8 reserved_at_0[0x40];
698 u8 reserved_at_41[0x1f];
700 u8 reserved_at_60[0x20];
702 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
704 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
706 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
708 u8 reserved_at_e0[0x720];
711 struct mlx5_ifc_calc_op {
712 u8 reserved_at_0[0x10];
713 u8 reserved_at_10[0x9];
714 u8 op_swap_endianness[0x1];
723 struct mlx5_ifc_vector_calc_cap_bits {
725 u8 reserved_at_1[0x1f];
726 u8 reserved_at_20[0x8];
727 u8 max_vec_count[0x8];
728 u8 reserved_at_30[0xd];
729 u8 max_chunk_size[0x3];
730 struct mlx5_ifc_calc_op calc0;
731 struct mlx5_ifc_calc_op calc1;
732 struct mlx5_ifc_calc_op calc2;
733 struct mlx5_ifc_calc_op calc3;
735 u8 reserved_at_e0[0x720];
739 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
740 MLX5_WQ_TYPE_CYCLIC = 0x1,
741 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
745 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
746 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
750 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
751 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
752 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
753 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
754 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
758 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
759 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
760 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
761 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
762 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
763 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
767 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
768 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
772 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
773 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
774 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
778 MLX5_CAP_PORT_TYPE_IB = 0x0,
779 MLX5_CAP_PORT_TYPE_ETH = 0x1,
783 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
784 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
785 MLX5_CAP_UMR_FENCE_NONE = 0x2,
788 struct mlx5_ifc_cmd_hca_cap_bits {
789 u8 reserved_at_0[0x80];
791 u8 log_max_srq_sz[0x8];
792 u8 log_max_qp_sz[0x8];
793 u8 reserved_at_90[0xb];
796 u8 reserved_at_a0[0xb];
798 u8 reserved_at_b0[0x10];
800 u8 reserved_at_c0[0x8];
801 u8 log_max_cq_sz[0x8];
802 u8 reserved_at_d0[0xb];
805 u8 log_max_eq_sz[0x8];
806 u8 reserved_at_e8[0x2];
807 u8 log_max_mkey[0x6];
808 u8 reserved_at_f0[0xc];
811 u8 max_indirection[0x8];
812 u8 fixed_buffer_size[0x1];
813 u8 log_max_mrw_sz[0x7];
814 u8 force_teardown[0x1];
815 u8 reserved_at_111[0x1];
816 u8 log_max_bsf_list_size[0x6];
817 u8 umr_extended_translation_offset[0x1];
819 u8 log_max_klm_list_size[0x6];
821 u8 reserved_at_120[0xa];
822 u8 log_max_ra_req_dc[0x6];
823 u8 reserved_at_130[0xa];
824 u8 log_max_ra_res_dc[0x6];
826 u8 reserved_at_140[0xa];
827 u8 log_max_ra_req_qp[0x6];
828 u8 reserved_at_150[0xa];
829 u8 log_max_ra_res_qp[0x6];
832 u8 cc_query_allowed[0x1];
833 u8 cc_modify_allowed[0x1];
835 u8 cache_line_128byte[0x1];
836 u8 reserved_at_165[0xb];
837 u8 gid_table_size[0x10];
839 u8 out_of_seq_cnt[0x1];
840 u8 vport_counters[0x1];
841 u8 retransmission_q_counters[0x1];
842 u8 reserved_at_183[0x1];
843 u8 modify_rq_counter_set_id[0x1];
844 u8 rq_delay_drop[0x1];
846 u8 pkey_table_size[0x10];
848 u8 vport_group_manager[0x1];
849 u8 vhca_group_manager[0x1];
852 u8 reserved_at_1a4[0x1];
854 u8 nic_flow_table[0x1];
855 u8 eswitch_flow_table[0x1];
856 u8 early_vf_enable[0x1];
859 u8 local_ca_ack_delay[0x5];
860 u8 port_module_event[0x1];
861 u8 reserved_at_1b1[0x1];
863 u8 reserved_at_1b3[0x1];
864 u8 disable_link_up[0x1];
869 u8 reserved_at_1c0[0x1];
873 u8 reserved_at_1c8[0x4];
875 u8 reserved_at_1d0[0x1];
877 u8 general_notification_event[0x1];
878 u8 reserved_at_1d3[0x2];
882 u8 reserved_at_1d8[0x1];
891 u8 stat_rate_support[0x10];
892 u8 reserved_at_1f0[0xc];
895 u8 compact_address_vector[0x1];
897 u8 reserved_at_202[0x1];
898 u8 ipoib_enhanced_offloads[0x1];
899 u8 ipoib_basic_offloads[0x1];
900 u8 reserved_at_205[0x5];
902 u8 reserved_at_20c[0x3];
903 u8 drain_sigerr[0x1];
904 u8 cmdif_checksum[0x2];
906 u8 reserved_at_213[0x1];
907 u8 wq_signature[0x1];
908 u8 sctr_data_cqe[0x1];
909 u8 reserved_at_216[0x1];
915 u8 eth_net_offloads[0x1];
918 u8 reserved_at_21f[0x1];
922 u8 cq_moderation[0x1];
923 u8 reserved_at_223[0x3];
927 u8 reserved_at_229[0x1];
928 u8 scqe_break_moderation[0x1];
929 u8 cq_period_start_from_cqe[0x1];
931 u8 reserved_at_22d[0x1];
934 u8 umr_ptr_rlky[0x1];
936 u8 reserved_at_232[0x4];
939 u8 set_deth_sqpn[0x1];
940 u8 reserved_at_239[0x3];
947 u8 reserved_at_241[0x9];
949 u8 reserved_at_250[0x8];
953 u8 driver_version[0x1];
954 u8 pad_tx_eth_packet[0x1];
955 u8 reserved_at_263[0x8];
956 u8 log_bf_reg_size[0x5];
958 u8 reserved_at_270[0xb];
960 u8 num_lag_ports[0x4];
962 u8 reserved_at_280[0x10];
963 u8 max_wqe_sz_sq[0x10];
965 u8 reserved_at_2a0[0x10];
966 u8 max_wqe_sz_rq[0x10];
968 u8 reserved_at_2c0[0x10];
969 u8 max_wqe_sz_sq_dc[0x10];
971 u8 reserved_at_2e0[0x7];
974 u8 reserved_at_300[0x18];
977 u8 reserved_at_320[0x3];
978 u8 log_max_transport_domain[0x5];
979 u8 reserved_at_328[0x3];
981 u8 reserved_at_330[0xb];
982 u8 log_max_xrcd[0x5];
984 u8 reserved_at_340[0x8];
985 u8 log_max_flow_counter_bulk[0x8];
986 u8 max_flow_counter[0x10];
989 u8 reserved_at_360[0x3];
991 u8 reserved_at_368[0x3];
993 u8 reserved_at_370[0x3];
995 u8 reserved_at_378[0x3];
998 u8 basic_cyclic_rcv_wqe[0x1];
999 u8 reserved_at_381[0x2];
1000 u8 log_max_rmp[0x5];
1001 u8 reserved_at_388[0x3];
1002 u8 log_max_rqt[0x5];
1003 u8 reserved_at_390[0x3];
1004 u8 log_max_rqt_size[0x5];
1005 u8 reserved_at_398[0x3];
1006 u8 log_max_tis_per_sq[0x5];
1008 u8 reserved_at_3a0[0x3];
1009 u8 log_max_stride_sz_rq[0x5];
1010 u8 reserved_at_3a8[0x3];
1011 u8 log_min_stride_sz_rq[0x5];
1012 u8 reserved_at_3b0[0x3];
1013 u8 log_max_stride_sz_sq[0x5];
1014 u8 reserved_at_3b8[0x3];
1015 u8 log_min_stride_sz_sq[0x5];
1017 u8 reserved_at_3c0[0x1b];
1018 u8 log_max_wq_sz[0x5];
1020 u8 nic_vport_change_event[0x1];
1021 u8 disable_local_lb[0x1];
1022 u8 reserved_at_3e2[0x9];
1023 u8 log_max_vlan_list[0x5];
1024 u8 reserved_at_3f0[0x3];
1025 u8 log_max_current_mc_list[0x5];
1026 u8 reserved_at_3f8[0x3];
1027 u8 log_max_current_uc_list[0x5];
1029 u8 reserved_at_400[0x80];
1031 u8 reserved_at_480[0x3];
1032 u8 log_max_l2_table[0x5];
1033 u8 reserved_at_488[0x8];
1034 u8 log_uar_page_sz[0x10];
1036 u8 reserved_at_4a0[0x20];
1037 u8 device_frequency_mhz[0x20];
1038 u8 device_frequency_khz[0x20];
1040 u8 reserved_at_500[0x20];
1041 u8 num_of_uars_per_page[0x20];
1042 u8 reserved_at_540[0x40];
1044 u8 reserved_at_580[0x3f];
1045 u8 cqe_compression[0x1];
1047 u8 cqe_compression_timeout[0x10];
1048 u8 cqe_compression_max_num[0x10];
1050 u8 reserved_at_5e0[0x10];
1051 u8 tag_matching[0x1];
1052 u8 rndv_offload_rc[0x1];
1053 u8 rndv_offload_dc[0x1];
1054 u8 log_tag_matching_list_sz[0x5];
1055 u8 reserved_at_5f8[0x3];
1056 u8 log_max_xrq[0x5];
1058 u8 reserved_at_600[0x200];
1061 enum mlx5_flow_destination_type {
1062 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1063 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1064 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1066 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1069 struct mlx5_ifc_dest_format_struct_bits {
1070 u8 destination_type[0x8];
1071 u8 destination_id[0x18];
1073 u8 reserved_at_20[0x20];
1076 struct mlx5_ifc_flow_counter_list_bits {
1078 u8 num_of_counters[0xf];
1079 u8 flow_counter_id[0x10];
1081 u8 reserved_at_20[0x20];
1084 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1085 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1086 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1087 u8 reserved_at_0[0x40];
1090 struct mlx5_ifc_fte_match_param_bits {
1091 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1093 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1095 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1097 u8 reserved_at_600[0xa00];
1101 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1102 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1103 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1104 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1105 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1108 struct mlx5_ifc_rx_hash_field_select_bits {
1109 u8 l3_prot_type[0x1];
1110 u8 l4_prot_type[0x1];
1111 u8 selected_fields[0x1e];
1115 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1116 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1120 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1121 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1124 struct mlx5_ifc_wq_bits {
1126 u8 wq_signature[0x1];
1127 u8 end_padding_mode[0x2];
1129 u8 reserved_at_8[0x18];
1131 u8 hds_skip_first_sge[0x1];
1132 u8 log2_hds_buf_size[0x3];
1133 u8 reserved_at_24[0x7];
1134 u8 page_offset[0x5];
1137 u8 reserved_at_40[0x8];
1140 u8 reserved_at_60[0x8];
1145 u8 hw_counter[0x20];
1147 u8 sw_counter[0x20];
1149 u8 reserved_at_100[0xc];
1150 u8 log_wq_stride[0x4];
1151 u8 reserved_at_110[0x3];
1152 u8 log_wq_pg_sz[0x5];
1153 u8 reserved_at_118[0x3];
1156 u8 reserved_at_120[0x15];
1157 u8 log_wqe_num_of_strides[0x3];
1158 u8 two_byte_shift_en[0x1];
1159 u8 reserved_at_139[0x4];
1160 u8 log_wqe_stride_size[0x3];
1162 u8 reserved_at_140[0x4c0];
1164 struct mlx5_ifc_cmd_pas_bits pas[0];
1167 struct mlx5_ifc_rq_num_bits {
1168 u8 reserved_at_0[0x8];
1172 struct mlx5_ifc_mac_address_layout_bits {
1173 u8 reserved_at_0[0x10];
1174 u8 mac_addr_47_32[0x10];
1176 u8 mac_addr_31_0[0x20];
1179 struct mlx5_ifc_vlan_layout_bits {
1180 u8 reserved_at_0[0x14];
1183 u8 reserved_at_20[0x20];
1186 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1187 u8 reserved_at_0[0xa0];
1189 u8 min_time_between_cnps[0x20];
1191 u8 reserved_at_c0[0x12];
1193 u8 reserved_at_d8[0x4];
1194 u8 cnp_prio_mode[0x1];
1195 u8 cnp_802p_prio[0x3];
1197 u8 reserved_at_e0[0x720];
1200 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1201 u8 reserved_at_0[0x60];
1203 u8 reserved_at_60[0x4];
1204 u8 clamp_tgt_rate[0x1];
1205 u8 reserved_at_65[0x3];
1206 u8 clamp_tgt_rate_after_time_inc[0x1];
1207 u8 reserved_at_69[0x17];
1209 u8 reserved_at_80[0x20];
1211 u8 rpg_time_reset[0x20];
1213 u8 rpg_byte_reset[0x20];
1215 u8 rpg_threshold[0x20];
1217 u8 rpg_max_rate[0x20];
1219 u8 rpg_ai_rate[0x20];
1221 u8 rpg_hai_rate[0x20];
1225 u8 rpg_min_dec_fac[0x20];
1227 u8 rpg_min_rate[0x20];
1229 u8 reserved_at_1c0[0xe0];
1231 u8 rate_to_set_on_first_cnp[0x20];
1235 u8 dce_tcp_rtt[0x20];
1237 u8 rate_reduce_monitor_period[0x20];
1239 u8 reserved_at_320[0x20];
1241 u8 initial_alpha_value[0x20];
1243 u8 reserved_at_360[0x4a0];
1246 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1247 u8 reserved_at_0[0x80];
1249 u8 rppp_max_rps[0x20];
1251 u8 rpg_time_reset[0x20];
1253 u8 rpg_byte_reset[0x20];
1255 u8 rpg_threshold[0x20];
1257 u8 rpg_max_rate[0x20];
1259 u8 rpg_ai_rate[0x20];
1261 u8 rpg_hai_rate[0x20];
1265 u8 rpg_min_dec_fac[0x20];
1267 u8 rpg_min_rate[0x20];
1269 u8 reserved_at_1c0[0x640];
1273 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1274 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1275 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1278 struct mlx5_ifc_resize_field_select_bits {
1279 u8 resize_field_select[0x20];
1283 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1284 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1285 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1286 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1289 struct mlx5_ifc_modify_field_select_bits {
1290 u8 modify_field_select[0x20];
1293 struct mlx5_ifc_field_select_r_roce_np_bits {
1294 u8 field_select_r_roce_np[0x20];
1297 struct mlx5_ifc_field_select_r_roce_rp_bits {
1298 u8 field_select_r_roce_rp[0x20];
1302 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1303 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1304 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1305 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1306 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1307 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1308 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1309 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1310 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1311 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1314 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1315 u8 field_select_8021qaurp[0x20];
1318 struct mlx5_ifc_phys_layer_cntrs_bits {
1319 u8 time_since_last_clear_high[0x20];
1321 u8 time_since_last_clear_low[0x20];
1323 u8 symbol_errors_high[0x20];
1325 u8 symbol_errors_low[0x20];
1327 u8 sync_headers_errors_high[0x20];
1329 u8 sync_headers_errors_low[0x20];
1331 u8 edpl_bip_errors_lane0_high[0x20];
1333 u8 edpl_bip_errors_lane0_low[0x20];
1335 u8 edpl_bip_errors_lane1_high[0x20];
1337 u8 edpl_bip_errors_lane1_low[0x20];
1339 u8 edpl_bip_errors_lane2_high[0x20];
1341 u8 edpl_bip_errors_lane2_low[0x20];
1343 u8 edpl_bip_errors_lane3_high[0x20];
1345 u8 edpl_bip_errors_lane3_low[0x20];
1347 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1349 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1351 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1353 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1355 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1357 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1359 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1361 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1363 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1365 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1367 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1369 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1371 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1373 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1375 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1377 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1379 u8 rs_fec_corrected_blocks_high[0x20];
1381 u8 rs_fec_corrected_blocks_low[0x20];
1383 u8 rs_fec_uncorrectable_blocks_high[0x20];
1385 u8 rs_fec_uncorrectable_blocks_low[0x20];
1387 u8 rs_fec_no_errors_blocks_high[0x20];
1389 u8 rs_fec_no_errors_blocks_low[0x20];
1391 u8 rs_fec_single_error_blocks_high[0x20];
1393 u8 rs_fec_single_error_blocks_low[0x20];
1395 u8 rs_fec_corrected_symbols_total_high[0x20];
1397 u8 rs_fec_corrected_symbols_total_low[0x20];
1399 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1401 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1403 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1405 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1407 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1409 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1411 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1413 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1415 u8 link_down_events[0x20];
1417 u8 successful_recovery_events[0x20];
1419 u8 reserved_at_640[0x180];
1422 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1423 u8 time_since_last_clear_high[0x20];
1425 u8 time_since_last_clear_low[0x20];
1427 u8 phy_received_bits_high[0x20];
1429 u8 phy_received_bits_low[0x20];
1431 u8 phy_symbol_errors_high[0x20];
1433 u8 phy_symbol_errors_low[0x20];
1435 u8 phy_corrected_bits_high[0x20];
1437 u8 phy_corrected_bits_low[0x20];
1439 u8 phy_corrected_bits_lane0_high[0x20];
1441 u8 phy_corrected_bits_lane0_low[0x20];
1443 u8 phy_corrected_bits_lane1_high[0x20];
1445 u8 phy_corrected_bits_lane1_low[0x20];
1447 u8 phy_corrected_bits_lane2_high[0x20];
1449 u8 phy_corrected_bits_lane2_low[0x20];
1451 u8 phy_corrected_bits_lane3_high[0x20];
1453 u8 phy_corrected_bits_lane3_low[0x20];
1455 u8 reserved_at_200[0x5c0];
1458 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1459 u8 symbol_error_counter[0x10];
1461 u8 link_error_recovery_counter[0x8];
1463 u8 link_downed_counter[0x8];
1465 u8 port_rcv_errors[0x10];
1467 u8 port_rcv_remote_physical_errors[0x10];
1469 u8 port_rcv_switch_relay_errors[0x10];
1471 u8 port_xmit_discards[0x10];
1473 u8 port_xmit_constraint_errors[0x8];
1475 u8 port_rcv_constraint_errors[0x8];
1477 u8 reserved_at_70[0x8];
1479 u8 link_overrun_errors[0x8];
1481 u8 reserved_at_80[0x10];
1483 u8 vl_15_dropped[0x10];
1485 u8 reserved_at_a0[0x80];
1487 u8 port_xmit_wait[0x20];
1490 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1491 u8 transmit_queue_high[0x20];
1493 u8 transmit_queue_low[0x20];
1495 u8 reserved_at_40[0x780];
1498 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1499 u8 rx_octets_high[0x20];
1501 u8 rx_octets_low[0x20];
1503 u8 reserved_at_40[0xc0];
1505 u8 rx_frames_high[0x20];
1507 u8 rx_frames_low[0x20];
1509 u8 tx_octets_high[0x20];
1511 u8 tx_octets_low[0x20];
1513 u8 reserved_at_180[0xc0];
1515 u8 tx_frames_high[0x20];
1517 u8 tx_frames_low[0x20];
1519 u8 rx_pause_high[0x20];
1521 u8 rx_pause_low[0x20];
1523 u8 rx_pause_duration_high[0x20];
1525 u8 rx_pause_duration_low[0x20];
1527 u8 tx_pause_high[0x20];
1529 u8 tx_pause_low[0x20];
1531 u8 tx_pause_duration_high[0x20];
1533 u8 tx_pause_duration_low[0x20];
1535 u8 rx_pause_transition_high[0x20];
1537 u8 rx_pause_transition_low[0x20];
1539 u8 reserved_at_3c0[0x400];
1542 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1543 u8 port_transmit_wait_high[0x20];
1545 u8 port_transmit_wait_low[0x20];
1547 u8 reserved_at_40[0x780];
1550 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1551 u8 dot3stats_alignment_errors_high[0x20];
1553 u8 dot3stats_alignment_errors_low[0x20];
1555 u8 dot3stats_fcs_errors_high[0x20];
1557 u8 dot3stats_fcs_errors_low[0x20];
1559 u8 dot3stats_single_collision_frames_high[0x20];
1561 u8 dot3stats_single_collision_frames_low[0x20];
1563 u8 dot3stats_multiple_collision_frames_high[0x20];
1565 u8 dot3stats_multiple_collision_frames_low[0x20];
1567 u8 dot3stats_sqe_test_errors_high[0x20];
1569 u8 dot3stats_sqe_test_errors_low[0x20];
1571 u8 dot3stats_deferred_transmissions_high[0x20];
1573 u8 dot3stats_deferred_transmissions_low[0x20];
1575 u8 dot3stats_late_collisions_high[0x20];
1577 u8 dot3stats_late_collisions_low[0x20];
1579 u8 dot3stats_excessive_collisions_high[0x20];
1581 u8 dot3stats_excessive_collisions_low[0x20];
1583 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1585 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1587 u8 dot3stats_carrier_sense_errors_high[0x20];
1589 u8 dot3stats_carrier_sense_errors_low[0x20];
1591 u8 dot3stats_frame_too_longs_high[0x20];
1593 u8 dot3stats_frame_too_longs_low[0x20];
1595 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1597 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1599 u8 dot3stats_symbol_errors_high[0x20];
1601 u8 dot3stats_symbol_errors_low[0x20];
1603 u8 dot3control_in_unknown_opcodes_high[0x20];
1605 u8 dot3control_in_unknown_opcodes_low[0x20];
1607 u8 dot3in_pause_frames_high[0x20];
1609 u8 dot3in_pause_frames_low[0x20];
1611 u8 dot3out_pause_frames_high[0x20];
1613 u8 dot3out_pause_frames_low[0x20];
1615 u8 reserved_at_400[0x3c0];
1618 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1619 u8 ether_stats_drop_events_high[0x20];
1621 u8 ether_stats_drop_events_low[0x20];
1623 u8 ether_stats_octets_high[0x20];
1625 u8 ether_stats_octets_low[0x20];
1627 u8 ether_stats_pkts_high[0x20];
1629 u8 ether_stats_pkts_low[0x20];
1631 u8 ether_stats_broadcast_pkts_high[0x20];
1633 u8 ether_stats_broadcast_pkts_low[0x20];
1635 u8 ether_stats_multicast_pkts_high[0x20];
1637 u8 ether_stats_multicast_pkts_low[0x20];
1639 u8 ether_stats_crc_align_errors_high[0x20];
1641 u8 ether_stats_crc_align_errors_low[0x20];
1643 u8 ether_stats_undersize_pkts_high[0x20];
1645 u8 ether_stats_undersize_pkts_low[0x20];
1647 u8 ether_stats_oversize_pkts_high[0x20];
1649 u8 ether_stats_oversize_pkts_low[0x20];
1651 u8 ether_stats_fragments_high[0x20];
1653 u8 ether_stats_fragments_low[0x20];
1655 u8 ether_stats_jabbers_high[0x20];
1657 u8 ether_stats_jabbers_low[0x20];
1659 u8 ether_stats_collisions_high[0x20];
1661 u8 ether_stats_collisions_low[0x20];
1663 u8 ether_stats_pkts64octets_high[0x20];
1665 u8 ether_stats_pkts64octets_low[0x20];
1667 u8 ether_stats_pkts65to127octets_high[0x20];
1669 u8 ether_stats_pkts65to127octets_low[0x20];
1671 u8 ether_stats_pkts128to255octets_high[0x20];
1673 u8 ether_stats_pkts128to255octets_low[0x20];
1675 u8 ether_stats_pkts256to511octets_high[0x20];
1677 u8 ether_stats_pkts256to511octets_low[0x20];
1679 u8 ether_stats_pkts512to1023octets_high[0x20];
1681 u8 ether_stats_pkts512to1023octets_low[0x20];
1683 u8 ether_stats_pkts1024to1518octets_high[0x20];
1685 u8 ether_stats_pkts1024to1518octets_low[0x20];
1687 u8 ether_stats_pkts1519to2047octets_high[0x20];
1689 u8 ether_stats_pkts1519to2047octets_low[0x20];
1691 u8 ether_stats_pkts2048to4095octets_high[0x20];
1693 u8 ether_stats_pkts2048to4095octets_low[0x20];
1695 u8 ether_stats_pkts4096to8191octets_high[0x20];
1697 u8 ether_stats_pkts4096to8191octets_low[0x20];
1699 u8 ether_stats_pkts8192to10239octets_high[0x20];
1701 u8 ether_stats_pkts8192to10239octets_low[0x20];
1703 u8 reserved_at_540[0x280];
1706 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1707 u8 if_in_octets_high[0x20];
1709 u8 if_in_octets_low[0x20];
1711 u8 if_in_ucast_pkts_high[0x20];
1713 u8 if_in_ucast_pkts_low[0x20];
1715 u8 if_in_discards_high[0x20];
1717 u8 if_in_discards_low[0x20];
1719 u8 if_in_errors_high[0x20];
1721 u8 if_in_errors_low[0x20];
1723 u8 if_in_unknown_protos_high[0x20];
1725 u8 if_in_unknown_protos_low[0x20];
1727 u8 if_out_octets_high[0x20];
1729 u8 if_out_octets_low[0x20];
1731 u8 if_out_ucast_pkts_high[0x20];
1733 u8 if_out_ucast_pkts_low[0x20];
1735 u8 if_out_discards_high[0x20];
1737 u8 if_out_discards_low[0x20];
1739 u8 if_out_errors_high[0x20];
1741 u8 if_out_errors_low[0x20];
1743 u8 if_in_multicast_pkts_high[0x20];
1745 u8 if_in_multicast_pkts_low[0x20];
1747 u8 if_in_broadcast_pkts_high[0x20];
1749 u8 if_in_broadcast_pkts_low[0x20];
1751 u8 if_out_multicast_pkts_high[0x20];
1753 u8 if_out_multicast_pkts_low[0x20];
1755 u8 if_out_broadcast_pkts_high[0x20];
1757 u8 if_out_broadcast_pkts_low[0x20];
1759 u8 reserved_at_340[0x480];
1762 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1763 u8 a_frames_transmitted_ok_high[0x20];
1765 u8 a_frames_transmitted_ok_low[0x20];
1767 u8 a_frames_received_ok_high[0x20];
1769 u8 a_frames_received_ok_low[0x20];
1771 u8 a_frame_check_sequence_errors_high[0x20];
1773 u8 a_frame_check_sequence_errors_low[0x20];
1775 u8 a_alignment_errors_high[0x20];
1777 u8 a_alignment_errors_low[0x20];
1779 u8 a_octets_transmitted_ok_high[0x20];
1781 u8 a_octets_transmitted_ok_low[0x20];
1783 u8 a_octets_received_ok_high[0x20];
1785 u8 a_octets_received_ok_low[0x20];
1787 u8 a_multicast_frames_xmitted_ok_high[0x20];
1789 u8 a_multicast_frames_xmitted_ok_low[0x20];
1791 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1793 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1795 u8 a_multicast_frames_received_ok_high[0x20];
1797 u8 a_multicast_frames_received_ok_low[0x20];
1799 u8 a_broadcast_frames_received_ok_high[0x20];
1801 u8 a_broadcast_frames_received_ok_low[0x20];
1803 u8 a_in_range_length_errors_high[0x20];
1805 u8 a_in_range_length_errors_low[0x20];
1807 u8 a_out_of_range_length_field_high[0x20];
1809 u8 a_out_of_range_length_field_low[0x20];
1811 u8 a_frame_too_long_errors_high[0x20];
1813 u8 a_frame_too_long_errors_low[0x20];
1815 u8 a_symbol_error_during_carrier_high[0x20];
1817 u8 a_symbol_error_during_carrier_low[0x20];
1819 u8 a_mac_control_frames_transmitted_high[0x20];
1821 u8 a_mac_control_frames_transmitted_low[0x20];
1823 u8 a_mac_control_frames_received_high[0x20];
1825 u8 a_mac_control_frames_received_low[0x20];
1827 u8 a_unsupported_opcodes_received_high[0x20];
1829 u8 a_unsupported_opcodes_received_low[0x20];
1831 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1833 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1835 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1837 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1839 u8 reserved_at_4c0[0x300];
1842 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1843 u8 life_time_counter_high[0x20];
1845 u8 life_time_counter_low[0x20];
1851 u8 l0_to_recovery_eieos[0x20];
1853 u8 l0_to_recovery_ts[0x20];
1855 u8 l0_to_recovery_framing[0x20];
1857 u8 l0_to_recovery_retrain[0x20];
1859 u8 crc_error_dllp[0x20];
1861 u8 crc_error_tlp[0x20];
1863 u8 reserved_at_140[0x680];
1866 struct mlx5_ifc_cmd_inter_comp_event_bits {
1867 u8 command_completion_vector[0x20];
1869 u8 reserved_at_20[0xc0];
1872 struct mlx5_ifc_stall_vl_event_bits {
1873 u8 reserved_at_0[0x18];
1875 u8 reserved_at_19[0x3];
1878 u8 reserved_at_20[0xa0];
1881 struct mlx5_ifc_db_bf_congestion_event_bits {
1882 u8 event_subtype[0x8];
1883 u8 reserved_at_8[0x8];
1884 u8 congestion_level[0x8];
1885 u8 reserved_at_18[0x8];
1887 u8 reserved_at_20[0xa0];
1890 struct mlx5_ifc_gpio_event_bits {
1891 u8 reserved_at_0[0x60];
1893 u8 gpio_event_hi[0x20];
1895 u8 gpio_event_lo[0x20];
1897 u8 reserved_at_a0[0x40];
1900 struct mlx5_ifc_port_state_change_event_bits {
1901 u8 reserved_at_0[0x40];
1904 u8 reserved_at_44[0x1c];
1906 u8 reserved_at_60[0x80];
1909 struct mlx5_ifc_dropped_packet_logged_bits {
1910 u8 reserved_at_0[0xe0];
1914 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1915 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1918 struct mlx5_ifc_cq_error_bits {
1919 u8 reserved_at_0[0x8];
1922 u8 reserved_at_20[0x20];
1924 u8 reserved_at_40[0x18];
1927 u8 reserved_at_60[0x80];
1930 struct mlx5_ifc_rdma_page_fault_event_bits {
1931 u8 bytes_committed[0x20];
1935 u8 reserved_at_40[0x10];
1936 u8 packet_len[0x10];
1938 u8 rdma_op_len[0x20];
1942 u8 reserved_at_c0[0x5];
1949 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1950 u8 bytes_committed[0x20];
1952 u8 reserved_at_20[0x10];
1955 u8 reserved_at_40[0x10];
1958 u8 reserved_at_60[0x60];
1960 u8 reserved_at_c0[0x5];
1967 struct mlx5_ifc_qp_events_bits {
1968 u8 reserved_at_0[0xa0];
1971 u8 reserved_at_a8[0x18];
1973 u8 reserved_at_c0[0x8];
1974 u8 qpn_rqn_sqn[0x18];
1977 struct mlx5_ifc_dct_events_bits {
1978 u8 reserved_at_0[0xc0];
1980 u8 reserved_at_c0[0x8];
1981 u8 dct_number[0x18];
1984 struct mlx5_ifc_comp_event_bits {
1985 u8 reserved_at_0[0xc0];
1987 u8 reserved_at_c0[0x8];
1992 MLX5_QPC_STATE_RST = 0x0,
1993 MLX5_QPC_STATE_INIT = 0x1,
1994 MLX5_QPC_STATE_RTR = 0x2,
1995 MLX5_QPC_STATE_RTS = 0x3,
1996 MLX5_QPC_STATE_SQER = 0x4,
1997 MLX5_QPC_STATE_ERR = 0x6,
1998 MLX5_QPC_STATE_SQD = 0x7,
1999 MLX5_QPC_STATE_SUSPENDED = 0x9,
2003 MLX5_QPC_ST_RC = 0x0,
2004 MLX5_QPC_ST_UC = 0x1,
2005 MLX5_QPC_ST_UD = 0x2,
2006 MLX5_QPC_ST_XRC = 0x3,
2007 MLX5_QPC_ST_DCI = 0x5,
2008 MLX5_QPC_ST_QP0 = 0x7,
2009 MLX5_QPC_ST_QP1 = 0x8,
2010 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2011 MLX5_QPC_ST_REG_UMR = 0xc,
2015 MLX5_QPC_PM_STATE_ARMED = 0x0,
2016 MLX5_QPC_PM_STATE_REARM = 0x1,
2017 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2018 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2022 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2023 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2027 MLX5_QPC_MTU_256_BYTES = 0x1,
2028 MLX5_QPC_MTU_512_BYTES = 0x2,
2029 MLX5_QPC_MTU_1K_BYTES = 0x3,
2030 MLX5_QPC_MTU_2K_BYTES = 0x4,
2031 MLX5_QPC_MTU_4K_BYTES = 0x5,
2032 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2036 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2037 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2038 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2039 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2040 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2041 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2042 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2043 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2047 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2048 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2049 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2053 MLX5_QPC_CS_RES_DISABLE = 0x0,
2054 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2055 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2058 struct mlx5_ifc_qpc_bits {
2060 u8 lag_tx_port_affinity[0x4];
2062 u8 reserved_at_10[0x3];
2064 u8 reserved_at_15[0x7];
2065 u8 end_padding_mode[0x2];
2066 u8 reserved_at_1e[0x2];
2068 u8 wq_signature[0x1];
2069 u8 block_lb_mc[0x1];
2070 u8 atomic_like_write_en[0x1];
2071 u8 latency_sensitive[0x1];
2072 u8 reserved_at_24[0x1];
2073 u8 drain_sigerr[0x1];
2074 u8 reserved_at_26[0x2];
2078 u8 log_msg_max[0x5];
2079 u8 reserved_at_48[0x1];
2080 u8 log_rq_size[0x4];
2081 u8 log_rq_stride[0x3];
2083 u8 log_sq_size[0x4];
2084 u8 reserved_at_55[0x6];
2086 u8 ulp_stateless_offload_mode[0x4];
2088 u8 counter_set_id[0x8];
2091 u8 reserved_at_80[0x8];
2092 u8 user_index[0x18];
2094 u8 reserved_at_a0[0x3];
2095 u8 log_page_size[0x5];
2096 u8 remote_qpn[0x18];
2098 struct mlx5_ifc_ads_bits primary_address_path;
2100 struct mlx5_ifc_ads_bits secondary_address_path;
2102 u8 log_ack_req_freq[0x4];
2103 u8 reserved_at_384[0x4];
2104 u8 log_sra_max[0x3];
2105 u8 reserved_at_38b[0x2];
2106 u8 retry_count[0x3];
2108 u8 reserved_at_393[0x1];
2110 u8 cur_rnr_retry[0x3];
2111 u8 cur_retry_count[0x3];
2112 u8 reserved_at_39b[0x5];
2114 u8 reserved_at_3a0[0x20];
2116 u8 reserved_at_3c0[0x8];
2117 u8 next_send_psn[0x18];
2119 u8 reserved_at_3e0[0x8];
2122 u8 reserved_at_400[0x8];
2125 u8 reserved_at_420[0x20];
2127 u8 reserved_at_440[0x8];
2128 u8 last_acked_psn[0x18];
2130 u8 reserved_at_460[0x8];
2133 u8 reserved_at_480[0x8];
2134 u8 log_rra_max[0x3];
2135 u8 reserved_at_48b[0x1];
2136 u8 atomic_mode[0x4];
2140 u8 reserved_at_493[0x1];
2141 u8 page_offset[0x6];
2142 u8 reserved_at_49a[0x3];
2143 u8 cd_slave_receive[0x1];
2144 u8 cd_slave_send[0x1];
2147 u8 reserved_at_4a0[0x3];
2148 u8 min_rnr_nak[0x5];
2149 u8 next_rcv_psn[0x18];
2151 u8 reserved_at_4c0[0x8];
2154 u8 reserved_at_4e0[0x8];
2161 u8 reserved_at_560[0x5];
2163 u8 srqn_rmpn_xrqn[0x18];
2165 u8 reserved_at_580[0x8];
2168 u8 hw_sq_wqebb_counter[0x10];
2169 u8 sw_sq_wqebb_counter[0x10];
2171 u8 hw_rq_counter[0x20];
2173 u8 sw_rq_counter[0x20];
2175 u8 reserved_at_600[0x20];
2177 u8 reserved_at_620[0xf];
2182 u8 dc_access_key[0x40];
2184 u8 reserved_at_680[0xc0];
2187 struct mlx5_ifc_roce_addr_layout_bits {
2188 u8 source_l3_address[16][0x8];
2190 u8 reserved_at_80[0x3];
2193 u8 source_mac_47_32[0x10];
2195 u8 source_mac_31_0[0x20];
2197 u8 reserved_at_c0[0x14];
2198 u8 roce_l3_type[0x4];
2199 u8 roce_version[0x8];
2201 u8 reserved_at_e0[0x20];
2204 union mlx5_ifc_hca_cap_union_bits {
2205 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2206 struct mlx5_ifc_odp_cap_bits odp_cap;
2207 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2208 struct mlx5_ifc_roce_cap_bits roce_cap;
2209 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2210 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2211 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2212 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2213 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2214 struct mlx5_ifc_qos_cap_bits qos_cap;
2215 struct mlx5_ifc_fpga_cap_bits fpga_cap;
2216 u8 reserved_at_0[0x8000];
2220 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2221 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2222 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2223 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2224 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2225 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2226 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
2229 struct mlx5_ifc_flow_context_bits {
2230 u8 reserved_at_0[0x20];
2234 u8 reserved_at_40[0x8];
2237 u8 reserved_at_60[0x10];
2240 u8 reserved_at_80[0x8];
2241 u8 destination_list_size[0x18];
2243 u8 reserved_at_a0[0x8];
2244 u8 flow_counter_list_size[0x18];
2248 u8 modify_header_id[0x20];
2250 u8 reserved_at_100[0x100];
2252 struct mlx5_ifc_fte_match_param_bits match_value;
2254 u8 reserved_at_1200[0x600];
2256 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2260 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2261 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2264 struct mlx5_ifc_xrc_srqc_bits {
2266 u8 log_xrc_srq_size[0x4];
2267 u8 reserved_at_8[0x18];
2269 u8 wq_signature[0x1];
2271 u8 reserved_at_22[0x1];
2273 u8 basic_cyclic_rcv_wqe[0x1];
2274 u8 log_rq_stride[0x3];
2277 u8 page_offset[0x6];
2278 u8 reserved_at_46[0x2];
2281 u8 reserved_at_60[0x20];
2283 u8 user_index_equal_xrc_srqn[0x1];
2284 u8 reserved_at_81[0x1];
2285 u8 log_page_size[0x6];
2286 u8 user_index[0x18];
2288 u8 reserved_at_a0[0x20];
2290 u8 reserved_at_c0[0x8];
2296 u8 reserved_at_100[0x40];
2298 u8 db_record_addr_h[0x20];
2300 u8 db_record_addr_l[0x1e];
2301 u8 reserved_at_17e[0x2];
2303 u8 reserved_at_180[0x80];
2306 struct mlx5_ifc_traffic_counter_bits {
2312 struct mlx5_ifc_tisc_bits {
2313 u8 strict_lag_tx_port_affinity[0x1];
2314 u8 reserved_at_1[0x3];
2315 u8 lag_tx_port_affinity[0x04];
2317 u8 reserved_at_8[0x4];
2319 u8 reserved_at_10[0x10];
2321 u8 reserved_at_20[0x100];
2323 u8 reserved_at_120[0x8];
2324 u8 transport_domain[0x18];
2326 u8 reserved_at_140[0x8];
2327 u8 underlay_qpn[0x18];
2328 u8 reserved_at_160[0x3a0];
2332 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2333 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2337 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2338 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2342 MLX5_RX_HASH_FN_NONE = 0x0,
2343 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2344 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2348 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2349 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2352 struct mlx5_ifc_tirc_bits {
2353 u8 reserved_at_0[0x20];
2356 u8 reserved_at_24[0x1c];
2358 u8 reserved_at_40[0x40];
2360 u8 reserved_at_80[0x4];
2361 u8 lro_timeout_period_usecs[0x10];
2362 u8 lro_enable_mask[0x4];
2363 u8 lro_max_ip_payload_size[0x8];
2365 u8 reserved_at_a0[0x40];
2367 u8 reserved_at_e0[0x8];
2368 u8 inline_rqn[0x18];
2370 u8 rx_hash_symmetric[0x1];
2371 u8 reserved_at_101[0x1];
2372 u8 tunneled_offload_en[0x1];
2373 u8 reserved_at_103[0x5];
2374 u8 indirect_table[0x18];
2377 u8 reserved_at_124[0x2];
2378 u8 self_lb_block[0x2];
2379 u8 transport_domain[0x18];
2381 u8 rx_hash_toeplitz_key[10][0x20];
2383 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2385 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2387 u8 reserved_at_2c0[0x4c0];
2391 MLX5_SRQC_STATE_GOOD = 0x0,
2392 MLX5_SRQC_STATE_ERROR = 0x1,
2395 struct mlx5_ifc_srqc_bits {
2397 u8 log_srq_size[0x4];
2398 u8 reserved_at_8[0x18];
2400 u8 wq_signature[0x1];
2402 u8 reserved_at_22[0x1];
2404 u8 reserved_at_24[0x1];
2405 u8 log_rq_stride[0x3];
2408 u8 page_offset[0x6];
2409 u8 reserved_at_46[0x2];
2412 u8 reserved_at_60[0x20];
2414 u8 reserved_at_80[0x2];
2415 u8 log_page_size[0x6];
2416 u8 reserved_at_88[0x18];
2418 u8 reserved_at_a0[0x20];
2420 u8 reserved_at_c0[0x8];
2426 u8 reserved_at_100[0x40];
2430 u8 reserved_at_180[0x80];
2434 MLX5_SQC_STATE_RST = 0x0,
2435 MLX5_SQC_STATE_RDY = 0x1,
2436 MLX5_SQC_STATE_ERR = 0x3,
2439 struct mlx5_ifc_sqc_bits {
2443 u8 flush_in_error_en[0x1];
2444 u8 reserved_at_4[0x1];
2445 u8 min_wqe_inline_mode[0x3];
2449 u8 reserved_at_e[0x12];
2451 u8 reserved_at_20[0x8];
2452 u8 user_index[0x18];
2454 u8 reserved_at_40[0x8];
2457 u8 reserved_at_60[0x90];
2459 u8 packet_pacing_rate_limit_index[0x10];
2460 u8 tis_lst_sz[0x10];
2461 u8 reserved_at_110[0x10];
2463 u8 reserved_at_120[0x40];
2465 u8 reserved_at_160[0x8];
2468 struct mlx5_ifc_wq_bits wq;
2472 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2473 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2474 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2475 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2478 struct mlx5_ifc_scheduling_context_bits {
2479 u8 element_type[0x8];
2480 u8 reserved_at_8[0x18];
2482 u8 element_attributes[0x20];
2484 u8 parent_element_id[0x20];
2486 u8 reserved_at_60[0x40];
2490 u8 max_average_bw[0x20];
2492 u8 reserved_at_e0[0x120];
2495 struct mlx5_ifc_rqtc_bits {
2496 u8 reserved_at_0[0xa0];
2498 u8 reserved_at_a0[0x10];
2499 u8 rqt_max_size[0x10];
2501 u8 reserved_at_c0[0x10];
2502 u8 rqt_actual_size[0x10];
2504 u8 reserved_at_e0[0x6a0];
2506 struct mlx5_ifc_rq_num_bits rq_num[0];
2510 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2511 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2515 MLX5_RQC_STATE_RST = 0x0,
2516 MLX5_RQC_STATE_RDY = 0x1,
2517 MLX5_RQC_STATE_ERR = 0x3,
2520 struct mlx5_ifc_rqc_bits {
2522 u8 reserved_at_1[0x1];
2523 u8 scatter_fcs[0x1];
2525 u8 mem_rq_type[0x4];
2527 u8 reserved_at_c[0x1];
2528 u8 flush_in_error_en[0x1];
2529 u8 reserved_at_e[0x12];
2531 u8 reserved_at_20[0x8];
2532 u8 user_index[0x18];
2534 u8 reserved_at_40[0x8];
2537 u8 counter_set_id[0x8];
2538 u8 reserved_at_68[0x18];
2540 u8 reserved_at_80[0x8];
2543 u8 reserved_at_a0[0xe0];
2545 struct mlx5_ifc_wq_bits wq;
2549 MLX5_RMPC_STATE_RDY = 0x1,
2550 MLX5_RMPC_STATE_ERR = 0x3,
2553 struct mlx5_ifc_rmpc_bits {
2554 u8 reserved_at_0[0x8];
2556 u8 reserved_at_c[0x14];
2558 u8 basic_cyclic_rcv_wqe[0x1];
2559 u8 reserved_at_21[0x1f];
2561 u8 reserved_at_40[0x140];
2563 struct mlx5_ifc_wq_bits wq;
2566 struct mlx5_ifc_nic_vport_context_bits {
2567 u8 reserved_at_0[0x5];
2568 u8 min_wqe_inline_mode[0x3];
2569 u8 reserved_at_8[0x15];
2570 u8 disable_mc_local_lb[0x1];
2571 u8 disable_uc_local_lb[0x1];
2574 u8 arm_change_event[0x1];
2575 u8 reserved_at_21[0x1a];
2576 u8 event_on_mtu[0x1];
2577 u8 event_on_promisc_change[0x1];
2578 u8 event_on_vlan_change[0x1];
2579 u8 event_on_mc_address_change[0x1];
2580 u8 event_on_uc_address_change[0x1];
2582 u8 reserved_at_40[0xf0];
2586 u8 system_image_guid[0x40];
2590 u8 reserved_at_200[0x140];
2591 u8 qkey_violation_counter[0x10];
2592 u8 reserved_at_350[0x430];
2596 u8 promisc_all[0x1];
2597 u8 reserved_at_783[0x2];
2598 u8 allowed_list_type[0x3];
2599 u8 reserved_at_788[0xc];
2600 u8 allowed_list_size[0xc];
2602 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2604 u8 reserved_at_7e0[0x20];
2606 u8 current_uc_mac_address[0][0x40];
2610 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2611 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2612 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2613 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
2616 struct mlx5_ifc_mkc_bits {
2617 u8 reserved_at_0[0x1];
2619 u8 reserved_at_2[0xd];
2620 u8 small_fence_on_rdma_read_response[0x1];
2627 u8 access_mode[0x2];
2628 u8 reserved_at_18[0x8];
2633 u8 reserved_at_40[0x20];
2638 u8 reserved_at_63[0x2];
2639 u8 expected_sigerr_count[0x1];
2640 u8 reserved_at_66[0x1];
2644 u8 start_addr[0x40];
2648 u8 bsf_octword_size[0x20];
2650 u8 reserved_at_120[0x80];
2652 u8 translations_octword_size[0x20];
2654 u8 reserved_at_1c0[0x1b];
2655 u8 log_page_size[0x5];
2657 u8 reserved_at_1e0[0x20];
2660 struct mlx5_ifc_pkey_bits {
2661 u8 reserved_at_0[0x10];
2665 struct mlx5_ifc_array128_auto_bits {
2666 u8 array128_auto[16][0x8];
2669 struct mlx5_ifc_hca_vport_context_bits {
2670 u8 field_select[0x20];
2672 u8 reserved_at_20[0xe0];
2674 u8 sm_virt_aware[0x1];
2677 u8 grh_required[0x1];
2678 u8 reserved_at_104[0xc];
2679 u8 port_physical_state[0x4];
2680 u8 vport_state_policy[0x4];
2682 u8 vport_state[0x4];
2684 u8 reserved_at_120[0x20];
2686 u8 system_image_guid[0x40];
2694 u8 cap_mask1_field_select[0x20];
2698 u8 cap_mask2_field_select[0x20];
2700 u8 reserved_at_280[0x80];
2703 u8 reserved_at_310[0x4];
2704 u8 init_type_reply[0x4];
2706 u8 subnet_timeout[0x5];
2710 u8 reserved_at_334[0xc];
2712 u8 qkey_violation_counter[0x10];
2713 u8 pkey_violation_counter[0x10];
2715 u8 reserved_at_360[0xca0];
2718 struct mlx5_ifc_esw_vport_context_bits {
2719 u8 reserved_at_0[0x3];
2720 u8 vport_svlan_strip[0x1];
2721 u8 vport_cvlan_strip[0x1];
2722 u8 vport_svlan_insert[0x1];
2723 u8 vport_cvlan_insert[0x2];
2724 u8 reserved_at_8[0x18];
2726 u8 reserved_at_20[0x20];
2735 u8 reserved_at_60[0x7a0];
2739 MLX5_EQC_STATUS_OK = 0x0,
2740 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2744 MLX5_EQC_ST_ARMED = 0x9,
2745 MLX5_EQC_ST_FIRED = 0xa,
2748 struct mlx5_ifc_eqc_bits {
2750 u8 reserved_at_4[0x9];
2753 u8 reserved_at_f[0x5];
2755 u8 reserved_at_18[0x8];
2757 u8 reserved_at_20[0x20];
2759 u8 reserved_at_40[0x14];
2760 u8 page_offset[0x6];
2761 u8 reserved_at_5a[0x6];
2763 u8 reserved_at_60[0x3];
2764 u8 log_eq_size[0x5];
2767 u8 reserved_at_80[0x20];
2769 u8 reserved_at_a0[0x18];
2772 u8 reserved_at_c0[0x3];
2773 u8 log_page_size[0x5];
2774 u8 reserved_at_c8[0x18];
2776 u8 reserved_at_e0[0x60];
2778 u8 reserved_at_140[0x8];
2779 u8 consumer_counter[0x18];
2781 u8 reserved_at_160[0x8];
2782 u8 producer_counter[0x18];
2784 u8 reserved_at_180[0x80];
2788 MLX5_DCTC_STATE_ACTIVE = 0x0,
2789 MLX5_DCTC_STATE_DRAINING = 0x1,
2790 MLX5_DCTC_STATE_DRAINED = 0x2,
2794 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2795 MLX5_DCTC_CS_RES_NA = 0x1,
2796 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2800 MLX5_DCTC_MTU_256_BYTES = 0x1,
2801 MLX5_DCTC_MTU_512_BYTES = 0x2,
2802 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2803 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2804 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2807 struct mlx5_ifc_dctc_bits {
2808 u8 reserved_at_0[0x4];
2810 u8 reserved_at_8[0x18];
2812 u8 reserved_at_20[0x8];
2813 u8 user_index[0x18];
2815 u8 reserved_at_40[0x8];
2818 u8 counter_set_id[0x8];
2819 u8 atomic_mode[0x4];
2823 u8 atomic_like_write_en[0x1];
2824 u8 latency_sensitive[0x1];
2827 u8 reserved_at_73[0xd];
2829 u8 reserved_at_80[0x8];
2831 u8 reserved_at_90[0x3];
2832 u8 min_rnr_nak[0x5];
2833 u8 reserved_at_98[0x8];
2835 u8 reserved_at_a0[0x8];
2838 u8 reserved_at_c0[0x8];
2842 u8 reserved_at_e8[0x4];
2843 u8 flow_label[0x14];
2845 u8 dc_access_key[0x40];
2847 u8 reserved_at_140[0x5];
2850 u8 pkey_index[0x10];
2852 u8 reserved_at_160[0x8];
2853 u8 my_addr_index[0x8];
2854 u8 reserved_at_170[0x8];
2857 u8 dc_access_key_violation_count[0x20];
2859 u8 reserved_at_1a0[0x14];
2865 u8 reserved_at_1c0[0x40];
2869 MLX5_CQC_STATUS_OK = 0x0,
2870 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2871 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2875 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2876 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2880 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2881 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2882 MLX5_CQC_ST_FIRED = 0xa,
2886 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2887 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2888 MLX5_CQ_PERIOD_NUM_MODES
2891 struct mlx5_ifc_cqc_bits {
2893 u8 reserved_at_4[0x4];
2896 u8 reserved_at_c[0x1];
2897 u8 scqe_break_moderation_en[0x1];
2899 u8 cq_period_mode[0x2];
2900 u8 cqe_comp_en[0x1];
2901 u8 mini_cqe_res_format[0x2];
2903 u8 reserved_at_18[0x8];
2905 u8 reserved_at_20[0x20];
2907 u8 reserved_at_40[0x14];
2908 u8 page_offset[0x6];
2909 u8 reserved_at_5a[0x6];
2911 u8 reserved_at_60[0x3];
2912 u8 log_cq_size[0x5];
2915 u8 reserved_at_80[0x4];
2917 u8 cq_max_count[0x10];
2919 u8 reserved_at_a0[0x18];
2922 u8 reserved_at_c0[0x3];
2923 u8 log_page_size[0x5];
2924 u8 reserved_at_c8[0x18];
2926 u8 reserved_at_e0[0x20];
2928 u8 reserved_at_100[0x8];
2929 u8 last_notified_index[0x18];
2931 u8 reserved_at_120[0x8];
2932 u8 last_solicit_index[0x18];
2934 u8 reserved_at_140[0x8];
2935 u8 consumer_counter[0x18];
2937 u8 reserved_at_160[0x8];
2938 u8 producer_counter[0x18];
2940 u8 reserved_at_180[0x40];
2945 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2946 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2947 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2948 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2949 u8 reserved_at_0[0x800];
2952 struct mlx5_ifc_query_adapter_param_block_bits {
2953 u8 reserved_at_0[0xc0];
2955 u8 reserved_at_c0[0x8];
2956 u8 ieee_vendor_id[0x18];
2958 u8 reserved_at_e0[0x10];
2959 u8 vsd_vendor_id[0x10];
2963 u8 vsd_contd_psid[16][0x8];
2967 MLX5_XRQC_STATE_GOOD = 0x0,
2968 MLX5_XRQC_STATE_ERROR = 0x1,
2972 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2973 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
2977 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2980 struct mlx5_ifc_tag_matching_topology_context_bits {
2981 u8 log_matching_list_sz[0x4];
2982 u8 reserved_at_4[0xc];
2983 u8 append_next_index[0x10];
2985 u8 sw_phase_cnt[0x10];
2986 u8 hw_phase_cnt[0x10];
2988 u8 reserved_at_40[0x40];
2991 struct mlx5_ifc_xrqc_bits {
2994 u8 reserved_at_5[0xf];
2996 u8 reserved_at_18[0x4];
2999 u8 reserved_at_20[0x8];
3000 u8 user_index[0x18];
3002 u8 reserved_at_40[0x8];
3005 u8 reserved_at_60[0xa0];
3007 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3009 u8 reserved_at_180[0x880];
3011 struct mlx5_ifc_wq_bits wq;
3014 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3015 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3016 struct mlx5_ifc_resize_field_select_bits resize_field_select;
3017 u8 reserved_at_0[0x20];
3020 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3021 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3022 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3023 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3024 u8 reserved_at_0[0x20];
3027 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3028 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3029 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3030 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3031 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3032 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3033 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3034 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3035 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3036 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3037 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3038 u8 reserved_at_0[0x7c0];
3041 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3042 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3043 u8 reserved_at_0[0x7c0];
3046 union mlx5_ifc_event_auto_bits {
3047 struct mlx5_ifc_comp_event_bits comp_event;
3048 struct mlx5_ifc_dct_events_bits dct_events;
3049 struct mlx5_ifc_qp_events_bits qp_events;
3050 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3051 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3052 struct mlx5_ifc_cq_error_bits cq_error;
3053 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3054 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3055 struct mlx5_ifc_gpio_event_bits gpio_event;
3056 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3057 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3058 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3059 u8 reserved_at_0[0xe0];
3062 struct mlx5_ifc_health_buffer_bits {
3063 u8 reserved_at_0[0x100];
3065 u8 assert_existptr[0x20];
3067 u8 assert_callra[0x20];
3069 u8 reserved_at_140[0x40];
3071 u8 fw_version[0x20];
3075 u8 reserved_at_1c0[0x20];
3077 u8 irisc_index[0x8];
3082 struct mlx5_ifc_register_loopback_control_bits {
3084 u8 reserved_at_1[0x7];
3086 u8 reserved_at_10[0x10];
3088 u8 reserved_at_20[0x60];
3091 struct mlx5_ifc_vport_tc_element_bits {
3092 u8 traffic_class[0x4];
3093 u8 reserved_at_4[0xc];
3094 u8 vport_number[0x10];
3097 struct mlx5_ifc_vport_element_bits {
3098 u8 reserved_at_0[0x10];
3099 u8 vport_number[0x10];
3103 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3104 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3105 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3108 struct mlx5_ifc_tsar_element_bits {
3109 u8 reserved_at_0[0x8];
3111 u8 reserved_at_10[0x10];
3115 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3116 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3119 struct mlx5_ifc_teardown_hca_out_bits {
3121 u8 reserved_at_8[0x18];
3125 u8 reserved_at_40[0x3f];
3127 u8 force_state[0x1];
3131 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3132 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
3135 struct mlx5_ifc_teardown_hca_in_bits {
3137 u8 reserved_at_10[0x10];
3139 u8 reserved_at_20[0x10];
3142 u8 reserved_at_40[0x10];
3145 u8 reserved_at_60[0x20];
3148 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3150 u8 reserved_at_8[0x18];
3154 u8 reserved_at_40[0x40];
3157 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3159 u8 reserved_at_10[0x10];
3161 u8 reserved_at_20[0x10];
3164 u8 reserved_at_40[0x8];
3167 u8 reserved_at_60[0x20];
3169 u8 opt_param_mask[0x20];
3171 u8 reserved_at_a0[0x20];
3173 struct mlx5_ifc_qpc_bits qpc;
3175 u8 reserved_at_800[0x80];
3178 struct mlx5_ifc_sqd2rts_qp_out_bits {
3180 u8 reserved_at_8[0x18];
3184 u8 reserved_at_40[0x40];
3187 struct mlx5_ifc_sqd2rts_qp_in_bits {
3189 u8 reserved_at_10[0x10];
3191 u8 reserved_at_20[0x10];
3194 u8 reserved_at_40[0x8];
3197 u8 reserved_at_60[0x20];
3199 u8 opt_param_mask[0x20];
3201 u8 reserved_at_a0[0x20];
3203 struct mlx5_ifc_qpc_bits qpc;
3205 u8 reserved_at_800[0x80];
3208 struct mlx5_ifc_set_roce_address_out_bits {
3210 u8 reserved_at_8[0x18];
3214 u8 reserved_at_40[0x40];
3217 struct mlx5_ifc_set_roce_address_in_bits {
3219 u8 reserved_at_10[0x10];
3221 u8 reserved_at_20[0x10];
3224 u8 roce_address_index[0x10];
3225 u8 reserved_at_50[0x10];
3227 u8 reserved_at_60[0x20];
3229 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3232 struct mlx5_ifc_set_mad_demux_out_bits {
3234 u8 reserved_at_8[0x18];
3238 u8 reserved_at_40[0x40];
3242 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3243 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3246 struct mlx5_ifc_set_mad_demux_in_bits {
3248 u8 reserved_at_10[0x10];
3250 u8 reserved_at_20[0x10];
3253 u8 reserved_at_40[0x20];
3255 u8 reserved_at_60[0x6];
3257 u8 reserved_at_68[0x18];
3260 struct mlx5_ifc_set_l2_table_entry_out_bits {
3262 u8 reserved_at_8[0x18];
3266 u8 reserved_at_40[0x40];
3269 struct mlx5_ifc_set_l2_table_entry_in_bits {
3271 u8 reserved_at_10[0x10];
3273 u8 reserved_at_20[0x10];
3276 u8 reserved_at_40[0x60];
3278 u8 reserved_at_a0[0x8];
3279 u8 table_index[0x18];
3281 u8 reserved_at_c0[0x20];
3283 u8 reserved_at_e0[0x13];
3287 struct mlx5_ifc_mac_address_layout_bits mac_address;
3289 u8 reserved_at_140[0xc0];
3292 struct mlx5_ifc_set_issi_out_bits {
3294 u8 reserved_at_8[0x18];
3298 u8 reserved_at_40[0x40];
3301 struct mlx5_ifc_set_issi_in_bits {
3303 u8 reserved_at_10[0x10];
3305 u8 reserved_at_20[0x10];
3308 u8 reserved_at_40[0x10];
3309 u8 current_issi[0x10];
3311 u8 reserved_at_60[0x20];
3314 struct mlx5_ifc_set_hca_cap_out_bits {
3316 u8 reserved_at_8[0x18];
3320 u8 reserved_at_40[0x40];
3323 struct mlx5_ifc_set_hca_cap_in_bits {
3325 u8 reserved_at_10[0x10];
3327 u8 reserved_at_20[0x10];
3330 u8 reserved_at_40[0x40];
3332 union mlx5_ifc_hca_cap_union_bits capability;
3336 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3337 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3338 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3339 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3342 struct mlx5_ifc_set_fte_out_bits {
3344 u8 reserved_at_8[0x18];
3348 u8 reserved_at_40[0x40];
3351 struct mlx5_ifc_set_fte_in_bits {
3353 u8 reserved_at_10[0x10];
3355 u8 reserved_at_20[0x10];
3358 u8 other_vport[0x1];
3359 u8 reserved_at_41[0xf];
3360 u8 vport_number[0x10];
3362 u8 reserved_at_60[0x20];
3365 u8 reserved_at_88[0x18];
3367 u8 reserved_at_a0[0x8];
3370 u8 reserved_at_c0[0x18];
3371 u8 modify_enable_mask[0x8];
3373 u8 reserved_at_e0[0x20];
3375 u8 flow_index[0x20];
3377 u8 reserved_at_120[0xe0];
3379 struct mlx5_ifc_flow_context_bits flow_context;
3382 struct mlx5_ifc_rts2rts_qp_out_bits {
3384 u8 reserved_at_8[0x18];
3388 u8 reserved_at_40[0x40];
3391 struct mlx5_ifc_rts2rts_qp_in_bits {
3393 u8 reserved_at_10[0x10];
3395 u8 reserved_at_20[0x10];
3398 u8 reserved_at_40[0x8];
3401 u8 reserved_at_60[0x20];
3403 u8 opt_param_mask[0x20];
3405 u8 reserved_at_a0[0x20];
3407 struct mlx5_ifc_qpc_bits qpc;
3409 u8 reserved_at_800[0x80];
3412 struct mlx5_ifc_rtr2rts_qp_out_bits {
3414 u8 reserved_at_8[0x18];
3418 u8 reserved_at_40[0x40];
3421 struct mlx5_ifc_rtr2rts_qp_in_bits {
3423 u8 reserved_at_10[0x10];
3425 u8 reserved_at_20[0x10];
3428 u8 reserved_at_40[0x8];
3431 u8 reserved_at_60[0x20];
3433 u8 opt_param_mask[0x20];
3435 u8 reserved_at_a0[0x20];
3437 struct mlx5_ifc_qpc_bits qpc;
3439 u8 reserved_at_800[0x80];
3442 struct mlx5_ifc_rst2init_qp_out_bits {
3444 u8 reserved_at_8[0x18];
3448 u8 reserved_at_40[0x40];
3451 struct mlx5_ifc_rst2init_qp_in_bits {
3453 u8 reserved_at_10[0x10];
3455 u8 reserved_at_20[0x10];
3458 u8 reserved_at_40[0x8];
3461 u8 reserved_at_60[0x20];
3463 u8 opt_param_mask[0x20];
3465 u8 reserved_at_a0[0x20];
3467 struct mlx5_ifc_qpc_bits qpc;
3469 u8 reserved_at_800[0x80];
3472 struct mlx5_ifc_query_xrq_out_bits {
3474 u8 reserved_at_8[0x18];
3478 u8 reserved_at_40[0x40];
3480 struct mlx5_ifc_xrqc_bits xrq_context;
3483 struct mlx5_ifc_query_xrq_in_bits {
3485 u8 reserved_at_10[0x10];
3487 u8 reserved_at_20[0x10];
3490 u8 reserved_at_40[0x8];
3493 u8 reserved_at_60[0x20];
3496 struct mlx5_ifc_query_xrc_srq_out_bits {
3498 u8 reserved_at_8[0x18];
3502 u8 reserved_at_40[0x40];
3504 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3506 u8 reserved_at_280[0x600];
3511 struct mlx5_ifc_query_xrc_srq_in_bits {
3513 u8 reserved_at_10[0x10];
3515 u8 reserved_at_20[0x10];
3518 u8 reserved_at_40[0x8];
3521 u8 reserved_at_60[0x20];
3525 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3526 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3529 struct mlx5_ifc_query_vport_state_out_bits {
3531 u8 reserved_at_8[0x18];
3535 u8 reserved_at_40[0x20];
3537 u8 reserved_at_60[0x18];
3538 u8 admin_state[0x4];
3543 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
3544 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
3547 struct mlx5_ifc_query_vport_state_in_bits {
3549 u8 reserved_at_10[0x10];
3551 u8 reserved_at_20[0x10];
3554 u8 other_vport[0x1];
3555 u8 reserved_at_41[0xf];
3556 u8 vport_number[0x10];
3558 u8 reserved_at_60[0x20];
3561 struct mlx5_ifc_query_vport_counter_out_bits {
3563 u8 reserved_at_8[0x18];
3567 u8 reserved_at_40[0x40];
3569 struct mlx5_ifc_traffic_counter_bits received_errors;
3571 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3573 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3575 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3577 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3579 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3581 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3583 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3585 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3587 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3589 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3591 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3593 u8 reserved_at_680[0xa00];
3597 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3600 struct mlx5_ifc_query_vport_counter_in_bits {
3602 u8 reserved_at_10[0x10];
3604 u8 reserved_at_20[0x10];
3607 u8 other_vport[0x1];
3608 u8 reserved_at_41[0xb];
3610 u8 vport_number[0x10];
3612 u8 reserved_at_60[0x60];
3615 u8 reserved_at_c1[0x1f];
3617 u8 reserved_at_e0[0x20];
3620 struct mlx5_ifc_query_tis_out_bits {
3622 u8 reserved_at_8[0x18];
3626 u8 reserved_at_40[0x40];
3628 struct mlx5_ifc_tisc_bits tis_context;
3631 struct mlx5_ifc_query_tis_in_bits {
3633 u8 reserved_at_10[0x10];
3635 u8 reserved_at_20[0x10];
3638 u8 reserved_at_40[0x8];
3641 u8 reserved_at_60[0x20];
3644 struct mlx5_ifc_query_tir_out_bits {
3646 u8 reserved_at_8[0x18];
3650 u8 reserved_at_40[0xc0];
3652 struct mlx5_ifc_tirc_bits tir_context;
3655 struct mlx5_ifc_query_tir_in_bits {
3657 u8 reserved_at_10[0x10];
3659 u8 reserved_at_20[0x10];
3662 u8 reserved_at_40[0x8];
3665 u8 reserved_at_60[0x20];
3668 struct mlx5_ifc_query_srq_out_bits {
3670 u8 reserved_at_8[0x18];
3674 u8 reserved_at_40[0x40];
3676 struct mlx5_ifc_srqc_bits srq_context_entry;
3678 u8 reserved_at_280[0x600];
3683 struct mlx5_ifc_query_srq_in_bits {
3685 u8 reserved_at_10[0x10];
3687 u8 reserved_at_20[0x10];
3690 u8 reserved_at_40[0x8];
3693 u8 reserved_at_60[0x20];
3696 struct mlx5_ifc_query_sq_out_bits {
3698 u8 reserved_at_8[0x18];
3702 u8 reserved_at_40[0xc0];
3704 struct mlx5_ifc_sqc_bits sq_context;
3707 struct mlx5_ifc_query_sq_in_bits {
3709 u8 reserved_at_10[0x10];
3711 u8 reserved_at_20[0x10];
3714 u8 reserved_at_40[0x8];
3717 u8 reserved_at_60[0x20];
3720 struct mlx5_ifc_query_special_contexts_out_bits {
3722 u8 reserved_at_8[0x18];
3726 u8 dump_fill_mkey[0x20];
3732 u8 reserved_at_a0[0x60];
3735 struct mlx5_ifc_query_special_contexts_in_bits {
3737 u8 reserved_at_10[0x10];
3739 u8 reserved_at_20[0x10];
3742 u8 reserved_at_40[0x40];
3745 struct mlx5_ifc_query_scheduling_element_out_bits {
3747 u8 reserved_at_10[0x10];
3749 u8 reserved_at_20[0x10];
3752 u8 reserved_at_40[0xc0];
3754 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3756 u8 reserved_at_300[0x100];
3760 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3763 struct mlx5_ifc_query_scheduling_element_in_bits {
3765 u8 reserved_at_10[0x10];
3767 u8 reserved_at_20[0x10];
3770 u8 scheduling_hierarchy[0x8];
3771 u8 reserved_at_48[0x18];
3773 u8 scheduling_element_id[0x20];
3775 u8 reserved_at_80[0x180];
3778 struct mlx5_ifc_query_rqt_out_bits {
3780 u8 reserved_at_8[0x18];
3784 u8 reserved_at_40[0xc0];
3786 struct mlx5_ifc_rqtc_bits rqt_context;
3789 struct mlx5_ifc_query_rqt_in_bits {
3791 u8 reserved_at_10[0x10];
3793 u8 reserved_at_20[0x10];
3796 u8 reserved_at_40[0x8];
3799 u8 reserved_at_60[0x20];
3802 struct mlx5_ifc_query_rq_out_bits {
3804 u8 reserved_at_8[0x18];
3808 u8 reserved_at_40[0xc0];
3810 struct mlx5_ifc_rqc_bits rq_context;
3813 struct mlx5_ifc_query_rq_in_bits {
3815 u8 reserved_at_10[0x10];
3817 u8 reserved_at_20[0x10];
3820 u8 reserved_at_40[0x8];
3823 u8 reserved_at_60[0x20];
3826 struct mlx5_ifc_query_roce_address_out_bits {
3828 u8 reserved_at_8[0x18];
3832 u8 reserved_at_40[0x40];
3834 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3837 struct mlx5_ifc_query_roce_address_in_bits {
3839 u8 reserved_at_10[0x10];
3841 u8 reserved_at_20[0x10];
3844 u8 roce_address_index[0x10];
3845 u8 reserved_at_50[0x10];
3847 u8 reserved_at_60[0x20];
3850 struct mlx5_ifc_query_rmp_out_bits {
3852 u8 reserved_at_8[0x18];
3856 u8 reserved_at_40[0xc0];
3858 struct mlx5_ifc_rmpc_bits rmp_context;
3861 struct mlx5_ifc_query_rmp_in_bits {
3863 u8 reserved_at_10[0x10];
3865 u8 reserved_at_20[0x10];
3868 u8 reserved_at_40[0x8];
3871 u8 reserved_at_60[0x20];
3874 struct mlx5_ifc_query_qp_out_bits {
3876 u8 reserved_at_8[0x18];
3880 u8 reserved_at_40[0x40];
3882 u8 opt_param_mask[0x20];
3884 u8 reserved_at_a0[0x20];
3886 struct mlx5_ifc_qpc_bits qpc;
3888 u8 reserved_at_800[0x80];
3893 struct mlx5_ifc_query_qp_in_bits {
3895 u8 reserved_at_10[0x10];
3897 u8 reserved_at_20[0x10];
3900 u8 reserved_at_40[0x8];
3903 u8 reserved_at_60[0x20];
3906 struct mlx5_ifc_query_q_counter_out_bits {
3908 u8 reserved_at_8[0x18];
3912 u8 reserved_at_40[0x40];
3914 u8 rx_write_requests[0x20];
3916 u8 reserved_at_a0[0x20];
3918 u8 rx_read_requests[0x20];
3920 u8 reserved_at_e0[0x20];
3922 u8 rx_atomic_requests[0x20];
3924 u8 reserved_at_120[0x20];
3926 u8 rx_dct_connect[0x20];
3928 u8 reserved_at_160[0x20];
3930 u8 out_of_buffer[0x20];
3932 u8 reserved_at_1a0[0x20];
3934 u8 out_of_sequence[0x20];
3936 u8 reserved_at_1e0[0x20];
3938 u8 duplicate_request[0x20];
3940 u8 reserved_at_220[0x20];
3942 u8 rnr_nak_retry_err[0x20];
3944 u8 reserved_at_260[0x20];
3946 u8 packet_seq_err[0x20];
3948 u8 reserved_at_2a0[0x20];
3950 u8 implied_nak_seq_err[0x20];
3952 u8 reserved_at_2e0[0x20];
3954 u8 local_ack_timeout_err[0x20];
3956 u8 reserved_at_320[0x4e0];
3959 struct mlx5_ifc_query_q_counter_in_bits {
3961 u8 reserved_at_10[0x10];
3963 u8 reserved_at_20[0x10];
3966 u8 reserved_at_40[0x80];
3969 u8 reserved_at_c1[0x1f];
3971 u8 reserved_at_e0[0x18];
3972 u8 counter_set_id[0x8];
3975 struct mlx5_ifc_query_pages_out_bits {
3977 u8 reserved_at_8[0x18];
3981 u8 reserved_at_40[0x10];
3982 u8 function_id[0x10];
3988 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3989 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3990 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3993 struct mlx5_ifc_query_pages_in_bits {
3995 u8 reserved_at_10[0x10];
3997 u8 reserved_at_20[0x10];
4000 u8 reserved_at_40[0x10];
4001 u8 function_id[0x10];
4003 u8 reserved_at_60[0x20];
4006 struct mlx5_ifc_query_nic_vport_context_out_bits {
4008 u8 reserved_at_8[0x18];
4012 u8 reserved_at_40[0x40];
4014 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4017 struct mlx5_ifc_query_nic_vport_context_in_bits {
4019 u8 reserved_at_10[0x10];
4021 u8 reserved_at_20[0x10];
4024 u8 other_vport[0x1];
4025 u8 reserved_at_41[0xf];
4026 u8 vport_number[0x10];
4028 u8 reserved_at_60[0x5];
4029 u8 allowed_list_type[0x3];
4030 u8 reserved_at_68[0x18];
4033 struct mlx5_ifc_query_mkey_out_bits {
4035 u8 reserved_at_8[0x18];
4039 u8 reserved_at_40[0x40];
4041 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4043 u8 reserved_at_280[0x600];
4045 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4047 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4050 struct mlx5_ifc_query_mkey_in_bits {
4052 u8 reserved_at_10[0x10];
4054 u8 reserved_at_20[0x10];
4057 u8 reserved_at_40[0x8];
4058 u8 mkey_index[0x18];
4061 u8 reserved_at_61[0x1f];
4064 struct mlx5_ifc_query_mad_demux_out_bits {
4066 u8 reserved_at_8[0x18];
4070 u8 reserved_at_40[0x40];
4072 u8 mad_dumux_parameters_block[0x20];
4075 struct mlx5_ifc_query_mad_demux_in_bits {
4077 u8 reserved_at_10[0x10];
4079 u8 reserved_at_20[0x10];
4082 u8 reserved_at_40[0x40];
4085 struct mlx5_ifc_query_l2_table_entry_out_bits {
4087 u8 reserved_at_8[0x18];
4091 u8 reserved_at_40[0xa0];
4093 u8 reserved_at_e0[0x13];
4097 struct mlx5_ifc_mac_address_layout_bits mac_address;
4099 u8 reserved_at_140[0xc0];
4102 struct mlx5_ifc_query_l2_table_entry_in_bits {
4104 u8 reserved_at_10[0x10];
4106 u8 reserved_at_20[0x10];
4109 u8 reserved_at_40[0x60];
4111 u8 reserved_at_a0[0x8];
4112 u8 table_index[0x18];
4114 u8 reserved_at_c0[0x140];
4117 struct mlx5_ifc_query_issi_out_bits {
4119 u8 reserved_at_8[0x18];
4123 u8 reserved_at_40[0x10];
4124 u8 current_issi[0x10];
4126 u8 reserved_at_60[0xa0];
4128 u8 reserved_at_100[76][0x8];
4129 u8 supported_issi_dw0[0x20];
4132 struct mlx5_ifc_query_issi_in_bits {
4134 u8 reserved_at_10[0x10];
4136 u8 reserved_at_20[0x10];
4139 u8 reserved_at_40[0x40];
4142 struct mlx5_ifc_set_driver_version_out_bits {
4144 u8 reserved_0[0x18];
4147 u8 reserved_1[0x40];
4150 struct mlx5_ifc_set_driver_version_in_bits {
4152 u8 reserved_0[0x10];
4154 u8 reserved_1[0x10];
4157 u8 reserved_2[0x40];
4158 u8 driver_version[64][0x8];
4161 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4163 u8 reserved_at_8[0x18];
4167 u8 reserved_at_40[0x40];
4169 struct mlx5_ifc_pkey_bits pkey[0];
4172 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4174 u8 reserved_at_10[0x10];
4176 u8 reserved_at_20[0x10];
4179 u8 other_vport[0x1];
4180 u8 reserved_at_41[0xb];
4182 u8 vport_number[0x10];
4184 u8 reserved_at_60[0x10];
4185 u8 pkey_index[0x10];
4189 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4190 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4191 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4194 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4196 u8 reserved_at_8[0x18];
4200 u8 reserved_at_40[0x20];
4203 u8 reserved_at_70[0x10];
4205 struct mlx5_ifc_array128_auto_bits gid[0];
4208 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4210 u8 reserved_at_10[0x10];
4212 u8 reserved_at_20[0x10];
4215 u8 other_vport[0x1];
4216 u8 reserved_at_41[0xb];
4218 u8 vport_number[0x10];
4220 u8 reserved_at_60[0x10];
4224 struct mlx5_ifc_query_hca_vport_context_out_bits {
4226 u8 reserved_at_8[0x18];
4230 u8 reserved_at_40[0x40];
4232 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4235 struct mlx5_ifc_query_hca_vport_context_in_bits {
4237 u8 reserved_at_10[0x10];
4239 u8 reserved_at_20[0x10];
4242 u8 other_vport[0x1];
4243 u8 reserved_at_41[0xb];
4245 u8 vport_number[0x10];
4247 u8 reserved_at_60[0x20];
4250 struct mlx5_ifc_query_hca_cap_out_bits {
4252 u8 reserved_at_8[0x18];
4256 u8 reserved_at_40[0x40];
4258 union mlx5_ifc_hca_cap_union_bits capability;
4261 struct mlx5_ifc_query_hca_cap_in_bits {
4263 u8 reserved_at_10[0x10];
4265 u8 reserved_at_20[0x10];
4268 u8 reserved_at_40[0x40];
4271 struct mlx5_ifc_query_flow_table_out_bits {
4273 u8 reserved_at_8[0x18];
4277 u8 reserved_at_40[0x80];
4279 u8 reserved_at_c0[0x8];
4281 u8 reserved_at_d0[0x8];
4284 u8 reserved_at_e0[0x120];
4287 struct mlx5_ifc_query_flow_table_in_bits {
4289 u8 reserved_at_10[0x10];
4291 u8 reserved_at_20[0x10];
4294 u8 reserved_at_40[0x40];
4297 u8 reserved_at_88[0x18];
4299 u8 reserved_at_a0[0x8];
4302 u8 reserved_at_c0[0x140];
4305 struct mlx5_ifc_query_fte_out_bits {
4307 u8 reserved_at_8[0x18];
4311 u8 reserved_at_40[0x1c0];
4313 struct mlx5_ifc_flow_context_bits flow_context;
4316 struct mlx5_ifc_query_fte_in_bits {
4318 u8 reserved_at_10[0x10];
4320 u8 reserved_at_20[0x10];
4323 u8 reserved_at_40[0x40];
4326 u8 reserved_at_88[0x18];
4328 u8 reserved_at_a0[0x8];
4331 u8 reserved_at_c0[0x40];
4333 u8 flow_index[0x20];
4335 u8 reserved_at_120[0xe0];
4339 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4340 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4341 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4344 struct mlx5_ifc_query_flow_group_out_bits {
4346 u8 reserved_at_8[0x18];
4350 u8 reserved_at_40[0xa0];
4352 u8 start_flow_index[0x20];
4354 u8 reserved_at_100[0x20];
4356 u8 end_flow_index[0x20];
4358 u8 reserved_at_140[0xa0];
4360 u8 reserved_at_1e0[0x18];
4361 u8 match_criteria_enable[0x8];
4363 struct mlx5_ifc_fte_match_param_bits match_criteria;
4365 u8 reserved_at_1200[0xe00];
4368 struct mlx5_ifc_query_flow_group_in_bits {
4370 u8 reserved_at_10[0x10];
4372 u8 reserved_at_20[0x10];
4375 u8 reserved_at_40[0x40];
4378 u8 reserved_at_88[0x18];
4380 u8 reserved_at_a0[0x8];
4385 u8 reserved_at_e0[0x120];
4388 struct mlx5_ifc_query_flow_counter_out_bits {
4390 u8 reserved_at_8[0x18];
4394 u8 reserved_at_40[0x40];
4396 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4399 struct mlx5_ifc_query_flow_counter_in_bits {
4401 u8 reserved_at_10[0x10];
4403 u8 reserved_at_20[0x10];
4406 u8 reserved_at_40[0x80];
4409 u8 reserved_at_c1[0xf];
4410 u8 num_of_counters[0x10];
4412 u8 reserved_at_e0[0x10];
4413 u8 flow_counter_id[0x10];
4416 struct mlx5_ifc_query_esw_vport_context_out_bits {
4418 u8 reserved_at_8[0x18];
4422 u8 reserved_at_40[0x40];
4424 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4427 struct mlx5_ifc_query_esw_vport_context_in_bits {
4429 u8 reserved_at_10[0x10];
4431 u8 reserved_at_20[0x10];
4434 u8 other_vport[0x1];
4435 u8 reserved_at_41[0xf];
4436 u8 vport_number[0x10];
4438 u8 reserved_at_60[0x20];
4441 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4443 u8 reserved_at_8[0x18];
4447 u8 reserved_at_40[0x40];
4450 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4451 u8 reserved_at_0[0x1c];
4452 u8 vport_cvlan_insert[0x1];
4453 u8 vport_svlan_insert[0x1];
4454 u8 vport_cvlan_strip[0x1];
4455 u8 vport_svlan_strip[0x1];
4458 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4460 u8 reserved_at_10[0x10];
4462 u8 reserved_at_20[0x10];
4465 u8 other_vport[0x1];
4466 u8 reserved_at_41[0xf];
4467 u8 vport_number[0x10];
4469 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4471 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4474 struct mlx5_ifc_query_eq_out_bits {
4476 u8 reserved_at_8[0x18];
4480 u8 reserved_at_40[0x40];
4482 struct mlx5_ifc_eqc_bits eq_context_entry;
4484 u8 reserved_at_280[0x40];
4486 u8 event_bitmask[0x40];
4488 u8 reserved_at_300[0x580];
4493 struct mlx5_ifc_query_eq_in_bits {
4495 u8 reserved_at_10[0x10];
4497 u8 reserved_at_20[0x10];
4500 u8 reserved_at_40[0x18];
4503 u8 reserved_at_60[0x20];
4506 struct mlx5_ifc_encap_header_in_bits {
4507 u8 reserved_at_0[0x5];
4508 u8 header_type[0x3];
4509 u8 reserved_at_8[0xe];
4510 u8 encap_header_size[0xa];
4512 u8 reserved_at_20[0x10];
4513 u8 encap_header[2][0x8];
4515 u8 more_encap_header[0][0x8];
4518 struct mlx5_ifc_query_encap_header_out_bits {
4520 u8 reserved_at_8[0x18];
4524 u8 reserved_at_40[0xa0];
4526 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4529 struct mlx5_ifc_query_encap_header_in_bits {
4531 u8 reserved_at_10[0x10];
4533 u8 reserved_at_20[0x10];
4538 u8 reserved_at_60[0xa0];
4541 struct mlx5_ifc_alloc_encap_header_out_bits {
4543 u8 reserved_at_8[0x18];
4549 u8 reserved_at_60[0x20];
4552 struct mlx5_ifc_alloc_encap_header_in_bits {
4554 u8 reserved_at_10[0x10];
4556 u8 reserved_at_20[0x10];
4559 u8 reserved_at_40[0xa0];
4561 struct mlx5_ifc_encap_header_in_bits encap_header;
4564 struct mlx5_ifc_dealloc_encap_header_out_bits {
4566 u8 reserved_at_8[0x18];
4570 u8 reserved_at_40[0x40];
4573 struct mlx5_ifc_dealloc_encap_header_in_bits {
4575 u8 reserved_at_10[0x10];
4577 u8 reserved_20[0x10];
4582 u8 reserved_60[0x20];
4585 struct mlx5_ifc_set_action_in_bits {
4586 u8 action_type[0x4];
4588 u8 reserved_at_10[0x3];
4590 u8 reserved_at_18[0x3];
4596 struct mlx5_ifc_add_action_in_bits {
4597 u8 action_type[0x4];
4599 u8 reserved_at_10[0x10];
4604 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4605 struct mlx5_ifc_set_action_in_bits set_action_in;
4606 struct mlx5_ifc_add_action_in_bits add_action_in;
4607 u8 reserved_at_0[0x40];
4611 MLX5_ACTION_TYPE_SET = 0x1,
4612 MLX5_ACTION_TYPE_ADD = 0x2,
4616 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
4617 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
4618 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
4619 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
4620 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
4621 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
4622 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
4623 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
4624 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
4625 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
4626 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
4627 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
4628 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
4629 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
4630 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
4631 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
4632 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
4633 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
4634 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
4635 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4636 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4637 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
4638 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4641 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4643 u8 reserved_at_8[0x18];
4647 u8 modify_header_id[0x20];
4649 u8 reserved_at_60[0x20];
4652 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4654 u8 reserved_at_10[0x10];
4656 u8 reserved_at_20[0x10];
4659 u8 reserved_at_40[0x20];
4662 u8 reserved_at_68[0x10];
4663 u8 num_of_actions[0x8];
4665 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4668 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4670 u8 reserved_at_8[0x18];
4674 u8 reserved_at_40[0x40];
4677 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4679 u8 reserved_at_10[0x10];
4681 u8 reserved_at_20[0x10];
4684 u8 modify_header_id[0x20];
4686 u8 reserved_at_60[0x20];
4689 struct mlx5_ifc_query_dct_out_bits {
4691 u8 reserved_at_8[0x18];
4695 u8 reserved_at_40[0x40];
4697 struct mlx5_ifc_dctc_bits dct_context_entry;
4699 u8 reserved_at_280[0x180];
4702 struct mlx5_ifc_query_dct_in_bits {
4704 u8 reserved_at_10[0x10];
4706 u8 reserved_at_20[0x10];
4709 u8 reserved_at_40[0x8];
4712 u8 reserved_at_60[0x20];
4715 struct mlx5_ifc_query_cq_out_bits {
4717 u8 reserved_at_8[0x18];
4721 u8 reserved_at_40[0x40];
4723 struct mlx5_ifc_cqc_bits cq_context;
4725 u8 reserved_at_280[0x600];
4730 struct mlx5_ifc_query_cq_in_bits {
4732 u8 reserved_at_10[0x10];
4734 u8 reserved_at_20[0x10];
4737 u8 reserved_at_40[0x8];
4740 u8 reserved_at_60[0x20];
4743 struct mlx5_ifc_query_cong_status_out_bits {
4745 u8 reserved_at_8[0x18];
4749 u8 reserved_at_40[0x20];
4753 u8 reserved_at_62[0x1e];
4756 struct mlx5_ifc_query_cong_status_in_bits {
4758 u8 reserved_at_10[0x10];
4760 u8 reserved_at_20[0x10];
4763 u8 reserved_at_40[0x18];
4765 u8 cong_protocol[0x4];
4767 u8 reserved_at_60[0x20];
4770 struct mlx5_ifc_query_cong_statistics_out_bits {
4772 u8 reserved_at_8[0x18];
4776 u8 reserved_at_40[0x40];
4778 u8 rp_cur_flows[0x20];
4782 u8 rp_cnp_ignored_high[0x20];
4784 u8 rp_cnp_ignored_low[0x20];
4786 u8 rp_cnp_handled_high[0x20];
4788 u8 rp_cnp_handled_low[0x20];
4790 u8 reserved_at_140[0x100];
4792 u8 time_stamp_high[0x20];
4794 u8 time_stamp_low[0x20];
4796 u8 accumulators_period[0x20];
4798 u8 np_ecn_marked_roce_packets_high[0x20];
4800 u8 np_ecn_marked_roce_packets_low[0x20];
4802 u8 np_cnp_sent_high[0x20];
4804 u8 np_cnp_sent_low[0x20];
4806 u8 reserved_at_320[0x560];
4809 struct mlx5_ifc_query_cong_statistics_in_bits {
4811 u8 reserved_at_10[0x10];
4813 u8 reserved_at_20[0x10];
4817 u8 reserved_at_41[0x1f];
4819 u8 reserved_at_60[0x20];
4822 struct mlx5_ifc_query_cong_params_out_bits {
4824 u8 reserved_at_8[0x18];
4828 u8 reserved_at_40[0x40];
4830 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4833 struct mlx5_ifc_query_cong_params_in_bits {
4835 u8 reserved_at_10[0x10];
4837 u8 reserved_at_20[0x10];
4840 u8 reserved_at_40[0x1c];
4841 u8 cong_protocol[0x4];
4843 u8 reserved_at_60[0x20];
4846 struct mlx5_ifc_query_adapter_out_bits {
4848 u8 reserved_at_8[0x18];
4852 u8 reserved_at_40[0x40];
4854 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4857 struct mlx5_ifc_query_adapter_in_bits {
4859 u8 reserved_at_10[0x10];
4861 u8 reserved_at_20[0x10];
4864 u8 reserved_at_40[0x40];
4867 struct mlx5_ifc_qp_2rst_out_bits {
4869 u8 reserved_at_8[0x18];
4873 u8 reserved_at_40[0x40];
4876 struct mlx5_ifc_qp_2rst_in_bits {
4878 u8 reserved_at_10[0x10];
4880 u8 reserved_at_20[0x10];
4883 u8 reserved_at_40[0x8];
4886 u8 reserved_at_60[0x20];
4889 struct mlx5_ifc_qp_2err_out_bits {
4891 u8 reserved_at_8[0x18];
4895 u8 reserved_at_40[0x40];
4898 struct mlx5_ifc_qp_2err_in_bits {
4900 u8 reserved_at_10[0x10];
4902 u8 reserved_at_20[0x10];
4905 u8 reserved_at_40[0x8];
4908 u8 reserved_at_60[0x20];
4911 struct mlx5_ifc_page_fault_resume_out_bits {
4913 u8 reserved_at_8[0x18];
4917 u8 reserved_at_40[0x40];
4920 struct mlx5_ifc_page_fault_resume_in_bits {
4922 u8 reserved_at_10[0x10];
4924 u8 reserved_at_20[0x10];
4928 u8 reserved_at_41[0x4];
4929 u8 page_fault_type[0x3];
4932 u8 reserved_at_60[0x8];
4936 struct mlx5_ifc_nop_out_bits {
4938 u8 reserved_at_8[0x18];
4942 u8 reserved_at_40[0x40];
4945 struct mlx5_ifc_nop_in_bits {
4947 u8 reserved_at_10[0x10];
4949 u8 reserved_at_20[0x10];
4952 u8 reserved_at_40[0x40];
4955 struct mlx5_ifc_modify_vport_state_out_bits {
4957 u8 reserved_at_8[0x18];
4961 u8 reserved_at_40[0x40];
4964 struct mlx5_ifc_modify_vport_state_in_bits {
4966 u8 reserved_at_10[0x10];
4968 u8 reserved_at_20[0x10];
4971 u8 other_vport[0x1];
4972 u8 reserved_at_41[0xf];
4973 u8 vport_number[0x10];
4975 u8 reserved_at_60[0x18];
4976 u8 admin_state[0x4];
4977 u8 reserved_at_7c[0x4];
4980 struct mlx5_ifc_modify_tis_out_bits {
4982 u8 reserved_at_8[0x18];
4986 u8 reserved_at_40[0x40];
4989 struct mlx5_ifc_modify_tis_bitmask_bits {
4990 u8 reserved_at_0[0x20];
4992 u8 reserved_at_20[0x1d];
4993 u8 lag_tx_port_affinity[0x1];
4994 u8 strict_lag_tx_port_affinity[0x1];
4998 struct mlx5_ifc_modify_tis_in_bits {
5000 u8 reserved_at_10[0x10];
5002 u8 reserved_at_20[0x10];
5005 u8 reserved_at_40[0x8];
5008 u8 reserved_at_60[0x20];
5010 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5012 u8 reserved_at_c0[0x40];
5014 struct mlx5_ifc_tisc_bits ctx;
5017 struct mlx5_ifc_modify_tir_bitmask_bits {
5018 u8 reserved_at_0[0x20];
5020 u8 reserved_at_20[0x1b];
5022 u8 reserved_at_3c[0x1];
5024 u8 reserved_at_3e[0x1];
5028 struct mlx5_ifc_modify_tir_out_bits {
5030 u8 reserved_at_8[0x18];
5034 u8 reserved_at_40[0x40];
5037 struct mlx5_ifc_modify_tir_in_bits {
5039 u8 reserved_at_10[0x10];
5041 u8 reserved_at_20[0x10];
5044 u8 reserved_at_40[0x8];
5047 u8 reserved_at_60[0x20];
5049 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5051 u8 reserved_at_c0[0x40];
5053 struct mlx5_ifc_tirc_bits ctx;
5056 struct mlx5_ifc_modify_sq_out_bits {
5058 u8 reserved_at_8[0x18];
5062 u8 reserved_at_40[0x40];
5065 struct mlx5_ifc_modify_sq_in_bits {
5067 u8 reserved_at_10[0x10];
5069 u8 reserved_at_20[0x10];
5073 u8 reserved_at_44[0x4];
5076 u8 reserved_at_60[0x20];
5078 u8 modify_bitmask[0x40];
5080 u8 reserved_at_c0[0x40];
5082 struct mlx5_ifc_sqc_bits ctx;
5085 struct mlx5_ifc_modify_scheduling_element_out_bits {
5087 u8 reserved_at_8[0x18];
5091 u8 reserved_at_40[0x1c0];
5095 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5096 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5099 struct mlx5_ifc_modify_scheduling_element_in_bits {
5101 u8 reserved_at_10[0x10];
5103 u8 reserved_at_20[0x10];
5106 u8 scheduling_hierarchy[0x8];
5107 u8 reserved_at_48[0x18];
5109 u8 scheduling_element_id[0x20];
5111 u8 reserved_at_80[0x20];
5113 u8 modify_bitmask[0x20];
5115 u8 reserved_at_c0[0x40];
5117 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5119 u8 reserved_at_300[0x100];
5122 struct mlx5_ifc_modify_rqt_out_bits {
5124 u8 reserved_at_8[0x18];
5128 u8 reserved_at_40[0x40];
5131 struct mlx5_ifc_rqt_bitmask_bits {
5132 u8 reserved_at_0[0x20];
5134 u8 reserved_at_20[0x1f];
5138 struct mlx5_ifc_modify_rqt_in_bits {
5140 u8 reserved_at_10[0x10];
5142 u8 reserved_at_20[0x10];
5145 u8 reserved_at_40[0x8];
5148 u8 reserved_at_60[0x20];
5150 struct mlx5_ifc_rqt_bitmask_bits bitmask;
5152 u8 reserved_at_c0[0x40];
5154 struct mlx5_ifc_rqtc_bits ctx;
5157 struct mlx5_ifc_modify_rq_out_bits {
5159 u8 reserved_at_8[0x18];
5163 u8 reserved_at_40[0x40];
5167 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5168 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5169 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5172 struct mlx5_ifc_modify_rq_in_bits {
5174 u8 reserved_at_10[0x10];
5176 u8 reserved_at_20[0x10];
5180 u8 reserved_at_44[0x4];
5183 u8 reserved_at_60[0x20];
5185 u8 modify_bitmask[0x40];
5187 u8 reserved_at_c0[0x40];
5189 struct mlx5_ifc_rqc_bits ctx;
5192 struct mlx5_ifc_modify_rmp_out_bits {
5194 u8 reserved_at_8[0x18];
5198 u8 reserved_at_40[0x40];
5201 struct mlx5_ifc_rmp_bitmask_bits {
5202 u8 reserved_at_0[0x20];
5204 u8 reserved_at_20[0x1f];
5208 struct mlx5_ifc_modify_rmp_in_bits {
5210 u8 reserved_at_10[0x10];
5212 u8 reserved_at_20[0x10];
5216 u8 reserved_at_44[0x4];
5219 u8 reserved_at_60[0x20];
5221 struct mlx5_ifc_rmp_bitmask_bits bitmask;
5223 u8 reserved_at_c0[0x40];
5225 struct mlx5_ifc_rmpc_bits ctx;
5228 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5230 u8 reserved_at_8[0x18];
5234 u8 reserved_at_40[0x40];
5237 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5238 u8 reserved_at_0[0x14];
5239 u8 disable_uc_local_lb[0x1];
5240 u8 disable_mc_local_lb[0x1];
5245 u8 change_event[0x1];
5247 u8 permanent_address[0x1];
5248 u8 addresses_list[0x1];
5250 u8 reserved_at_1f[0x1];
5253 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5255 u8 reserved_at_10[0x10];
5257 u8 reserved_at_20[0x10];
5260 u8 other_vport[0x1];
5261 u8 reserved_at_41[0xf];
5262 u8 vport_number[0x10];
5264 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5266 u8 reserved_at_80[0x780];
5268 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5271 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5273 u8 reserved_at_8[0x18];
5277 u8 reserved_at_40[0x40];
5280 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5282 u8 reserved_at_10[0x10];
5284 u8 reserved_at_20[0x10];
5287 u8 other_vport[0x1];
5288 u8 reserved_at_41[0xb];
5290 u8 vport_number[0x10];
5292 u8 reserved_at_60[0x20];
5294 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5297 struct mlx5_ifc_modify_cq_out_bits {
5299 u8 reserved_at_8[0x18];
5303 u8 reserved_at_40[0x40];
5307 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5308 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5311 struct mlx5_ifc_modify_cq_in_bits {
5313 u8 reserved_at_10[0x10];
5315 u8 reserved_at_20[0x10];
5318 u8 reserved_at_40[0x8];
5321 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5323 struct mlx5_ifc_cqc_bits cq_context;
5325 u8 reserved_at_280[0x600];
5330 struct mlx5_ifc_modify_cong_status_out_bits {
5332 u8 reserved_at_8[0x18];
5336 u8 reserved_at_40[0x40];
5339 struct mlx5_ifc_modify_cong_status_in_bits {
5341 u8 reserved_at_10[0x10];
5343 u8 reserved_at_20[0x10];
5346 u8 reserved_at_40[0x18];
5348 u8 cong_protocol[0x4];
5352 u8 reserved_at_62[0x1e];
5355 struct mlx5_ifc_modify_cong_params_out_bits {
5357 u8 reserved_at_8[0x18];
5361 u8 reserved_at_40[0x40];
5364 struct mlx5_ifc_modify_cong_params_in_bits {
5366 u8 reserved_at_10[0x10];
5368 u8 reserved_at_20[0x10];
5371 u8 reserved_at_40[0x1c];
5372 u8 cong_protocol[0x4];
5374 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5376 u8 reserved_at_80[0x80];
5378 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5381 struct mlx5_ifc_manage_pages_out_bits {
5383 u8 reserved_at_8[0x18];
5387 u8 output_num_entries[0x20];
5389 u8 reserved_at_60[0x20];
5395 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5396 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5397 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5400 struct mlx5_ifc_manage_pages_in_bits {
5402 u8 reserved_at_10[0x10];
5404 u8 reserved_at_20[0x10];
5407 u8 reserved_at_40[0x10];
5408 u8 function_id[0x10];
5410 u8 input_num_entries[0x20];
5415 struct mlx5_ifc_mad_ifc_out_bits {
5417 u8 reserved_at_8[0x18];
5421 u8 reserved_at_40[0x40];
5423 u8 response_mad_packet[256][0x8];
5426 struct mlx5_ifc_mad_ifc_in_bits {
5428 u8 reserved_at_10[0x10];
5430 u8 reserved_at_20[0x10];
5433 u8 remote_lid[0x10];
5434 u8 reserved_at_50[0x8];
5437 u8 reserved_at_60[0x20];
5442 struct mlx5_ifc_init_hca_out_bits {
5444 u8 reserved_at_8[0x18];
5448 u8 reserved_at_40[0x40];
5451 struct mlx5_ifc_init_hca_in_bits {
5453 u8 reserved_at_10[0x10];
5455 u8 reserved_at_20[0x10];
5458 u8 reserved_at_40[0x40];
5461 struct mlx5_ifc_init2rtr_qp_out_bits {
5463 u8 reserved_at_8[0x18];
5467 u8 reserved_at_40[0x40];
5470 struct mlx5_ifc_init2rtr_qp_in_bits {
5472 u8 reserved_at_10[0x10];
5474 u8 reserved_at_20[0x10];
5477 u8 reserved_at_40[0x8];
5480 u8 reserved_at_60[0x20];
5482 u8 opt_param_mask[0x20];
5484 u8 reserved_at_a0[0x20];
5486 struct mlx5_ifc_qpc_bits qpc;
5488 u8 reserved_at_800[0x80];
5491 struct mlx5_ifc_init2init_qp_out_bits {
5493 u8 reserved_at_8[0x18];
5497 u8 reserved_at_40[0x40];
5500 struct mlx5_ifc_init2init_qp_in_bits {
5502 u8 reserved_at_10[0x10];
5504 u8 reserved_at_20[0x10];
5507 u8 reserved_at_40[0x8];
5510 u8 reserved_at_60[0x20];
5512 u8 opt_param_mask[0x20];
5514 u8 reserved_at_a0[0x20];
5516 struct mlx5_ifc_qpc_bits qpc;
5518 u8 reserved_at_800[0x80];
5521 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5523 u8 reserved_at_8[0x18];
5527 u8 reserved_at_40[0x40];
5529 u8 packet_headers_log[128][0x8];
5531 u8 packet_syndrome[64][0x8];
5534 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5536 u8 reserved_at_10[0x10];
5538 u8 reserved_at_20[0x10];
5541 u8 reserved_at_40[0x40];
5544 struct mlx5_ifc_gen_eqe_in_bits {
5546 u8 reserved_at_10[0x10];
5548 u8 reserved_at_20[0x10];
5551 u8 reserved_at_40[0x18];
5554 u8 reserved_at_60[0x20];
5559 struct mlx5_ifc_gen_eq_out_bits {
5561 u8 reserved_at_8[0x18];
5565 u8 reserved_at_40[0x40];
5568 struct mlx5_ifc_enable_hca_out_bits {
5570 u8 reserved_at_8[0x18];
5574 u8 reserved_at_40[0x20];
5577 struct mlx5_ifc_enable_hca_in_bits {
5579 u8 reserved_at_10[0x10];
5581 u8 reserved_at_20[0x10];
5584 u8 reserved_at_40[0x10];
5585 u8 function_id[0x10];
5587 u8 reserved_at_60[0x20];
5590 struct mlx5_ifc_drain_dct_out_bits {
5592 u8 reserved_at_8[0x18];
5596 u8 reserved_at_40[0x40];
5599 struct mlx5_ifc_drain_dct_in_bits {
5601 u8 reserved_at_10[0x10];
5603 u8 reserved_at_20[0x10];
5606 u8 reserved_at_40[0x8];
5609 u8 reserved_at_60[0x20];
5612 struct mlx5_ifc_disable_hca_out_bits {
5614 u8 reserved_at_8[0x18];
5618 u8 reserved_at_40[0x20];
5621 struct mlx5_ifc_disable_hca_in_bits {
5623 u8 reserved_at_10[0x10];
5625 u8 reserved_at_20[0x10];
5628 u8 reserved_at_40[0x10];
5629 u8 function_id[0x10];
5631 u8 reserved_at_60[0x20];
5634 struct mlx5_ifc_detach_from_mcg_out_bits {
5636 u8 reserved_at_8[0x18];
5640 u8 reserved_at_40[0x40];
5643 struct mlx5_ifc_detach_from_mcg_in_bits {
5645 u8 reserved_at_10[0x10];
5647 u8 reserved_at_20[0x10];
5650 u8 reserved_at_40[0x8];
5653 u8 reserved_at_60[0x20];
5655 u8 multicast_gid[16][0x8];
5658 struct mlx5_ifc_destroy_xrq_out_bits {
5660 u8 reserved_at_8[0x18];
5664 u8 reserved_at_40[0x40];
5667 struct mlx5_ifc_destroy_xrq_in_bits {
5669 u8 reserved_at_10[0x10];
5671 u8 reserved_at_20[0x10];
5674 u8 reserved_at_40[0x8];
5677 u8 reserved_at_60[0x20];
5680 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5682 u8 reserved_at_8[0x18];
5686 u8 reserved_at_40[0x40];
5689 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5691 u8 reserved_at_10[0x10];
5693 u8 reserved_at_20[0x10];
5696 u8 reserved_at_40[0x8];
5699 u8 reserved_at_60[0x20];
5702 struct mlx5_ifc_destroy_tis_out_bits {
5704 u8 reserved_at_8[0x18];
5708 u8 reserved_at_40[0x40];
5711 struct mlx5_ifc_destroy_tis_in_bits {
5713 u8 reserved_at_10[0x10];
5715 u8 reserved_at_20[0x10];
5718 u8 reserved_at_40[0x8];
5721 u8 reserved_at_60[0x20];
5724 struct mlx5_ifc_destroy_tir_out_bits {
5726 u8 reserved_at_8[0x18];
5730 u8 reserved_at_40[0x40];
5733 struct mlx5_ifc_destroy_tir_in_bits {
5735 u8 reserved_at_10[0x10];
5737 u8 reserved_at_20[0x10];
5740 u8 reserved_at_40[0x8];
5743 u8 reserved_at_60[0x20];
5746 struct mlx5_ifc_destroy_srq_out_bits {
5748 u8 reserved_at_8[0x18];
5752 u8 reserved_at_40[0x40];
5755 struct mlx5_ifc_destroy_srq_in_bits {
5757 u8 reserved_at_10[0x10];
5759 u8 reserved_at_20[0x10];
5762 u8 reserved_at_40[0x8];
5765 u8 reserved_at_60[0x20];
5768 struct mlx5_ifc_destroy_sq_out_bits {
5770 u8 reserved_at_8[0x18];
5774 u8 reserved_at_40[0x40];
5777 struct mlx5_ifc_destroy_sq_in_bits {
5779 u8 reserved_at_10[0x10];
5781 u8 reserved_at_20[0x10];
5784 u8 reserved_at_40[0x8];
5787 u8 reserved_at_60[0x20];
5790 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5792 u8 reserved_at_8[0x18];
5796 u8 reserved_at_40[0x1c0];
5799 struct mlx5_ifc_destroy_scheduling_element_in_bits {
5801 u8 reserved_at_10[0x10];
5803 u8 reserved_at_20[0x10];
5806 u8 scheduling_hierarchy[0x8];
5807 u8 reserved_at_48[0x18];
5809 u8 scheduling_element_id[0x20];
5811 u8 reserved_at_80[0x180];
5814 struct mlx5_ifc_destroy_rqt_out_bits {
5816 u8 reserved_at_8[0x18];
5820 u8 reserved_at_40[0x40];
5823 struct mlx5_ifc_destroy_rqt_in_bits {
5825 u8 reserved_at_10[0x10];
5827 u8 reserved_at_20[0x10];
5830 u8 reserved_at_40[0x8];
5833 u8 reserved_at_60[0x20];
5836 struct mlx5_ifc_destroy_rq_out_bits {
5838 u8 reserved_at_8[0x18];
5842 u8 reserved_at_40[0x40];
5845 struct mlx5_ifc_destroy_rq_in_bits {
5847 u8 reserved_at_10[0x10];
5849 u8 reserved_at_20[0x10];
5852 u8 reserved_at_40[0x8];
5855 u8 reserved_at_60[0x20];
5858 struct mlx5_ifc_set_delay_drop_params_in_bits {
5860 u8 reserved_at_10[0x10];
5862 u8 reserved_at_20[0x10];
5865 u8 reserved_at_40[0x20];
5867 u8 reserved_at_60[0x10];
5868 u8 delay_drop_timeout[0x10];
5871 struct mlx5_ifc_set_delay_drop_params_out_bits {
5873 u8 reserved_at_8[0x18];
5877 u8 reserved_at_40[0x40];
5880 struct mlx5_ifc_destroy_rmp_out_bits {
5882 u8 reserved_at_8[0x18];
5886 u8 reserved_at_40[0x40];
5889 struct mlx5_ifc_destroy_rmp_in_bits {
5891 u8 reserved_at_10[0x10];
5893 u8 reserved_at_20[0x10];
5896 u8 reserved_at_40[0x8];
5899 u8 reserved_at_60[0x20];
5902 struct mlx5_ifc_destroy_qp_out_bits {
5904 u8 reserved_at_8[0x18];
5908 u8 reserved_at_40[0x40];
5911 struct mlx5_ifc_destroy_qp_in_bits {
5913 u8 reserved_at_10[0x10];
5915 u8 reserved_at_20[0x10];
5918 u8 reserved_at_40[0x8];
5921 u8 reserved_at_60[0x20];
5924 struct mlx5_ifc_destroy_psv_out_bits {
5926 u8 reserved_at_8[0x18];
5930 u8 reserved_at_40[0x40];
5933 struct mlx5_ifc_destroy_psv_in_bits {
5935 u8 reserved_at_10[0x10];
5937 u8 reserved_at_20[0x10];
5940 u8 reserved_at_40[0x8];
5943 u8 reserved_at_60[0x20];
5946 struct mlx5_ifc_destroy_mkey_out_bits {
5948 u8 reserved_at_8[0x18];
5952 u8 reserved_at_40[0x40];
5955 struct mlx5_ifc_destroy_mkey_in_bits {
5957 u8 reserved_at_10[0x10];
5959 u8 reserved_at_20[0x10];
5962 u8 reserved_at_40[0x8];
5963 u8 mkey_index[0x18];
5965 u8 reserved_at_60[0x20];
5968 struct mlx5_ifc_destroy_flow_table_out_bits {
5970 u8 reserved_at_8[0x18];
5974 u8 reserved_at_40[0x40];
5977 struct mlx5_ifc_destroy_flow_table_in_bits {
5979 u8 reserved_at_10[0x10];
5981 u8 reserved_at_20[0x10];
5984 u8 other_vport[0x1];
5985 u8 reserved_at_41[0xf];
5986 u8 vport_number[0x10];
5988 u8 reserved_at_60[0x20];
5991 u8 reserved_at_88[0x18];
5993 u8 reserved_at_a0[0x8];
5996 u8 reserved_at_c0[0x140];
5999 struct mlx5_ifc_destroy_flow_group_out_bits {
6001 u8 reserved_at_8[0x18];
6005 u8 reserved_at_40[0x40];
6008 struct mlx5_ifc_destroy_flow_group_in_bits {
6010 u8 reserved_at_10[0x10];
6012 u8 reserved_at_20[0x10];
6015 u8 other_vport[0x1];
6016 u8 reserved_at_41[0xf];
6017 u8 vport_number[0x10];
6019 u8 reserved_at_60[0x20];
6022 u8 reserved_at_88[0x18];
6024 u8 reserved_at_a0[0x8];
6029 u8 reserved_at_e0[0x120];
6032 struct mlx5_ifc_destroy_eq_out_bits {
6034 u8 reserved_at_8[0x18];
6038 u8 reserved_at_40[0x40];
6041 struct mlx5_ifc_destroy_eq_in_bits {
6043 u8 reserved_at_10[0x10];
6045 u8 reserved_at_20[0x10];
6048 u8 reserved_at_40[0x18];
6051 u8 reserved_at_60[0x20];
6054 struct mlx5_ifc_destroy_dct_out_bits {
6056 u8 reserved_at_8[0x18];
6060 u8 reserved_at_40[0x40];
6063 struct mlx5_ifc_destroy_dct_in_bits {
6065 u8 reserved_at_10[0x10];
6067 u8 reserved_at_20[0x10];
6070 u8 reserved_at_40[0x8];
6073 u8 reserved_at_60[0x20];
6076 struct mlx5_ifc_destroy_cq_out_bits {
6078 u8 reserved_at_8[0x18];
6082 u8 reserved_at_40[0x40];
6085 struct mlx5_ifc_destroy_cq_in_bits {
6087 u8 reserved_at_10[0x10];
6089 u8 reserved_at_20[0x10];
6092 u8 reserved_at_40[0x8];
6095 u8 reserved_at_60[0x20];
6098 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6100 u8 reserved_at_8[0x18];
6104 u8 reserved_at_40[0x40];
6107 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6109 u8 reserved_at_10[0x10];
6111 u8 reserved_at_20[0x10];
6114 u8 reserved_at_40[0x20];
6116 u8 reserved_at_60[0x10];
6117 u8 vxlan_udp_port[0x10];
6120 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6122 u8 reserved_at_8[0x18];
6126 u8 reserved_at_40[0x40];
6129 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6131 u8 reserved_at_10[0x10];
6133 u8 reserved_at_20[0x10];
6136 u8 reserved_at_40[0x60];
6138 u8 reserved_at_a0[0x8];
6139 u8 table_index[0x18];
6141 u8 reserved_at_c0[0x140];
6144 struct mlx5_ifc_delete_fte_out_bits {
6146 u8 reserved_at_8[0x18];
6150 u8 reserved_at_40[0x40];
6153 struct mlx5_ifc_delete_fte_in_bits {
6155 u8 reserved_at_10[0x10];
6157 u8 reserved_at_20[0x10];
6160 u8 other_vport[0x1];
6161 u8 reserved_at_41[0xf];
6162 u8 vport_number[0x10];
6164 u8 reserved_at_60[0x20];
6167 u8 reserved_at_88[0x18];
6169 u8 reserved_at_a0[0x8];
6172 u8 reserved_at_c0[0x40];
6174 u8 flow_index[0x20];
6176 u8 reserved_at_120[0xe0];
6179 struct mlx5_ifc_dealloc_xrcd_out_bits {
6181 u8 reserved_at_8[0x18];
6185 u8 reserved_at_40[0x40];
6188 struct mlx5_ifc_dealloc_xrcd_in_bits {
6190 u8 reserved_at_10[0x10];
6192 u8 reserved_at_20[0x10];
6195 u8 reserved_at_40[0x8];
6198 u8 reserved_at_60[0x20];
6201 struct mlx5_ifc_dealloc_uar_out_bits {
6203 u8 reserved_at_8[0x18];
6207 u8 reserved_at_40[0x40];
6210 struct mlx5_ifc_dealloc_uar_in_bits {
6212 u8 reserved_at_10[0x10];
6214 u8 reserved_at_20[0x10];
6217 u8 reserved_at_40[0x8];
6220 u8 reserved_at_60[0x20];
6223 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6225 u8 reserved_at_8[0x18];
6229 u8 reserved_at_40[0x40];
6232 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6234 u8 reserved_at_10[0x10];
6236 u8 reserved_at_20[0x10];
6239 u8 reserved_at_40[0x8];
6240 u8 transport_domain[0x18];
6242 u8 reserved_at_60[0x20];
6245 struct mlx5_ifc_dealloc_q_counter_out_bits {
6247 u8 reserved_at_8[0x18];
6251 u8 reserved_at_40[0x40];
6254 struct mlx5_ifc_dealloc_q_counter_in_bits {
6256 u8 reserved_at_10[0x10];
6258 u8 reserved_at_20[0x10];
6261 u8 reserved_at_40[0x18];
6262 u8 counter_set_id[0x8];
6264 u8 reserved_at_60[0x20];
6267 struct mlx5_ifc_dealloc_pd_out_bits {
6269 u8 reserved_at_8[0x18];
6273 u8 reserved_at_40[0x40];
6276 struct mlx5_ifc_dealloc_pd_in_bits {
6278 u8 reserved_at_10[0x10];
6280 u8 reserved_at_20[0x10];
6283 u8 reserved_at_40[0x8];
6286 u8 reserved_at_60[0x20];
6289 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6291 u8 reserved_at_8[0x18];
6295 u8 reserved_at_40[0x40];
6298 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6300 u8 reserved_at_10[0x10];
6302 u8 reserved_at_20[0x10];
6305 u8 reserved_at_40[0x10];
6306 u8 flow_counter_id[0x10];
6308 u8 reserved_at_60[0x20];
6311 struct mlx5_ifc_create_xrq_out_bits {
6313 u8 reserved_at_8[0x18];
6317 u8 reserved_at_40[0x8];
6320 u8 reserved_at_60[0x20];
6323 struct mlx5_ifc_create_xrq_in_bits {
6325 u8 reserved_at_10[0x10];
6327 u8 reserved_at_20[0x10];
6330 u8 reserved_at_40[0x40];
6332 struct mlx5_ifc_xrqc_bits xrq_context;
6335 struct mlx5_ifc_create_xrc_srq_out_bits {
6337 u8 reserved_at_8[0x18];
6341 u8 reserved_at_40[0x8];
6344 u8 reserved_at_60[0x20];
6347 struct mlx5_ifc_create_xrc_srq_in_bits {
6349 u8 reserved_at_10[0x10];
6351 u8 reserved_at_20[0x10];
6354 u8 reserved_at_40[0x40];
6356 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6358 u8 reserved_at_280[0x600];
6363 struct mlx5_ifc_create_tis_out_bits {
6365 u8 reserved_at_8[0x18];
6369 u8 reserved_at_40[0x8];
6372 u8 reserved_at_60[0x20];
6375 struct mlx5_ifc_create_tis_in_bits {
6377 u8 reserved_at_10[0x10];
6379 u8 reserved_at_20[0x10];
6382 u8 reserved_at_40[0xc0];
6384 struct mlx5_ifc_tisc_bits ctx;
6387 struct mlx5_ifc_create_tir_out_bits {
6389 u8 reserved_at_8[0x18];
6393 u8 reserved_at_40[0x8];
6396 u8 reserved_at_60[0x20];
6399 struct mlx5_ifc_create_tir_in_bits {
6401 u8 reserved_at_10[0x10];
6403 u8 reserved_at_20[0x10];
6406 u8 reserved_at_40[0xc0];
6408 struct mlx5_ifc_tirc_bits ctx;
6411 struct mlx5_ifc_create_srq_out_bits {
6413 u8 reserved_at_8[0x18];
6417 u8 reserved_at_40[0x8];
6420 u8 reserved_at_60[0x20];
6423 struct mlx5_ifc_create_srq_in_bits {
6425 u8 reserved_at_10[0x10];
6427 u8 reserved_at_20[0x10];
6430 u8 reserved_at_40[0x40];
6432 struct mlx5_ifc_srqc_bits srq_context_entry;
6434 u8 reserved_at_280[0x600];
6439 struct mlx5_ifc_create_sq_out_bits {
6441 u8 reserved_at_8[0x18];
6445 u8 reserved_at_40[0x8];
6448 u8 reserved_at_60[0x20];
6451 struct mlx5_ifc_create_sq_in_bits {
6453 u8 reserved_at_10[0x10];
6455 u8 reserved_at_20[0x10];
6458 u8 reserved_at_40[0xc0];
6460 struct mlx5_ifc_sqc_bits ctx;
6463 struct mlx5_ifc_create_scheduling_element_out_bits {
6465 u8 reserved_at_8[0x18];
6469 u8 reserved_at_40[0x40];
6471 u8 scheduling_element_id[0x20];
6473 u8 reserved_at_a0[0x160];
6476 struct mlx5_ifc_create_scheduling_element_in_bits {
6478 u8 reserved_at_10[0x10];
6480 u8 reserved_at_20[0x10];
6483 u8 scheduling_hierarchy[0x8];
6484 u8 reserved_at_48[0x18];
6486 u8 reserved_at_60[0xa0];
6488 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6490 u8 reserved_at_300[0x100];
6493 struct mlx5_ifc_create_rqt_out_bits {
6495 u8 reserved_at_8[0x18];
6499 u8 reserved_at_40[0x8];
6502 u8 reserved_at_60[0x20];
6505 struct mlx5_ifc_create_rqt_in_bits {
6507 u8 reserved_at_10[0x10];
6509 u8 reserved_at_20[0x10];
6512 u8 reserved_at_40[0xc0];
6514 struct mlx5_ifc_rqtc_bits rqt_context;
6517 struct mlx5_ifc_create_rq_out_bits {
6519 u8 reserved_at_8[0x18];
6523 u8 reserved_at_40[0x8];
6526 u8 reserved_at_60[0x20];
6529 struct mlx5_ifc_create_rq_in_bits {
6531 u8 reserved_at_10[0x10];
6533 u8 reserved_at_20[0x10];
6536 u8 reserved_at_40[0xc0];
6538 struct mlx5_ifc_rqc_bits ctx;
6541 struct mlx5_ifc_create_rmp_out_bits {
6543 u8 reserved_at_8[0x18];
6547 u8 reserved_at_40[0x8];
6550 u8 reserved_at_60[0x20];
6553 struct mlx5_ifc_create_rmp_in_bits {
6555 u8 reserved_at_10[0x10];
6557 u8 reserved_at_20[0x10];
6560 u8 reserved_at_40[0xc0];
6562 struct mlx5_ifc_rmpc_bits ctx;
6565 struct mlx5_ifc_create_qp_out_bits {
6567 u8 reserved_at_8[0x18];
6571 u8 reserved_at_40[0x8];
6574 u8 reserved_at_60[0x20];
6577 struct mlx5_ifc_create_qp_in_bits {
6579 u8 reserved_at_10[0x10];
6581 u8 reserved_at_20[0x10];
6584 u8 reserved_at_40[0x40];
6586 u8 opt_param_mask[0x20];
6588 u8 reserved_at_a0[0x20];
6590 struct mlx5_ifc_qpc_bits qpc;
6592 u8 reserved_at_800[0x80];
6597 struct mlx5_ifc_create_psv_out_bits {
6599 u8 reserved_at_8[0x18];
6603 u8 reserved_at_40[0x40];
6605 u8 reserved_at_80[0x8];
6606 u8 psv0_index[0x18];
6608 u8 reserved_at_a0[0x8];
6609 u8 psv1_index[0x18];
6611 u8 reserved_at_c0[0x8];
6612 u8 psv2_index[0x18];
6614 u8 reserved_at_e0[0x8];
6615 u8 psv3_index[0x18];
6618 struct mlx5_ifc_create_psv_in_bits {
6620 u8 reserved_at_10[0x10];
6622 u8 reserved_at_20[0x10];
6626 u8 reserved_at_44[0x4];
6629 u8 reserved_at_60[0x20];
6632 struct mlx5_ifc_create_mkey_out_bits {
6634 u8 reserved_at_8[0x18];
6638 u8 reserved_at_40[0x8];
6639 u8 mkey_index[0x18];
6641 u8 reserved_at_60[0x20];
6644 struct mlx5_ifc_create_mkey_in_bits {
6646 u8 reserved_at_10[0x10];
6648 u8 reserved_at_20[0x10];
6651 u8 reserved_at_40[0x20];
6654 u8 reserved_at_61[0x1f];
6656 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6658 u8 reserved_at_280[0x80];
6660 u8 translations_octword_actual_size[0x20];
6662 u8 reserved_at_320[0x560];
6664 u8 klm_pas_mtt[0][0x20];
6667 struct mlx5_ifc_create_flow_table_out_bits {
6669 u8 reserved_at_8[0x18];
6673 u8 reserved_at_40[0x8];
6676 u8 reserved_at_60[0x20];
6679 struct mlx5_ifc_flow_table_context_bits {
6682 u8 reserved_at_2[0x2];
6683 u8 table_miss_action[0x4];
6685 u8 reserved_at_10[0x8];
6688 u8 reserved_at_20[0x8];
6689 u8 table_miss_id[0x18];
6691 u8 reserved_at_40[0x8];
6692 u8 lag_master_next_table_id[0x18];
6694 u8 reserved_at_60[0xe0];
6697 struct mlx5_ifc_create_flow_table_in_bits {
6699 u8 reserved_at_10[0x10];
6701 u8 reserved_at_20[0x10];
6704 u8 other_vport[0x1];
6705 u8 reserved_at_41[0xf];
6706 u8 vport_number[0x10];
6708 u8 reserved_at_60[0x20];
6711 u8 reserved_at_88[0x18];
6713 u8 reserved_at_a0[0x20];
6715 struct mlx5_ifc_flow_table_context_bits flow_table_context;
6718 struct mlx5_ifc_create_flow_group_out_bits {
6720 u8 reserved_at_8[0x18];
6724 u8 reserved_at_40[0x8];
6727 u8 reserved_at_60[0x20];
6731 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6732 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6733 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6736 struct mlx5_ifc_create_flow_group_in_bits {
6738 u8 reserved_at_10[0x10];
6740 u8 reserved_at_20[0x10];
6743 u8 other_vport[0x1];
6744 u8 reserved_at_41[0xf];
6745 u8 vport_number[0x10];
6747 u8 reserved_at_60[0x20];
6750 u8 reserved_at_88[0x18];
6752 u8 reserved_at_a0[0x8];
6755 u8 reserved_at_c0[0x20];
6757 u8 start_flow_index[0x20];
6759 u8 reserved_at_100[0x20];
6761 u8 end_flow_index[0x20];
6763 u8 reserved_at_140[0xa0];
6765 u8 reserved_at_1e0[0x18];
6766 u8 match_criteria_enable[0x8];
6768 struct mlx5_ifc_fte_match_param_bits match_criteria;
6770 u8 reserved_at_1200[0xe00];
6773 struct mlx5_ifc_create_eq_out_bits {
6775 u8 reserved_at_8[0x18];
6779 u8 reserved_at_40[0x18];
6782 u8 reserved_at_60[0x20];
6785 struct mlx5_ifc_create_eq_in_bits {
6787 u8 reserved_at_10[0x10];
6789 u8 reserved_at_20[0x10];
6792 u8 reserved_at_40[0x40];
6794 struct mlx5_ifc_eqc_bits eq_context_entry;
6796 u8 reserved_at_280[0x40];
6798 u8 event_bitmask[0x40];
6800 u8 reserved_at_300[0x580];
6805 struct mlx5_ifc_create_dct_out_bits {
6807 u8 reserved_at_8[0x18];
6811 u8 reserved_at_40[0x8];
6814 u8 reserved_at_60[0x20];
6817 struct mlx5_ifc_create_dct_in_bits {
6819 u8 reserved_at_10[0x10];
6821 u8 reserved_at_20[0x10];
6824 u8 reserved_at_40[0x40];
6826 struct mlx5_ifc_dctc_bits dct_context_entry;
6828 u8 reserved_at_280[0x180];
6831 struct mlx5_ifc_create_cq_out_bits {
6833 u8 reserved_at_8[0x18];
6837 u8 reserved_at_40[0x8];
6840 u8 reserved_at_60[0x20];
6843 struct mlx5_ifc_create_cq_in_bits {
6845 u8 reserved_at_10[0x10];
6847 u8 reserved_at_20[0x10];
6850 u8 reserved_at_40[0x40];
6852 struct mlx5_ifc_cqc_bits cq_context;
6854 u8 reserved_at_280[0x600];
6859 struct mlx5_ifc_config_int_moderation_out_bits {
6861 u8 reserved_at_8[0x18];
6865 u8 reserved_at_40[0x4];
6867 u8 int_vector[0x10];
6869 u8 reserved_at_60[0x20];
6873 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6874 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6877 struct mlx5_ifc_config_int_moderation_in_bits {
6879 u8 reserved_at_10[0x10];
6881 u8 reserved_at_20[0x10];
6884 u8 reserved_at_40[0x4];
6886 u8 int_vector[0x10];
6888 u8 reserved_at_60[0x20];
6891 struct mlx5_ifc_attach_to_mcg_out_bits {
6893 u8 reserved_at_8[0x18];
6897 u8 reserved_at_40[0x40];
6900 struct mlx5_ifc_attach_to_mcg_in_bits {
6902 u8 reserved_at_10[0x10];
6904 u8 reserved_at_20[0x10];
6907 u8 reserved_at_40[0x8];
6910 u8 reserved_at_60[0x20];
6912 u8 multicast_gid[16][0x8];
6915 struct mlx5_ifc_arm_xrq_out_bits {
6917 u8 reserved_at_8[0x18];
6921 u8 reserved_at_40[0x40];
6924 struct mlx5_ifc_arm_xrq_in_bits {
6926 u8 reserved_at_10[0x10];
6928 u8 reserved_at_20[0x10];
6931 u8 reserved_at_40[0x8];
6934 u8 reserved_at_60[0x10];
6938 struct mlx5_ifc_arm_xrc_srq_out_bits {
6940 u8 reserved_at_8[0x18];
6944 u8 reserved_at_40[0x40];
6948 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
6951 struct mlx5_ifc_arm_xrc_srq_in_bits {
6953 u8 reserved_at_10[0x10];
6955 u8 reserved_at_20[0x10];
6958 u8 reserved_at_40[0x8];
6961 u8 reserved_at_60[0x10];
6965 struct mlx5_ifc_arm_rq_out_bits {
6967 u8 reserved_at_8[0x18];
6971 u8 reserved_at_40[0x40];
6975 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6976 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
6979 struct mlx5_ifc_arm_rq_in_bits {
6981 u8 reserved_at_10[0x10];
6983 u8 reserved_at_20[0x10];
6986 u8 reserved_at_40[0x8];
6987 u8 srq_number[0x18];
6989 u8 reserved_at_60[0x10];
6993 struct mlx5_ifc_arm_dct_out_bits {
6995 u8 reserved_at_8[0x18];
6999 u8 reserved_at_40[0x40];
7002 struct mlx5_ifc_arm_dct_in_bits {
7004 u8 reserved_at_10[0x10];
7006 u8 reserved_at_20[0x10];
7009 u8 reserved_at_40[0x8];
7010 u8 dct_number[0x18];
7012 u8 reserved_at_60[0x20];
7015 struct mlx5_ifc_alloc_xrcd_out_bits {
7017 u8 reserved_at_8[0x18];
7021 u8 reserved_at_40[0x8];
7024 u8 reserved_at_60[0x20];
7027 struct mlx5_ifc_alloc_xrcd_in_bits {
7029 u8 reserved_at_10[0x10];
7031 u8 reserved_at_20[0x10];
7034 u8 reserved_at_40[0x40];
7037 struct mlx5_ifc_alloc_uar_out_bits {
7039 u8 reserved_at_8[0x18];
7043 u8 reserved_at_40[0x8];
7046 u8 reserved_at_60[0x20];
7049 struct mlx5_ifc_alloc_uar_in_bits {
7051 u8 reserved_at_10[0x10];
7053 u8 reserved_at_20[0x10];
7056 u8 reserved_at_40[0x40];
7059 struct mlx5_ifc_alloc_transport_domain_out_bits {
7061 u8 reserved_at_8[0x18];
7065 u8 reserved_at_40[0x8];
7066 u8 transport_domain[0x18];
7068 u8 reserved_at_60[0x20];
7071 struct mlx5_ifc_alloc_transport_domain_in_bits {
7073 u8 reserved_at_10[0x10];
7075 u8 reserved_at_20[0x10];
7078 u8 reserved_at_40[0x40];
7081 struct mlx5_ifc_alloc_q_counter_out_bits {
7083 u8 reserved_at_8[0x18];
7087 u8 reserved_at_40[0x18];
7088 u8 counter_set_id[0x8];
7090 u8 reserved_at_60[0x20];
7093 struct mlx5_ifc_alloc_q_counter_in_bits {
7095 u8 reserved_at_10[0x10];
7097 u8 reserved_at_20[0x10];
7100 u8 reserved_at_40[0x40];
7103 struct mlx5_ifc_alloc_pd_out_bits {
7105 u8 reserved_at_8[0x18];
7109 u8 reserved_at_40[0x8];
7112 u8 reserved_at_60[0x20];
7115 struct mlx5_ifc_alloc_pd_in_bits {
7117 u8 reserved_at_10[0x10];
7119 u8 reserved_at_20[0x10];
7122 u8 reserved_at_40[0x40];
7125 struct mlx5_ifc_alloc_flow_counter_out_bits {
7127 u8 reserved_at_8[0x18];
7131 u8 reserved_at_40[0x10];
7132 u8 flow_counter_id[0x10];
7134 u8 reserved_at_60[0x20];
7137 struct mlx5_ifc_alloc_flow_counter_in_bits {
7139 u8 reserved_at_10[0x10];
7141 u8 reserved_at_20[0x10];
7144 u8 reserved_at_40[0x40];
7147 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7149 u8 reserved_at_8[0x18];
7153 u8 reserved_at_40[0x40];
7156 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7158 u8 reserved_at_10[0x10];
7160 u8 reserved_at_20[0x10];
7163 u8 reserved_at_40[0x20];
7165 u8 reserved_at_60[0x10];
7166 u8 vxlan_udp_port[0x10];
7169 struct mlx5_ifc_set_rate_limit_out_bits {
7171 u8 reserved_at_8[0x18];
7175 u8 reserved_at_40[0x40];
7178 struct mlx5_ifc_set_rate_limit_in_bits {
7180 u8 reserved_at_10[0x10];
7182 u8 reserved_at_20[0x10];
7185 u8 reserved_at_40[0x10];
7186 u8 rate_limit_index[0x10];
7188 u8 reserved_at_60[0x20];
7190 u8 rate_limit[0x20];
7193 struct mlx5_ifc_access_register_out_bits {
7195 u8 reserved_at_8[0x18];
7199 u8 reserved_at_40[0x40];
7201 u8 register_data[0][0x20];
7205 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7206 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7209 struct mlx5_ifc_access_register_in_bits {
7211 u8 reserved_at_10[0x10];
7213 u8 reserved_at_20[0x10];
7216 u8 reserved_at_40[0x10];
7217 u8 register_id[0x10];
7221 u8 register_data[0][0x20];
7224 struct mlx5_ifc_sltp_reg_bits {
7229 u8 reserved_at_12[0x2];
7231 u8 reserved_at_18[0x8];
7233 u8 reserved_at_20[0x20];
7235 u8 reserved_at_40[0x7];
7241 u8 reserved_at_60[0xc];
7242 u8 ob_preemp_mode[0x4];
7246 u8 reserved_at_80[0x20];
7249 struct mlx5_ifc_slrg_reg_bits {
7254 u8 reserved_at_12[0x2];
7256 u8 reserved_at_18[0x8];
7258 u8 time_to_link_up[0x10];
7259 u8 reserved_at_30[0xc];
7260 u8 grade_lane_speed[0x4];
7262 u8 grade_version[0x8];
7265 u8 reserved_at_60[0x4];
7266 u8 height_grade_type[0x4];
7267 u8 height_grade[0x18];
7272 u8 reserved_at_a0[0x10];
7273 u8 height_sigma[0x10];
7275 u8 reserved_at_c0[0x20];
7277 u8 reserved_at_e0[0x4];
7278 u8 phase_grade_type[0x4];
7279 u8 phase_grade[0x18];
7281 u8 reserved_at_100[0x8];
7282 u8 phase_eo_pos[0x8];
7283 u8 reserved_at_110[0x8];
7284 u8 phase_eo_neg[0x8];
7286 u8 ffe_set_tested[0x10];
7287 u8 test_errors_per_lane[0x10];
7290 struct mlx5_ifc_pvlc_reg_bits {
7291 u8 reserved_at_0[0x8];
7293 u8 reserved_at_10[0x10];
7295 u8 reserved_at_20[0x1c];
7298 u8 reserved_at_40[0x1c];
7301 u8 reserved_at_60[0x1c];
7302 u8 vl_operational[0x4];
7305 struct mlx5_ifc_pude_reg_bits {
7308 u8 reserved_at_10[0x4];
7309 u8 admin_status[0x4];
7310 u8 reserved_at_18[0x4];
7311 u8 oper_status[0x4];
7313 u8 reserved_at_20[0x60];
7316 struct mlx5_ifc_ptys_reg_bits {
7317 u8 reserved_at_0[0x1];
7318 u8 an_disable_admin[0x1];
7319 u8 an_disable_cap[0x1];
7320 u8 reserved_at_3[0x5];
7322 u8 reserved_at_10[0xd];
7326 u8 reserved_at_24[0x3c];
7328 u8 eth_proto_capability[0x20];
7330 u8 ib_link_width_capability[0x10];
7331 u8 ib_proto_capability[0x10];
7333 u8 reserved_at_a0[0x20];
7335 u8 eth_proto_admin[0x20];
7337 u8 ib_link_width_admin[0x10];
7338 u8 ib_proto_admin[0x10];
7340 u8 reserved_at_100[0x20];
7342 u8 eth_proto_oper[0x20];
7344 u8 ib_link_width_oper[0x10];
7345 u8 ib_proto_oper[0x10];
7347 u8 reserved_at_160[0x1c];
7348 u8 connector_type[0x4];
7350 u8 eth_proto_lp_advertise[0x20];
7352 u8 reserved_at_1a0[0x60];
7355 struct mlx5_ifc_mlcr_reg_bits {
7356 u8 reserved_at_0[0x8];
7358 u8 reserved_at_10[0x20];
7360 u8 beacon_duration[0x10];
7361 u8 reserved_at_40[0x10];
7363 u8 beacon_remain[0x10];
7366 struct mlx5_ifc_ptas_reg_bits {
7367 u8 reserved_at_0[0x20];
7369 u8 algorithm_options[0x10];
7370 u8 reserved_at_30[0x4];
7371 u8 repetitions_mode[0x4];
7372 u8 num_of_repetitions[0x8];
7374 u8 grade_version[0x8];
7375 u8 height_grade_type[0x4];
7376 u8 phase_grade_type[0x4];
7377 u8 height_grade_weight[0x8];
7378 u8 phase_grade_weight[0x8];
7380 u8 gisim_measure_bits[0x10];
7381 u8 adaptive_tap_measure_bits[0x10];
7383 u8 ber_bath_high_error_threshold[0x10];
7384 u8 ber_bath_mid_error_threshold[0x10];
7386 u8 ber_bath_low_error_threshold[0x10];
7387 u8 one_ratio_high_threshold[0x10];
7389 u8 one_ratio_high_mid_threshold[0x10];
7390 u8 one_ratio_low_mid_threshold[0x10];
7392 u8 one_ratio_low_threshold[0x10];
7393 u8 ndeo_error_threshold[0x10];
7395 u8 mixer_offset_step_size[0x10];
7396 u8 reserved_at_110[0x8];
7397 u8 mix90_phase_for_voltage_bath[0x8];
7399 u8 mixer_offset_start[0x10];
7400 u8 mixer_offset_end[0x10];
7402 u8 reserved_at_140[0x15];
7403 u8 ber_test_time[0xb];
7406 struct mlx5_ifc_pspa_reg_bits {
7410 u8 reserved_at_18[0x8];
7412 u8 reserved_at_20[0x20];
7415 struct mlx5_ifc_pqdr_reg_bits {
7416 u8 reserved_at_0[0x8];
7418 u8 reserved_at_10[0x5];
7420 u8 reserved_at_18[0x6];
7423 u8 reserved_at_20[0x20];
7425 u8 reserved_at_40[0x10];
7426 u8 min_threshold[0x10];
7428 u8 reserved_at_60[0x10];
7429 u8 max_threshold[0x10];
7431 u8 reserved_at_80[0x10];
7432 u8 mark_probability_denominator[0x10];
7434 u8 reserved_at_a0[0x60];
7437 struct mlx5_ifc_ppsc_reg_bits {
7438 u8 reserved_at_0[0x8];
7440 u8 reserved_at_10[0x10];
7442 u8 reserved_at_20[0x60];
7444 u8 reserved_at_80[0x1c];
7447 u8 reserved_at_a0[0x1c];
7448 u8 wrps_status[0x4];
7450 u8 reserved_at_c0[0x8];
7451 u8 up_threshold[0x8];
7452 u8 reserved_at_d0[0x8];
7453 u8 down_threshold[0x8];
7455 u8 reserved_at_e0[0x20];
7457 u8 reserved_at_100[0x1c];
7460 u8 reserved_at_120[0x1c];
7461 u8 srps_status[0x4];
7463 u8 reserved_at_140[0x40];
7466 struct mlx5_ifc_pplr_reg_bits {
7467 u8 reserved_at_0[0x8];
7469 u8 reserved_at_10[0x10];
7471 u8 reserved_at_20[0x8];
7473 u8 reserved_at_30[0x8];
7477 struct mlx5_ifc_pplm_reg_bits {
7478 u8 reserved_at_0[0x8];
7480 u8 reserved_at_10[0x10];
7482 u8 reserved_at_20[0x20];
7484 u8 port_profile_mode[0x8];
7485 u8 static_port_profile[0x8];
7486 u8 active_port_profile[0x8];
7487 u8 reserved_at_58[0x8];
7489 u8 retransmission_active[0x8];
7490 u8 fec_mode_active[0x18];
7492 u8 reserved_at_80[0x20];
7495 struct mlx5_ifc_ppcnt_reg_bits {
7499 u8 reserved_at_12[0x8];
7503 u8 reserved_at_21[0x1c];
7506 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7509 struct mlx5_ifc_mpcnt_reg_bits {
7510 u8 reserved_at_0[0x8];
7512 u8 reserved_at_10[0xa];
7516 u8 reserved_at_21[0x1f];
7518 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7521 struct mlx5_ifc_ppad_reg_bits {
7522 u8 reserved_at_0[0x3];
7524 u8 reserved_at_4[0x4];
7530 u8 reserved_at_40[0x40];
7533 struct mlx5_ifc_pmtu_reg_bits {
7534 u8 reserved_at_0[0x8];
7536 u8 reserved_at_10[0x10];
7539 u8 reserved_at_30[0x10];
7542 u8 reserved_at_50[0x10];
7545 u8 reserved_at_70[0x10];
7548 struct mlx5_ifc_pmpr_reg_bits {
7549 u8 reserved_at_0[0x8];
7551 u8 reserved_at_10[0x10];
7553 u8 reserved_at_20[0x18];
7554 u8 attenuation_5g[0x8];
7556 u8 reserved_at_40[0x18];
7557 u8 attenuation_7g[0x8];
7559 u8 reserved_at_60[0x18];
7560 u8 attenuation_12g[0x8];
7563 struct mlx5_ifc_pmpe_reg_bits {
7564 u8 reserved_at_0[0x8];
7566 u8 reserved_at_10[0xc];
7567 u8 module_status[0x4];
7569 u8 reserved_at_20[0x60];
7572 struct mlx5_ifc_pmpc_reg_bits {
7573 u8 module_state_updated[32][0x8];
7576 struct mlx5_ifc_pmlpn_reg_bits {
7577 u8 reserved_at_0[0x4];
7578 u8 mlpn_status[0x4];
7580 u8 reserved_at_10[0x10];
7583 u8 reserved_at_21[0x1f];
7586 struct mlx5_ifc_pmlp_reg_bits {
7588 u8 reserved_at_1[0x7];
7590 u8 reserved_at_10[0x8];
7593 u8 lane0_module_mapping[0x20];
7595 u8 lane1_module_mapping[0x20];
7597 u8 lane2_module_mapping[0x20];
7599 u8 lane3_module_mapping[0x20];
7601 u8 reserved_at_a0[0x160];
7604 struct mlx5_ifc_pmaos_reg_bits {
7605 u8 reserved_at_0[0x8];
7607 u8 reserved_at_10[0x4];
7608 u8 admin_status[0x4];
7609 u8 reserved_at_18[0x4];
7610 u8 oper_status[0x4];
7614 u8 reserved_at_22[0x1c];
7617 u8 reserved_at_40[0x40];
7620 struct mlx5_ifc_plpc_reg_bits {
7621 u8 reserved_at_0[0x4];
7623 u8 reserved_at_10[0x4];
7625 u8 reserved_at_18[0x8];
7627 u8 reserved_at_20[0x10];
7628 u8 lane_speed[0x10];
7630 u8 reserved_at_40[0x17];
7632 u8 fec_mode_policy[0x8];
7634 u8 retransmission_capability[0x8];
7635 u8 fec_mode_capability[0x18];
7637 u8 retransmission_support_admin[0x8];
7638 u8 fec_mode_support_admin[0x18];
7640 u8 retransmission_request_admin[0x8];
7641 u8 fec_mode_request_admin[0x18];
7643 u8 reserved_at_c0[0x80];
7646 struct mlx5_ifc_plib_reg_bits {
7647 u8 reserved_at_0[0x8];
7649 u8 reserved_at_10[0x8];
7652 u8 reserved_at_20[0x60];
7655 struct mlx5_ifc_plbf_reg_bits {
7656 u8 reserved_at_0[0x8];
7658 u8 reserved_at_10[0xd];
7661 u8 reserved_at_20[0x20];
7664 struct mlx5_ifc_pipg_reg_bits {
7665 u8 reserved_at_0[0x8];
7667 u8 reserved_at_10[0x10];
7670 u8 reserved_at_21[0x19];
7672 u8 reserved_at_3e[0x2];
7675 struct mlx5_ifc_pifr_reg_bits {
7676 u8 reserved_at_0[0x8];
7678 u8 reserved_at_10[0x10];
7680 u8 reserved_at_20[0xe0];
7682 u8 port_filter[8][0x20];
7684 u8 port_filter_update_en[8][0x20];
7687 struct mlx5_ifc_pfcc_reg_bits {
7688 u8 reserved_at_0[0x8];
7690 u8 reserved_at_10[0x10];
7693 u8 reserved_at_24[0x4];
7694 u8 prio_mask_tx[0x8];
7695 u8 reserved_at_30[0x8];
7696 u8 prio_mask_rx[0x8];
7700 u8 reserved_at_42[0x6];
7702 u8 reserved_at_50[0x10];
7706 u8 reserved_at_62[0x6];
7708 u8 reserved_at_70[0x10];
7710 u8 reserved_at_80[0x80];
7713 struct mlx5_ifc_pelc_reg_bits {
7715 u8 reserved_at_4[0x4];
7717 u8 reserved_at_10[0x10];
7720 u8 op_capability[0x8];
7726 u8 capability[0x40];
7732 u8 reserved_at_140[0x80];
7735 struct mlx5_ifc_peir_reg_bits {
7736 u8 reserved_at_0[0x8];
7738 u8 reserved_at_10[0x10];
7740 u8 reserved_at_20[0xc];
7741 u8 error_count[0x4];
7742 u8 reserved_at_30[0x10];
7744 u8 reserved_at_40[0xc];
7746 u8 reserved_at_50[0x8];
7750 struct mlx5_ifc_pcam_enhanced_features_bits {
7751 u8 reserved_at_0[0x7c];
7753 u8 ptys_connector_type[0x1];
7754 u8 reserved_at_7d[0x1];
7755 u8 ppcnt_discard_group[0x1];
7756 u8 ppcnt_statistical_group[0x1];
7759 struct mlx5_ifc_pcam_reg_bits {
7760 u8 reserved_at_0[0x8];
7761 u8 feature_group[0x8];
7762 u8 reserved_at_10[0x8];
7763 u8 access_reg_group[0x8];
7765 u8 reserved_at_20[0x20];
7768 u8 reserved_at_0[0x80];
7769 } port_access_reg_cap_mask;
7771 u8 reserved_at_c0[0x80];
7774 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7775 u8 reserved_at_0[0x80];
7778 u8 reserved_at_1c0[0xc0];
7781 struct mlx5_ifc_mcam_enhanced_features_bits {
7782 u8 reserved_at_0[0x7f];
7784 u8 pcie_performance_group[0x1];
7787 struct mlx5_ifc_mcam_access_reg_bits {
7788 u8 reserved_at_0[0x1c];
7792 u8 reserved_at_1f[0x1];
7794 u8 regs_95_to_64[0x20];
7795 u8 regs_63_to_32[0x20];
7796 u8 regs_31_to_0[0x20];
7799 struct mlx5_ifc_mcam_reg_bits {
7800 u8 reserved_at_0[0x8];
7801 u8 feature_group[0x8];
7802 u8 reserved_at_10[0x8];
7803 u8 access_reg_group[0x8];
7805 u8 reserved_at_20[0x20];
7808 struct mlx5_ifc_mcam_access_reg_bits access_regs;
7809 u8 reserved_at_0[0x80];
7810 } mng_access_reg_cap_mask;
7812 u8 reserved_at_c0[0x80];
7815 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7816 u8 reserved_at_0[0x80];
7817 } mng_feature_cap_mask;
7819 u8 reserved_at_1c0[0x80];
7822 struct mlx5_ifc_pcap_reg_bits {
7823 u8 reserved_at_0[0x8];
7825 u8 reserved_at_10[0x10];
7827 u8 port_capability_mask[4][0x20];
7830 struct mlx5_ifc_paos_reg_bits {
7833 u8 reserved_at_10[0x4];
7834 u8 admin_status[0x4];
7835 u8 reserved_at_18[0x4];
7836 u8 oper_status[0x4];
7840 u8 reserved_at_22[0x1c];
7843 u8 reserved_at_40[0x40];
7846 struct mlx5_ifc_pamp_reg_bits {
7847 u8 reserved_at_0[0x8];
7848 u8 opamp_group[0x8];
7849 u8 reserved_at_10[0xc];
7850 u8 opamp_group_type[0x4];
7852 u8 start_index[0x10];
7853 u8 reserved_at_30[0x4];
7854 u8 num_of_indices[0xc];
7856 u8 index_data[18][0x10];
7859 struct mlx5_ifc_pcmr_reg_bits {
7860 u8 reserved_at_0[0x8];
7862 u8 reserved_at_10[0x2e];
7864 u8 reserved_at_3f[0x1f];
7866 u8 reserved_at_5f[0x1];
7869 struct mlx5_ifc_lane_2_module_mapping_bits {
7870 u8 reserved_at_0[0x6];
7872 u8 reserved_at_8[0x6];
7874 u8 reserved_at_10[0x8];
7878 struct mlx5_ifc_bufferx_reg_bits {
7879 u8 reserved_at_0[0x6];
7882 u8 reserved_at_8[0xc];
7885 u8 xoff_threshold[0x10];
7886 u8 xon_threshold[0x10];
7889 struct mlx5_ifc_set_node_in_bits {
7890 u8 node_description[64][0x8];
7893 struct mlx5_ifc_register_power_settings_bits {
7894 u8 reserved_at_0[0x18];
7895 u8 power_settings_level[0x8];
7897 u8 reserved_at_20[0x60];
7900 struct mlx5_ifc_register_host_endianness_bits {
7902 u8 reserved_at_1[0x1f];
7904 u8 reserved_at_20[0x60];
7907 struct mlx5_ifc_umr_pointer_desc_argument_bits {
7908 u8 reserved_at_0[0x20];
7912 u8 addressh_63_32[0x20];
7914 u8 addressl_31_0[0x20];
7917 struct mlx5_ifc_ud_adrs_vector_bits {
7921 u8 reserved_at_41[0x7];
7922 u8 destination_qp_dct[0x18];
7924 u8 static_rate[0x4];
7925 u8 sl_eth_prio[0x4];
7928 u8 rlid_udp_sport[0x10];
7930 u8 reserved_at_80[0x20];
7932 u8 rmac_47_16[0x20];
7938 u8 reserved_at_e0[0x1];
7940 u8 reserved_at_e2[0x2];
7941 u8 src_addr_index[0x8];
7942 u8 flow_label[0x14];
7944 u8 rgid_rip[16][0x8];
7947 struct mlx5_ifc_pages_req_event_bits {
7948 u8 reserved_at_0[0x10];
7949 u8 function_id[0x10];
7953 u8 reserved_at_40[0xa0];
7956 struct mlx5_ifc_eqe_bits {
7957 u8 reserved_at_0[0x8];
7959 u8 reserved_at_10[0x8];
7960 u8 event_sub_type[0x8];
7962 u8 reserved_at_20[0xe0];
7964 union mlx5_ifc_event_auto_bits event_data;
7966 u8 reserved_at_1e0[0x10];
7968 u8 reserved_at_1f8[0x7];
7973 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
7976 struct mlx5_ifc_cmd_queue_entry_bits {
7978 u8 reserved_at_8[0x18];
7980 u8 input_length[0x20];
7982 u8 input_mailbox_pointer_63_32[0x20];
7984 u8 input_mailbox_pointer_31_9[0x17];
7985 u8 reserved_at_77[0x9];
7987 u8 command_input_inline_data[16][0x8];
7989 u8 command_output_inline_data[16][0x8];
7991 u8 output_mailbox_pointer_63_32[0x20];
7993 u8 output_mailbox_pointer_31_9[0x17];
7994 u8 reserved_at_1b7[0x9];
7996 u8 output_length[0x20];
8000 u8 reserved_at_1f0[0x8];
8005 struct mlx5_ifc_cmd_out_bits {
8007 u8 reserved_at_8[0x18];
8011 u8 command_output[0x20];
8014 struct mlx5_ifc_cmd_in_bits {
8016 u8 reserved_at_10[0x10];
8018 u8 reserved_at_20[0x10];
8021 u8 command[0][0x20];
8024 struct mlx5_ifc_cmd_if_box_bits {
8025 u8 mailbox_data[512][0x8];
8027 u8 reserved_at_1000[0x180];
8029 u8 next_pointer_63_32[0x20];
8031 u8 next_pointer_31_10[0x16];
8032 u8 reserved_at_11b6[0xa];
8034 u8 block_number[0x20];
8036 u8 reserved_at_11e0[0x8];
8038 u8 ctrl_signature[0x8];
8042 struct mlx5_ifc_mtt_bits {
8043 u8 ptag_63_32[0x20];
8046 u8 reserved_at_38[0x6];
8051 struct mlx5_ifc_query_wol_rol_out_bits {
8053 u8 reserved_at_8[0x18];
8057 u8 reserved_at_40[0x10];
8061 u8 reserved_at_60[0x20];
8064 struct mlx5_ifc_query_wol_rol_in_bits {
8066 u8 reserved_at_10[0x10];
8068 u8 reserved_at_20[0x10];
8071 u8 reserved_at_40[0x40];
8074 struct mlx5_ifc_set_wol_rol_out_bits {
8076 u8 reserved_at_8[0x18];
8080 u8 reserved_at_40[0x40];
8083 struct mlx5_ifc_set_wol_rol_in_bits {
8085 u8 reserved_at_10[0x10];
8087 u8 reserved_at_20[0x10];
8090 u8 rol_mode_valid[0x1];
8091 u8 wol_mode_valid[0x1];
8092 u8 reserved_at_42[0xe];
8096 u8 reserved_at_60[0x20];
8100 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8101 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8102 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8106 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8107 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8108 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8112 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8113 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8114 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8115 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8116 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8117 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8118 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8119 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8120 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8121 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8122 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8125 struct mlx5_ifc_initial_seg_bits {
8126 u8 fw_rev_minor[0x10];
8127 u8 fw_rev_major[0x10];
8129 u8 cmd_interface_rev[0x10];
8130 u8 fw_rev_subminor[0x10];
8132 u8 reserved_at_40[0x40];
8134 u8 cmdq_phy_addr_63_32[0x20];
8136 u8 cmdq_phy_addr_31_12[0x14];
8137 u8 reserved_at_b4[0x2];
8138 u8 nic_interface[0x2];
8139 u8 log_cmdq_size[0x4];
8140 u8 log_cmdq_stride[0x4];
8142 u8 command_doorbell_vector[0x20];
8144 u8 reserved_at_e0[0xf00];
8146 u8 initializing[0x1];
8147 u8 reserved_at_fe1[0x4];
8148 u8 nic_interface_supported[0x3];
8149 u8 reserved_at_fe8[0x18];
8151 struct mlx5_ifc_health_buffer_bits health_buffer;
8153 u8 no_dram_nic_offset[0x20];
8155 u8 reserved_at_1220[0x6e40];
8157 u8 reserved_at_8060[0x1f];
8160 u8 health_syndrome[0x8];
8161 u8 health_counter[0x18];
8163 u8 reserved_at_80a0[0x17fc0];
8166 struct mlx5_ifc_mtpps_reg_bits {
8167 u8 reserved_at_0[0xc];
8168 u8 cap_number_of_pps_pins[0x4];
8169 u8 reserved_at_10[0x4];
8170 u8 cap_max_num_of_pps_in_pins[0x4];
8171 u8 reserved_at_18[0x4];
8172 u8 cap_max_num_of_pps_out_pins[0x4];
8174 u8 reserved_at_20[0x24];
8175 u8 cap_pin_3_mode[0x4];
8176 u8 reserved_at_48[0x4];
8177 u8 cap_pin_2_mode[0x4];
8178 u8 reserved_at_50[0x4];
8179 u8 cap_pin_1_mode[0x4];
8180 u8 reserved_at_58[0x4];
8181 u8 cap_pin_0_mode[0x4];
8183 u8 reserved_at_60[0x4];
8184 u8 cap_pin_7_mode[0x4];
8185 u8 reserved_at_68[0x4];
8186 u8 cap_pin_6_mode[0x4];
8187 u8 reserved_at_70[0x4];
8188 u8 cap_pin_5_mode[0x4];
8189 u8 reserved_at_78[0x4];
8190 u8 cap_pin_4_mode[0x4];
8192 u8 reserved_at_80[0x80];
8195 u8 reserved_at_101[0xb];
8197 u8 reserved_at_110[0x4];
8201 u8 reserved_at_120[0x20];
8203 u8 time_stamp[0x40];
8205 u8 out_pulse_duration[0x10];
8206 u8 out_periodic_adjustment[0x10];
8208 u8 reserved_at_1a0[0x60];
8211 struct mlx5_ifc_mtppse_reg_bits {
8212 u8 reserved_at_0[0x18];
8215 u8 reserved_at_21[0x1b];
8216 u8 event_generation_mode[0x4];
8217 u8 reserved_at_40[0x40];
8220 struct mlx5_ifc_mcqi_cap_bits {
8221 u8 supported_info_bitmask[0x20];
8223 u8 component_size[0x20];
8225 u8 max_component_size[0x20];
8227 u8 log_mcda_word_size[0x4];
8228 u8 reserved_at_64[0xc];
8229 u8 mcda_max_write_size[0x10];
8232 u8 reserved_at_81[0x1];
8233 u8 match_chip_id[0x1];
8235 u8 check_user_timestamp[0x1];
8236 u8 match_base_guid_mac[0x1];
8237 u8 reserved_at_86[0x1a];
8240 struct mlx5_ifc_mcqi_reg_bits {
8241 u8 read_pending_component[0x1];
8242 u8 reserved_at_1[0xf];
8243 u8 component_index[0x10];
8245 u8 reserved_at_20[0x20];
8247 u8 reserved_at_40[0x1b];
8254 u8 reserved_at_a0[0x10];
8260 struct mlx5_ifc_mcc_reg_bits {
8261 u8 reserved_at_0[0x4];
8262 u8 time_elapsed_since_last_cmd[0xc];
8263 u8 reserved_at_10[0x8];
8264 u8 instruction[0x8];
8266 u8 reserved_at_20[0x10];
8267 u8 component_index[0x10];
8269 u8 reserved_at_40[0x8];
8270 u8 update_handle[0x18];
8272 u8 handle_owner_type[0x4];
8273 u8 handle_owner_host_id[0x4];
8274 u8 reserved_at_68[0x1];
8275 u8 control_progress[0x7];
8277 u8 reserved_at_78[0x4];
8278 u8 control_state[0x4];
8280 u8 component_size[0x20];
8282 u8 reserved_at_a0[0x60];
8285 struct mlx5_ifc_mcda_reg_bits {
8286 u8 reserved_at_0[0x8];
8287 u8 update_handle[0x18];
8291 u8 reserved_at_40[0x10];
8294 u8 reserved_at_60[0x20];
8299 union mlx5_ifc_ports_control_registers_document_bits {
8300 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8301 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8302 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8303 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8304 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8305 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8306 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8307 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8308 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8309 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8310 struct mlx5_ifc_paos_reg_bits paos_reg;
8311 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8312 struct mlx5_ifc_peir_reg_bits peir_reg;
8313 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8314 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8315 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8316 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8317 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8318 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8319 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8320 struct mlx5_ifc_plib_reg_bits plib_reg;
8321 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8322 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8323 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8324 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8325 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8326 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8327 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8328 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8329 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8330 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8331 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8332 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8333 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8334 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8335 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8336 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8337 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8338 struct mlx5_ifc_ptys_reg_bits ptys_reg;
8339 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8340 struct mlx5_ifc_pude_reg_bits pude_reg;
8341 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8342 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8343 struct mlx5_ifc_sltp_reg_bits sltp_reg;
8344 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8345 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8346 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8347 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8348 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8349 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8350 struct mlx5_ifc_mcc_reg_bits mcc_reg;
8351 struct mlx5_ifc_mcda_reg_bits mcda_reg;
8352 u8 reserved_at_0[0x60e0];
8355 union mlx5_ifc_debug_enhancements_document_bits {
8356 struct mlx5_ifc_health_buffer_bits health_buffer;
8357 u8 reserved_at_0[0x200];
8360 union mlx5_ifc_uplink_pci_interface_document_bits {
8361 struct mlx5_ifc_initial_seg_bits initial_seg;
8362 u8 reserved_at_0[0x20060];
8365 struct mlx5_ifc_set_flow_table_root_out_bits {
8367 u8 reserved_at_8[0x18];
8371 u8 reserved_at_40[0x40];
8374 struct mlx5_ifc_set_flow_table_root_in_bits {
8376 u8 reserved_at_10[0x10];
8378 u8 reserved_at_20[0x10];
8381 u8 other_vport[0x1];
8382 u8 reserved_at_41[0xf];
8383 u8 vport_number[0x10];
8385 u8 reserved_at_60[0x20];
8388 u8 reserved_at_88[0x18];
8390 u8 reserved_at_a0[0x8];
8393 u8 reserved_at_c0[0x8];
8394 u8 underlay_qpn[0x18];
8395 u8 reserved_at_e0[0x120];
8399 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8400 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8403 struct mlx5_ifc_modify_flow_table_out_bits {
8405 u8 reserved_at_8[0x18];
8409 u8 reserved_at_40[0x40];
8412 struct mlx5_ifc_modify_flow_table_in_bits {
8414 u8 reserved_at_10[0x10];
8416 u8 reserved_at_20[0x10];
8419 u8 other_vport[0x1];
8420 u8 reserved_at_41[0xf];
8421 u8 vport_number[0x10];
8423 u8 reserved_at_60[0x10];
8424 u8 modify_field_select[0x10];
8427 u8 reserved_at_88[0x18];
8429 u8 reserved_at_a0[0x8];
8432 struct mlx5_ifc_flow_table_context_bits flow_table_context;
8435 struct mlx5_ifc_ets_tcn_config_reg_bits {
8439 u8 reserved_at_3[0x9];
8441 u8 reserved_at_10[0x9];
8442 u8 bw_allocation[0x7];
8444 u8 reserved_at_20[0xc];
8445 u8 max_bw_units[0x4];
8446 u8 reserved_at_30[0x8];
8447 u8 max_bw_value[0x8];
8450 struct mlx5_ifc_ets_global_config_reg_bits {
8451 u8 reserved_at_0[0x2];
8453 u8 reserved_at_3[0x1d];
8455 u8 reserved_at_20[0xc];
8456 u8 max_bw_units[0x4];
8457 u8 reserved_at_30[0x8];
8458 u8 max_bw_value[0x8];
8461 struct mlx5_ifc_qetc_reg_bits {
8462 u8 reserved_at_0[0x8];
8463 u8 port_number[0x8];
8464 u8 reserved_at_10[0x30];
8466 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8467 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8470 struct mlx5_ifc_qtct_reg_bits {
8471 u8 reserved_at_0[0x8];
8472 u8 port_number[0x8];
8473 u8 reserved_at_10[0xd];
8476 u8 reserved_at_20[0x1d];
8480 struct mlx5_ifc_mcia_reg_bits {
8482 u8 reserved_at_1[0x7];
8484 u8 reserved_at_10[0x8];
8487 u8 i2c_device_address[0x8];
8488 u8 page_number[0x8];
8489 u8 device_address[0x10];
8491 u8 reserved_at_40[0x10];
8494 u8 reserved_at_60[0x20];
8510 struct mlx5_ifc_dcbx_param_bits {
8511 u8 dcbx_cee_cap[0x1];
8512 u8 dcbx_ieee_cap[0x1];
8513 u8 dcbx_standby_cap[0x1];
8514 u8 reserved_at_0[0x5];
8515 u8 port_number[0x8];
8516 u8 reserved_at_10[0xa];
8517 u8 max_application_table_size[6];
8518 u8 reserved_at_20[0x15];
8519 u8 version_oper[0x3];
8520 u8 reserved_at_38[5];
8521 u8 version_admin[0x3];
8522 u8 willing_admin[0x1];
8523 u8 reserved_at_41[0x3];
8524 u8 pfc_cap_oper[0x4];
8525 u8 reserved_at_48[0x4];
8526 u8 pfc_cap_admin[0x4];
8527 u8 reserved_at_50[0x4];
8528 u8 num_of_tc_oper[0x4];
8529 u8 reserved_at_58[0x4];
8530 u8 num_of_tc_admin[0x4];
8531 u8 remote_willing[0x1];
8532 u8 reserved_at_61[3];
8533 u8 remote_pfc_cap[4];
8534 u8 reserved_at_68[0x14];
8535 u8 remote_num_of_tc[0x4];
8536 u8 reserved_at_80[0x18];
8538 u8 reserved_at_a0[0x160];
8541 struct mlx5_ifc_lagc_bits {
8542 u8 reserved_at_0[0x1d];
8545 u8 reserved_at_20[0x14];
8546 u8 tx_remap_affinity_2[0x4];
8547 u8 reserved_at_38[0x4];
8548 u8 tx_remap_affinity_1[0x4];
8551 struct mlx5_ifc_create_lag_out_bits {
8553 u8 reserved_at_8[0x18];
8557 u8 reserved_at_40[0x40];
8560 struct mlx5_ifc_create_lag_in_bits {
8562 u8 reserved_at_10[0x10];
8564 u8 reserved_at_20[0x10];
8567 struct mlx5_ifc_lagc_bits ctx;
8570 struct mlx5_ifc_modify_lag_out_bits {
8572 u8 reserved_at_8[0x18];
8576 u8 reserved_at_40[0x40];
8579 struct mlx5_ifc_modify_lag_in_bits {
8581 u8 reserved_at_10[0x10];
8583 u8 reserved_at_20[0x10];
8586 u8 reserved_at_40[0x20];
8587 u8 field_select[0x20];
8589 struct mlx5_ifc_lagc_bits ctx;
8592 struct mlx5_ifc_query_lag_out_bits {
8594 u8 reserved_at_8[0x18];
8598 u8 reserved_at_40[0x40];
8600 struct mlx5_ifc_lagc_bits ctx;
8603 struct mlx5_ifc_query_lag_in_bits {
8605 u8 reserved_at_10[0x10];
8607 u8 reserved_at_20[0x10];
8610 u8 reserved_at_40[0x40];
8613 struct mlx5_ifc_destroy_lag_out_bits {
8615 u8 reserved_at_8[0x18];
8619 u8 reserved_at_40[0x40];
8622 struct mlx5_ifc_destroy_lag_in_bits {
8624 u8 reserved_at_10[0x10];
8626 u8 reserved_at_20[0x10];
8629 u8 reserved_at_40[0x40];
8632 struct mlx5_ifc_create_vport_lag_out_bits {
8634 u8 reserved_at_8[0x18];
8638 u8 reserved_at_40[0x40];
8641 struct mlx5_ifc_create_vport_lag_in_bits {
8643 u8 reserved_at_10[0x10];
8645 u8 reserved_at_20[0x10];
8648 u8 reserved_at_40[0x40];
8651 struct mlx5_ifc_destroy_vport_lag_out_bits {
8653 u8 reserved_at_8[0x18];
8657 u8 reserved_at_40[0x40];
8660 struct mlx5_ifc_destroy_vport_lag_in_bits {
8662 u8 reserved_at_10[0x10];
8664 u8 reserved_at_20[0x10];
8667 u8 reserved_at_40[0x40];
8670 #endif /* MLX5_IFC_H */