2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/xarray.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
49 #include <linux/notifier.h>
50 #include <linux/refcount.h>
51 #include <linux/auxiliary_bus.h>
53 #include <linux/mlx5/device.h>
54 #include <linux/mlx5/doorbell.h>
55 #include <linux/mlx5/eq.h>
56 #include <linux/timecounter.h>
57 #include <linux/ptp_clock_kernel.h>
58 #include <net/devlink.h>
60 #define MLX5_ADEV_NAME "mlx5_core"
63 MLX5_BOARD_ID_LEN = 64,
67 /* one minute for the sake of bringup. Generally, commands must always
68 * complete and we may need to increase this timeout value
70 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000,
71 MLX5_CMD_WQ_MAX_NAME = 32,
77 CMD_STATUS_SUCCESS = 0,
83 MLX5_SQP_IEEE_1588 = 2,
85 MLX5_SQP_SYNC_UMR = 4,
93 MLX5_ATOMIC_MODE_OFFSET = 16,
94 MLX5_ATOMIC_MODE_IB_COMP = 1,
95 MLX5_ATOMIC_MODE_CX = 2,
96 MLX5_ATOMIC_MODE_8B = 3,
97 MLX5_ATOMIC_MODE_16B = 4,
98 MLX5_ATOMIC_MODE_32B = 5,
99 MLX5_ATOMIC_MODE_64B = 6,
100 MLX5_ATOMIC_MODE_128B = 7,
101 MLX5_ATOMIC_MODE_256B = 8,
105 MLX5_REG_QPTS = 0x4002,
106 MLX5_REG_QETCR = 0x4005,
107 MLX5_REG_QTCT = 0x400a,
108 MLX5_REG_QPDPM = 0x4013,
109 MLX5_REG_QCAM = 0x4019,
110 MLX5_REG_DCBX_PARAM = 0x4020,
111 MLX5_REG_DCBX_APP = 0x4021,
112 MLX5_REG_FPGA_CAP = 0x4022,
113 MLX5_REG_FPGA_CTRL = 0x4023,
114 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
115 MLX5_REG_CORE_DUMP = 0x402e,
116 MLX5_REG_PCAP = 0x5001,
117 MLX5_REG_PMTU = 0x5003,
118 MLX5_REG_PTYS = 0x5004,
119 MLX5_REG_PAOS = 0x5006,
120 MLX5_REG_PFCC = 0x5007,
121 MLX5_REG_PPCNT = 0x5008,
122 MLX5_REG_PPTB = 0x500b,
123 MLX5_REG_PBMC = 0x500c,
124 MLX5_REG_PMAOS = 0x5012,
125 MLX5_REG_PUDE = 0x5009,
126 MLX5_REG_PMPE = 0x5010,
127 MLX5_REG_PELC = 0x500e,
128 MLX5_REG_PVLC = 0x500f,
129 MLX5_REG_PCMR = 0x5041,
130 MLX5_REG_PMLP = 0x5002,
131 MLX5_REG_PPLM = 0x5023,
132 MLX5_REG_PCAM = 0x507f,
133 MLX5_REG_NODE_DESC = 0x6001,
134 MLX5_REG_HOST_ENDIANNESS = 0x7004,
135 MLX5_REG_MCIA = 0x9014,
136 MLX5_REG_MFRL = 0x9028,
137 MLX5_REG_MLCR = 0x902b,
138 MLX5_REG_MTRC_CAP = 0x9040,
139 MLX5_REG_MTRC_CONF = 0x9041,
140 MLX5_REG_MTRC_STDB = 0x9042,
141 MLX5_REG_MTRC_CTRL = 0x9043,
142 MLX5_REG_MPEIN = 0x9050,
143 MLX5_REG_MPCNT = 0x9051,
144 MLX5_REG_MTPPS = 0x9053,
145 MLX5_REG_MTPPSE = 0x9054,
146 MLX5_REG_MTUTC = 0x9055,
147 MLX5_REG_MPEGC = 0x9056,
148 MLX5_REG_MCQS = 0x9060,
149 MLX5_REG_MCQI = 0x9061,
150 MLX5_REG_MCC = 0x9062,
151 MLX5_REG_MCDA = 0x9063,
152 MLX5_REG_MCAM = 0x907f,
153 MLX5_REG_MIRC = 0x9162,
154 MLX5_REG_SBCAM = 0xB01F,
155 MLX5_REG_RESOURCE_DUMP = 0xC000,
158 enum mlx5_qpts_trust_state {
159 MLX5_QPTS_TRUST_PCP = 1,
160 MLX5_QPTS_TRUST_DSCP = 2,
163 enum mlx5_dcbx_oper_mode {
164 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
165 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
169 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
170 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
171 MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
172 MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
175 enum mlx5_page_fault_resume_flags {
176 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
177 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
178 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
179 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
188 enum port_state_policy {
189 MLX5_POLICY_DOWN = 0,
191 MLX5_POLICY_FOLLOW = 2,
192 MLX5_POLICY_INVALID = 0xffffffff
195 enum mlx5_coredev_type {
201 struct mlx5_field_desc {
205 struct mlx5_rsc_debug {
206 struct mlx5_core_dev *dev;
208 enum dbg_rsc_type type;
210 struct mlx5_field_desc fields[];
213 enum mlx5_dev_event {
214 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
215 MLX5_DEV_EVENT_PORT_AFFINITY = 129,
218 enum mlx5_port_status {
223 enum mlx5_cmdif_state {
224 MLX5_CMDIF_STATE_UNINITIALIZED,
226 MLX5_CMDIF_STATE_DOWN,
229 struct mlx5_cmd_first {
233 struct mlx5_cmd_msg {
234 struct list_head list;
235 struct cmd_msg_cache *parent;
237 struct mlx5_cmd_first first;
238 struct mlx5_cmd_mailbox *next;
241 struct mlx5_cmd_debug {
242 struct dentry *dbg_root;
250 struct cmd_msg_cache {
251 /* protect block chain allocations
254 struct list_head head;
255 unsigned int max_inbox_size;
256 unsigned int num_ent;
260 MLX5_NUM_COMMAND_CACHES = 5,
263 struct mlx5_cmd_stats {
267 /* protect command average calculations */
274 enum mlx5_cmdif_state state;
276 dma_addr_t alloc_dma;
287 /* protect command queue allocations
289 spinlock_t alloc_lock;
291 /* protect token allocations
293 spinlock_t token_lock;
295 unsigned long bitmask;
296 char wq_name[MLX5_CMD_WQ_MAX_NAME];
297 struct workqueue_struct *wq;
298 struct semaphore sem;
299 struct semaphore pages_sem;
302 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
303 struct dma_pool *pool;
304 struct mlx5_cmd_debug dbg;
305 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
306 int checksum_disabled;
307 struct mlx5_cmd_stats *stats;
310 struct mlx5_cmd_mailbox {
313 struct mlx5_cmd_mailbox *next;
316 struct mlx5_buf_list {
321 struct mlx5_frag_buf {
322 struct mlx5_buf_list *frags;
328 struct mlx5_frag_buf_ctrl {
329 struct mlx5_buf_list *frags;
338 struct mlx5_core_psv {
350 struct mlx5_core_sig_ctx {
351 struct mlx5_core_psv psv_memory;
352 struct mlx5_core_psv psv_wire;
353 struct ib_sig_err err_item;
354 bool sig_status_checked;
362 MLX5_MKEY_INDIRECT_DEVX,
365 struct mlx5_core_mkey {
371 struct wait_queue_head wait;
375 #define MLX5_24BIT_MASK ((1 << 24) - 1)
378 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
379 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
380 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
384 MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT,
387 struct mlx5_core_rsc_common {
388 enum mlx5_res_type res;
390 struct completion free;
393 struct mlx5_uars_page {
397 struct list_head list;
399 unsigned long *reg_bitmap; /* for non fast path bf regs */
400 unsigned long *fp_bitmap;
401 unsigned int reg_avail;
402 unsigned int fp_avail;
403 struct kref ref_count;
404 struct mlx5_core_dev *mdev;
407 struct mlx5_bfreg_head {
408 /* protect blue flame registers allocations */
410 struct list_head list;
413 struct mlx5_bfreg_data {
414 struct mlx5_bfreg_head reg_head;
415 struct mlx5_bfreg_head wc_head;
418 struct mlx5_sq_bfreg {
420 struct mlx5_uars_page *up;
426 struct mlx5_core_health {
427 struct health_buffer __iomem *health;
428 __be32 __iomem *health_counter;
429 struct timer_list timer;
435 /* wq spinlock to synchronize draining */
437 struct workqueue_struct *wq;
439 struct work_struct fatal_report_work;
440 struct work_struct report_work;
441 struct delayed_work recover_work;
442 struct devlink_health_reporter *fw_reporter;
443 struct devlink_health_reporter *fw_fatal_reporter;
446 struct mlx5_qp_table {
447 struct notifier_block nb;
449 /* protect radix tree
452 struct radix_tree_root tree;
455 struct mlx5_vf_context {
459 /* Valid bits are used to validate administrative guid only.
460 * Enabled after ndo_set_vf_guid
462 u8 port_guid_valid:1;
463 u8 node_guid_valid:1;
464 enum port_state_policy policy;
467 struct mlx5_core_sriov {
468 struct mlx5_vf_context *vfs_ctx;
473 struct mlx5_fc_pool {
474 struct mlx5_core_dev *dev;
475 struct mutex pool_lock; /* protects pool lists */
476 struct list_head fully_used;
477 struct list_head partially_used;
478 struct list_head unused;
484 struct mlx5_fc_stats {
485 spinlock_t counters_idr_lock; /* protects counters_idr */
486 struct idr counters_idr;
487 struct list_head counters;
488 struct llist_head addlist;
489 struct llist_head dellist;
491 struct workqueue_struct *wq;
492 struct delayed_work work;
493 unsigned long next_query;
494 unsigned long sampling_interval; /* jiffies */
496 struct mlx5_fc_pool fc_pool;
504 struct mlx5_fw_reset;
505 struct mlx5_eq_table;
506 struct mlx5_irq_table;
507 struct mlx5_vhca_state_notifier;
508 struct mlx5_sf_dev_table;
509 struct mlx5_sf_hw_table;
510 struct mlx5_sf_table;
512 struct mlx5_rate_limit {
518 struct mlx5_rl_entry {
519 u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
526 struct mlx5_rl_table {
527 /* protect rate limit table */
528 struct mutex rl_lock;
532 struct mlx5_rl_entry *rl_entry;
535 struct mlx5_core_roce {
536 struct mlx5_flow_table *ft;
537 struct mlx5_flow_group *fg;
538 struct mlx5_flow_handle *allow_rule;
542 MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
543 MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
547 struct auxiliary_device adev;
548 struct mlx5_core_dev *mdev;
553 /* IRQ table valid only for real pci devices PF or VF */
554 struct mlx5_irq_table *irq_table;
555 struct mlx5_eq_table *eq_table;
558 struct mlx5_nb pg_nb;
559 struct workqueue_struct *pg_wq;
560 struct xarray page_root_xa;
563 struct list_head free_list;
567 struct mlx5_core_health health;
568 struct list_head traps;
570 /* start: qp staff */
571 struct dentry *qp_debugfs;
572 struct dentry *eq_debugfs;
573 struct dentry *cq_debugfs;
574 struct dentry *cmdif_debugfs;
577 /* start: alloc staff */
578 /* protect buffer alocation according to numa node */
579 struct mutex alloc_mutex;
582 struct mutex pgdir_mutex;
583 struct list_head pgdir_list;
584 /* end: alloc staff */
585 struct dentry *dbg_root;
587 struct list_head ctx_list;
589 struct mlx5_adev **adev;
591 struct mlx5_events *events;
593 struct mlx5_flow_steering *steering;
594 struct mlx5_mpfs *mpfs;
595 struct mlx5_eswitch *eswitch;
596 struct mlx5_core_sriov sriov;
597 struct mlx5_lag *lag;
599 struct mlx5_devcom *devcom;
600 struct mlx5_fw_reset *fw_reset;
601 struct mlx5_core_roce roce;
602 struct mlx5_fc_stats fc_stats;
603 struct mlx5_rl_table rl_table;
605 struct mlx5_bfreg_data bfregs;
606 struct mlx5_uars_page *uar;
607 #ifdef CONFIG_MLX5_SF
608 struct mlx5_vhca_state_notifier *vhca_state_notifier;
609 struct mlx5_sf_dev_table *sf_dev_table;
610 struct mlx5_core_dev *parent_mdev;
612 #ifdef CONFIG_MLX5_SF_MANAGER
613 struct mlx5_sf_hw_table *sf_hw_table;
614 struct mlx5_sf_table *sf_table;
618 enum mlx5_device_state {
619 MLX5_DEVICE_STATE_UNINITIALIZED,
620 MLX5_DEVICE_STATE_UP,
621 MLX5_DEVICE_STATE_INTERNAL_ERROR,
624 enum mlx5_interface_state {
625 MLX5_INTERFACE_STATE_UP = BIT(0),
628 enum mlx5_pci_status {
629 MLX5_PCI_STATUS_DISABLED,
630 MLX5_PCI_STATUS_ENABLED,
633 enum mlx5_pagefault_type_flags {
634 MLX5_PFAULT_REQUESTOR = 1 << 0,
635 MLX5_PFAULT_WRITE = 1 << 1,
636 MLX5_PFAULT_RDMA = 1 << 2,
640 /* protects tirs list changes while tirs refresh */
641 struct mutex list_lock;
642 struct list_head tirs_list;
646 struct mlx5e_resources {
649 struct mlx5_core_mkey mkey;
650 struct mlx5_sq_bfreg bfreg;
653 enum mlx5_sw_icm_type {
654 MLX5_SW_ICM_TYPE_STEERING,
655 MLX5_SW_ICM_TYPE_HEADER_MODIFY,
658 #define MLX5_MAX_RESERVED_GIDS 8
660 struct mlx5_rsvd_gids {
666 #define MAX_PIN_NUM 8
668 u8 pin_caps[MAX_PIN_NUM];
669 struct work_struct out_work;
670 u64 start[MAX_PIN_NUM];
675 struct cyclecounter cycles;
676 struct timecounter tc;
678 unsigned long overflow_period;
679 struct delayed_work overflow_work;
683 struct mlx5_nb pps_nb;
685 struct hwtstamp_config hwtstamp_config;
686 struct ptp_clock *ptp;
687 struct ptp_clock_info ptp_info;
688 struct mlx5_pps pps_info;
689 struct mlx5_timer timer;
693 struct mlx5_fw_tracer;
698 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
699 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
701 struct mlx5_core_dev {
702 struct device *device;
703 enum mlx5_coredev_type coredev_type;
704 struct pci_dev *pdev;
706 struct mutex pci_status_mutex;
707 enum mlx5_pci_status pci_status;
709 char board_id[MLX5_BOARD_ID_LEN];
712 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
713 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
714 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
715 u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
716 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
717 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
721 phys_addr_t iseg_base;
722 struct mlx5_init_seg __iomem *iseg;
723 phys_addr_t bar_addr;
724 enum mlx5_device_state state;
725 /* sync interface state */
726 struct mutex intf_state_mutex;
727 unsigned long intf_state;
728 struct mlx5_priv priv;
729 struct mlx5_profile *profile;
731 struct mlx5e_resources mlx5e_res;
733 struct mlx5_vxlan *vxlan;
734 struct mlx5_geneve *geneve;
736 struct mlx5_rsvd_gids reserved_gids;
739 #ifdef CONFIG_MLX5_FPGA
740 struct mlx5_fpga_device *fpga;
742 #ifdef CONFIG_MLX5_ACCEL
743 const struct mlx5_accel_ipsec_ops *ipsec_ops;
745 struct mlx5_clock clock;
746 struct mlx5_ib_clock_info *clock_info;
747 struct mlx5_fw_tracer *tracer;
748 struct mlx5_rsc_dump *rsc_dump;
750 struct mlx5_hv_vhca *hv_vhca;
756 struct mlx5_db_pgdir *pgdir;
757 struct mlx5_ib_user_db_page *user_page;
764 MLX5_COMP_EQ_SIZE = 1024,
768 MLX5_PTYS_IB = 1 << 0,
769 MLX5_PTYS_EN = 1 << 2,
772 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
775 MLX5_CMD_ENT_STATE_PENDING_COMP,
778 struct mlx5_cmd_work_ent {
780 struct mlx5_cmd_msg *in;
781 struct mlx5_cmd_msg *out;
784 mlx5_cmd_cbk_t callback;
785 struct delayed_work cb_timeout_work;
788 struct completion handling;
789 struct completion done;
790 struct mlx5_cmd *cmd;
791 struct work_struct work;
792 struct mlx5_cmd_layout *lay;
801 /* Track the max comp handlers */
810 enum phy_port_state {
814 struct mlx5_hca_vport_context {
819 enum port_state_policy policy;
820 enum phy_port_state phys_state;
821 enum ib_port_state vport_state;
822 u8 port_physical_state;
831 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
836 u16 qkey_violation_counter;
837 u16 pkey_violation_counter;
841 static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset)
843 return buf->frags->buf + offset;
846 #define STRUCT_FIELD(header, field) \
847 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
848 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
850 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
852 return pci_get_drvdata(pdev);
855 extern struct dentry *mlx5_debugfs_root;
857 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
859 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
862 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
864 return ioread32be(&dev->iseg->fw_rev) >> 16;
867 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
869 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
872 static inline u32 mlx5_base_mkey(const u32 key)
874 return key & 0xffffff00u;
877 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
878 u8 log_stride, u8 log_sz,
880 struct mlx5_frag_buf_ctrl *fbc)
883 fbc->log_stride = log_stride;
884 fbc->log_sz = log_sz;
885 fbc->sz_m1 = (1 << fbc->log_sz) - 1;
886 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
887 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1;
888 fbc->strides_offset = strides_offset;
891 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
892 u8 log_stride, u8 log_sz,
893 struct mlx5_frag_buf_ctrl *fbc)
895 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
898 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
903 ix += fbc->strides_offset;
904 frag = ix >> fbc->log_frag_strides;
906 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
910 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
912 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
914 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
918 CMD_ALLOWED_OPCODE_ALL,
921 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
922 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
923 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
925 struct mlx5_async_ctx {
926 struct mlx5_core_dev *dev;
927 atomic_t num_inflight;
928 struct wait_queue_head wait;
931 struct mlx5_async_work;
933 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
935 struct mlx5_async_work {
936 struct mlx5_async_ctx *ctx;
937 mlx5_async_cbk_t user_callback;
940 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
941 struct mlx5_async_ctx *ctx);
942 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
943 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
944 void *out, int out_size, mlx5_async_cbk_t callback,
945 struct mlx5_async_work *work);
947 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
950 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out) \
952 mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out, \
953 MLX5_ST_SZ_BYTES(ifc_cmd##_out)); \
956 #define mlx5_cmd_exec_in(dev, ifc_cmd, in) \
958 u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {}; \
959 mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out); \
962 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
963 void *out, int out_size);
964 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
965 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
967 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
968 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
969 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
970 void mlx5_health_flush(struct mlx5_core_dev *dev);
971 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
972 int mlx5_health_init(struct mlx5_core_dev *dev);
973 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
974 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
975 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
976 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
977 int mlx5_buf_alloc(struct mlx5_core_dev *dev,
978 int size, struct mlx5_frag_buf *buf);
979 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
980 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
981 struct mlx5_frag_buf *buf, int node);
982 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
983 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
984 gfp_t flags, int npages);
985 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
986 struct mlx5_cmd_mailbox *head);
987 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
988 struct mlx5_core_mkey *mkey,
990 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
991 struct mlx5_core_mkey *mkey);
992 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
993 u32 *out, int outlen);
994 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
995 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
996 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
997 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
998 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
999 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1000 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1001 s32 npages, bool ec_function);
1002 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1003 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1004 void mlx5_register_debugfs(void);
1005 void mlx5_unregister_debugfs(void);
1007 void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas);
1008 void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
1009 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1010 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
1011 unsigned int *irqn);
1012 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1013 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1015 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1016 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1017 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1018 int size_in, void *data_out, int size_out,
1019 u16 reg_num, int arg, int write);
1021 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1022 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1024 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1026 const char *mlx5_command_str(int command);
1027 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1028 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1029 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1030 int npsvs, u32 *sig_index);
1031 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1032 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1033 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1034 struct mlx5_odp_caps *odp_caps);
1035 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1036 u8 port_num, void *out, size_t sz);
1038 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1039 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1040 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1041 struct mlx5_rate_limit *rl);
1042 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1043 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1044 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1045 bool dedicated_entry, u16 *index);
1046 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1047 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1048 struct mlx5_rate_limit *rl_1);
1049 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1050 bool map_wc, bool fast_path);
1051 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1053 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev);
1055 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector);
1056 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1057 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1058 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1059 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1061 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1066 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1068 return mkey_idx << 8;
1071 static inline u8 mlx5_mkey_variant(u32 mkey)
1077 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
1078 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
1082 MR_CACHE_LAST_STD_ENTRY = 20,
1083 MLX5_IMR_MTT_CACHE_ENTRY,
1084 MLX5_IMR_KSM_CACHE_ENTRY,
1085 MAX_MR_CACHE_ENTRIES
1088 /* Async-atomic event notifier used by mlx5 core to forward FW
1089 * evetns recived from event queue to mlx5 consumers.
1090 * Optimise event queue dipatching.
1092 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1093 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1095 /* Async-atomic event notifier used for forwarding
1096 * evetns from the event queue into the to mlx5 events dispatcher,
1097 * eswitch, clock and others.
1099 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1100 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1102 /* Blocking event notifier used to forward SW events, used for slow path */
1103 int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1104 int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1105 int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event,
1108 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1110 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1111 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1112 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1113 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1114 bool mlx5_lag_is_multipath(struct mlx5_core_dev *dev);
1115 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1116 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1117 u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1118 struct net_device *slave);
1119 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1123 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1124 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1125 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1126 u64 length, u32 log_alignment, u16 uid,
1127 phys_addr_t *addr, u32 *obj_id);
1128 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1129 u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1131 #ifdef CONFIG_MLX5_CORE_IPOIB
1132 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1133 struct ib_device *ibdev,
1135 void (*setup)(struct net_device *));
1136 #endif /* CONFIG_MLX5_CORE_IPOIB */
1137 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1138 struct ib_device *device,
1139 struct rdma_netdev_alloc_params *params);
1141 struct mlx5_profile {
1147 } mr_cache[MAX_MR_CACHE_ENTRIES];
1151 MLX5_PCI_DEV_IS_VF = 1 << 0,
1154 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1156 return dev->coredev_type == MLX5_COREDEV_PF;
1159 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1161 return dev->coredev_type == MLX5_COREDEV_VF;
1164 static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1166 return dev->caps.embedded_cpu;
1170 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1172 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1175 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1177 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1180 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1182 return dev->priv.sriov.max_vfs;
1185 static inline int mlx5_get_gid_table_len(u16 param)
1188 pr_warn("gid table length is zero\n");
1192 return 8 * (1 << param);
1195 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1197 return !!(dev->priv.rl_table.max_size);
1200 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1202 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1203 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1206 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1208 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1211 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1213 return mlx5_core_is_mp_slave(dev) ||
1214 mlx5_core_is_mp_master(dev);
1217 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1219 if (!mlx5_core_mp_enabled(dev))
1222 return MLX5_CAP_GEN(dev, native_port_num);
1226 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1229 static inline bool mlx5_is_roce_enabled(struct mlx5_core_dev *dev)
1231 struct devlink *devlink = priv_to_devlink(dev);
1232 union devlink_param_value val;
1234 devlink_param_driverinit_value_get(devlink,
1235 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
1240 #endif /* MLX5_DRIVER_H */