4 #include <linux/device.h>
7 #include <linux/jiffies.h>
8 #include <linux/platform_device.h>
9 #include <linux/pm_runtime.h>
11 #define tmio_ioread8(addr) readb(addr)
12 #define tmio_ioread16(addr) readw(addr)
13 #define tmio_ioread16_rep(r, b, l) readsw(r, b, l)
14 #define tmio_ioread32(addr) \
15 (((u32) readw((addr))) | (((u32) readw((addr) + 2)) << 16))
17 #define tmio_iowrite8(val, addr) writeb((val), (addr))
18 #define tmio_iowrite16(val, addr) writew((val), (addr))
19 #define tmio_iowrite16_rep(r, b, l) writesw(r, b, l)
20 #define tmio_iowrite32(val, addr) \
22 writew((val), (addr)); \
23 writew((val) >> 16, (addr) + 2); \
27 #define CNF_CTL_BASE 0x10
28 #define CNF_INT_PIN 0x3d
29 #define CNF_STOP_CLK_CTL 0x40
30 #define CNF_GCLK_CTL 0x41
31 #define CNF_SD_CLK_MODE 0x42
32 #define CNF_PIN_STATUS 0x44
33 #define CNF_PWR_CTL_1 0x48
34 #define CNF_PWR_CTL_2 0x49
35 #define CNF_PWR_CTL_3 0x4a
36 #define CNF_CARD_DETECT_MODE 0x4c
37 #define CNF_SD_SLOT 0x50
38 #define CNF_EXT_GCLK_CTL_1 0xf0
39 #define CNF_EXT_GCLK_CTL_2 0xf1
40 #define CNF_EXT_GCLK_CTL_3 0xf9
41 #define CNF_SD_LED_EN_1 0xfa
42 #define CNF_SD_LED_EN_2 0xfe
44 #define SDCREN 0x2 /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/
46 #define sd_config_write8(base, shift, reg, val) \
47 tmio_iowrite8((val), (base) + ((reg) << (shift)))
48 #define sd_config_write16(base, shift, reg, val) \
49 tmio_iowrite16((val), (base) + ((reg) << (shift)))
50 #define sd_config_write32(base, shift, reg, val) \
52 tmio_iowrite16((val), (base) + ((reg) << (shift))); \
53 tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \
56 /* tmio MMC platform flags */
57 #define TMIO_MMC_WRPROTECT_DISABLE (1 << 0)
59 * Some controllers can support a 2-byte block size when the bus width
60 * is configured in 4-bit mode.
62 #define TMIO_MMC_BLKSZ_2BYTES (1 << 1)
64 * Some controllers can support SDIO IRQ signalling.
66 #define TMIO_MMC_SDIO_IRQ (1 << 2)
68 * Some controllers require waiting for the SD bus to become
69 * idle before writing to some registers.
71 #define TMIO_MMC_HAS_IDLE_WAIT (1 << 4)
73 * A GPIO is used for card hotplug detection. We need an extra flag for this,
74 * because 0 is a valid GPIO number too, and requiring users to specify
75 * cd_gpio < 0 to disable GPIO hotplug would break backwards compatibility.
77 #define TMIO_MMC_USE_GPIO_CD (1 << 5)
79 int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
80 int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
81 void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
82 void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);
93 * data for the MMC controller
95 struct tmio_mmc_data {
97 unsigned long capabilities;
98 unsigned long capabilities2;
100 u32 ocr_mask; /* available voltages */
101 struct tmio_mmc_dma *dma;
103 unsigned int cd_gpio;
104 void (*set_pwr)(struct platform_device *host, int state);
105 void (*set_clk_div)(struct platform_device *host, int state);
106 int (*get_cd)(struct platform_device *host);
107 int (*write16_hook)(struct tmio_mmc_host *host, int addr);
108 /* clock management callbacks */
109 int (*clk_enable)(struct platform_device *pdev, unsigned int *f);
110 void (*clk_disable)(struct platform_device *pdev);
114 * data for the NAND controller
116 struct tmio_nand_data {
117 struct nand_bbt_descr *badblock_pattern;
118 struct mtd_partition *partition;
119 unsigned int num_partitions;
122 #define FBIO_TMIO_ACC_WRITE 0x7C639300
123 #define FBIO_TMIO_ACC_SYNC 0x7C639301
125 struct tmio_fb_data {
126 int (*lcd_set_power)(struct platform_device *fb_dev,
128 int (*lcd_mode)(struct platform_device *fb_dev,
129 const struct fb_videomode *mode);
131 struct fb_videomode *modes;
133 /* in mm: size of screen */