include/linux/mfd/palmas.h

   1 /*
   2  * TI Palmas
   3  *
   4  * Copyright 2011 Texas Instruments Inc.
   5  *
   6  * Author: Graeme Gregory <gg@slimlogic.co.uk>
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under  the terms of the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the License, or (at your
  11  *  option) any later version.
  12  *
  13  */
  14
  15 #ifndef __LINUX_MFD_PALMAS_H
  16 #define __LINUX_MFD_PALMAS_H
  17
  18 #include <linux/usb/otg.h>
  19 #include <linux/leds.h>
  20 #include <linux/regmap.h>
  21 #include <linux/regulator/driver.h>
  22
  23 #define PALMAS_NUM_CLIENTS              3
  24
  25 struct palmas_pmic;
  26 struct palmas_gpadc;
  27 struct palmas_resource;
  28 struct palmas_usb;
  29
  30 struct palmas {
  31         struct device *dev;
  32
  33         struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
  34         struct regmap *regmap[PALMAS_NUM_CLIENTS];
  35
  36         /* Stored chip id */
  37         int id;
  38
  39         /* IRQ Data */
  40         int irq;
  41         u32 irq_mask;
  42         struct mutex irq_lock;
  43         struct regmap_irq_chip_data *irq_data;
  44
  45         /* Child Devices */
  46         struct palmas_pmic *pmic;
  47         struct palmas_gpadc *gpadc;
  48         struct palmas_resource *resource;
  49         struct palmas_usb *usb;
  50
  51         /* GPIO MUXing */
  52         u8 gpio_muxed;
  53         u8 led_muxed;
  54         u8 pwm_muxed;
  55 };
  56
  57 struct palmas_gpadc_platform_data {
  58         /* Channel 3 current source is only enabled during conversion */
  59         int ch3_current;
  60
  61         /* Channel 0 current source can be used for battery detection.
  62          * If used for battery detection this will cause a permanent current
  63          * consumption depending on current level set here.
  64          */
  65         int ch0_current;
  66
  67         /* default BAT_REMOVAL_DAT setting on device probe */
  68         int bat_removal;
  69
  70         /* Sets the START_POLARITY bit in the RT_CTRL register */
  71         int start_polarity;
  72 };
  73
  74 struct palmas_reg_init {
  75         /* warm_rest controls the voltage levels after a warm reset
  76          *
  77          * 0: reload default values from OTP on warm reset
  78          * 1: maintain voltage from VSEL on warm reset
  79          */
  80         int warm_reset;
  81
  82         /* roof_floor controls whether the regulator uses the i2c style
  83          * of DVS or uses the method where a GPIO or other control method is
  84          * attached to the NSLEEP/ENABLE1/ENABLE2 pins
  85          *
  86          * For SMPS
  87          *
  88          * 0: i2c selection of voltage
  89          * 1: pin selection of voltage.
  90          *
  91          * For LDO unused
  92          */
  93         int roof_floor;
  94
  95         /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
  96          * the data sheet.
  97          *
  98          * For SMPS
  99          *
 100          * 0: Off
 101          * 1: AUTO
 102          * 2: ECO
 103          * 3: Forced PWM
 104          *
 105          * For LDO
 106          *
 107          * 0: Off
 108          * 1: On
 109          */
 110         int mode_sleep;
 111
 112         /* tstep is the timestep loaded to the TSTEP register
 113          *
 114          * For SMPS
 115          *
 116          * 0: Jump (no slope control)
 117          * 1: 10mV/us
 118          * 2: 5mV/us
 119          * 3: 2.5mV/us
 120          *
 121          * For LDO unused
 122          */
 123         int tstep;
 124
 125         /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
 126          * register. Set this is the default voltage set in OTP needs
 127          * to be overridden.
 128          */
 129         u8 vsel;
 130
 131 };
 132
 133 enum palmas_regulators {
 134         /* SMPS regulators */
 135         PALMAS_REG_SMPS12,
 136         PALMAS_REG_SMPS123,
 137         PALMAS_REG_SMPS3,
 138         PALMAS_REG_SMPS45,
 139         PALMAS_REG_SMPS457,
 140         PALMAS_REG_SMPS6,
 141         PALMAS_REG_SMPS7,
 142         PALMAS_REG_SMPS8,
 143         PALMAS_REG_SMPS9,
 144         PALMAS_REG_SMPS10,
 145         /* LDO regulators */
 146         PALMAS_REG_LDO1,
 147         PALMAS_REG_LDO2,
 148         PALMAS_REG_LDO3,
 149         PALMAS_REG_LDO4,
 150         PALMAS_REG_LDO5,
 151         PALMAS_REG_LDO6,
 152         PALMAS_REG_LDO7,
 153         PALMAS_REG_LDO8,
 154         PALMAS_REG_LDO9,
 155         PALMAS_REG_LDOLN,
 156         PALMAS_REG_LDOUSB,
 157         /* External regulators */
 158         PALMAS_REG_REGEN1,
 159         PALMAS_REG_REGEN2,
 160         PALMAS_REG_REGEN3,
 161         PALMAS_REG_SYSEN1,
 162         PALMAS_REG_SYSEN2,
 163         /* Total number of regulators */
 164         PALMAS_NUM_REGS,
 165 };
 166
 167 struct palmas_pmic_platform_data {
 168         /* An array of pointers to regulator init data indexed by regulator
 169          * ID
 170          */
 171         struct regulator_init_data *reg_data[PALMAS_NUM_REGS];
 172
 173         /* An array of pointers to structures containing sleep mode and DVS
 174          * configuration for regulators indexed by ID
 175          */
 176         struct palmas_reg_init *reg_init[PALMAS_NUM_REGS];
 177
 178         /* use LDO6 for vibrator control */
 179         int ldo6_vibrator;
 180 };
 181
 182 struct palmas_usb_platform_data {
 183         /* Set this if platform wishes its own vbus control */
 184         int no_control_vbus;
 185
 186         /* Do we enable the wakeup comparator on probe */
 187         int wakeup;
 188 };
 189
 190 struct palmas_resource_platform_data {
 191         int regen1_mode_sleep;
 192         int regen2_mode_sleep;
 193         int sysen1_mode_sleep;
 194         int sysen2_mode_sleep;
 195
 196         /* bitfield to be loaded to NSLEEP_RES_ASSIGN */
 197         u8 nsleep_res;
 198         /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */
 199         u8 nsleep_smps;
 200         /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */
 201         u8 nsleep_ldo1;
 202         /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */
 203         u8 nsleep_ldo2;
 204
 205         /* bitfield to be loaded to ENABLE1_RES_ASSIGN */
 206         u8 enable1_res;
 207         /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */
 208         u8 enable1_smps;
 209         /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */
 210         u8 enable1_ldo1;
 211         /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */
 212         u8 enable1_ldo2;
 213
 214         /* bitfield to be loaded to ENABLE2_RES_ASSIGN */
 215         u8 enable2_res;
 216         /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */
 217         u8 enable2_smps;
 218         /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */
 219         u8 enable2_ldo1;
 220         /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */
 221         u8 enable2_ldo2;
 222 };
 223
 224 struct palmas_clk_platform_data {
 225         int clk32kg_mode_sleep;
 226         int clk32kgaudio_mode_sleep;
 227 };
 228
 229 struct palmas_platform_data {
 230         int gpio_base;
 231
 232         /* bit value to be loaded to the POWER_CTRL register */
 233         u8 power_ctrl;
 234
 235         /*
 236          * boolean to select if we want to configure muxing here
 237          * then the two value to load into the registers if true
 238          */
 239         int mux_from_pdata;
 240         u8 pad1, pad2;
 241
 242         struct palmas_pmic_platform_data *pmic_pdata;
 243         struct palmas_gpadc_platform_data *gpadc_pdata;
 244         struct palmas_usb_platform_data *usb_pdata;
 245         struct palmas_resource_platform_data *resource_pdata;
 246         struct palmas_clk_platform_data *clk_pdata;
 247 };
 248
 249 struct palmas_gpadc_calibration {
 250         s32 gain;
 251         s32 gain_error;
 252         s32 offset_error;
 253 };
 254
 255 struct palmas_gpadc {
 256         struct device *dev;
 257         struct palmas *palmas;
 258
 259         int ch3_current;
 260         int ch0_current;
 261
 262         int gpadc_force;
 263
 264         int bat_removal;
 265
 266         struct mutex reading_lock;
 267         struct completion irq_complete;
 268
 269         int eoc_sw_irq;
 270
 271         struct palmas_gpadc_calibration *palmas_cal_tbl;
 272
 273         int conv0_channel;
 274         int conv1_channel;
 275         int rt_channel;
 276 };
 277
 278 struct palmas_gpadc_result {
 279         s32 raw_code;
 280         s32 corrected_code;
 281         s32 result;
 282 };
 283
 284 #define PALMAS_MAX_CHANNELS 16
 285
 286 /* Define the palmas IRQ numbers */
 287 enum palmas_irqs {
 288         /* INT1 registers */
 289         PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
 290         PALMAS_PWRON_IRQ,
 291         PALMAS_LONG_PRESS_KEY_IRQ,
 292         PALMAS_RPWRON_IRQ,
 293         PALMAS_PWRDOWN_IRQ,
 294         PALMAS_HOTDIE_IRQ,
 295         PALMAS_VSYS_MON_IRQ,
 296         PALMAS_VBAT_MON_IRQ,
 297         /* INT2 registers */
 298         PALMAS_RTC_ALARM_IRQ,
 299         PALMAS_RTC_TIMER_IRQ,
 300         PALMAS_WDT_IRQ,
 301         PALMAS_BATREMOVAL_IRQ,
 302         PALMAS_RESET_IN_IRQ,
 303         PALMAS_FBI_BB_IRQ,
 304         PALMAS_SHORT_IRQ,
 305         PALMAS_VAC_ACOK_IRQ,
 306         /* INT3 registers */
 307         PALMAS_GPADC_AUTO_0_IRQ,
 308         PALMAS_GPADC_AUTO_1_IRQ,
 309         PALMAS_GPADC_EOC_SW_IRQ,
 310         PALMAS_GPADC_EOC_RT_IRQ,
 311         PALMAS_ID_OTG_IRQ,
 312         PALMAS_ID_IRQ,
 313         PALMAS_VBUS_OTG_IRQ,
 314         PALMAS_VBUS_IRQ,
 315         /* INT4 registers */
 316         PALMAS_GPIO_0_IRQ,
 317         PALMAS_GPIO_1_IRQ,
 318         PALMAS_GPIO_2_IRQ,
 319         PALMAS_GPIO_3_IRQ,
 320         PALMAS_GPIO_4_IRQ,
 321         PALMAS_GPIO_5_IRQ,
 322         PALMAS_GPIO_6_IRQ,
 323         PALMAS_GPIO_7_IRQ,
 324         /* Total Number IRQs */
 325         PALMAS_NUM_IRQ,
 326 };
 327
 328 struct palmas_pmic {
 329         struct palmas *palmas;
 330         struct device *dev;
 331         struct regulator_desc desc[PALMAS_NUM_REGS];
 332         struct regulator_dev *rdev[PALMAS_NUM_REGS];
 333         struct mutex mutex;
 334
 335         int smps123;
 336         int smps457;
 337
 338         int range[PALMAS_REG_SMPS10];
 339 };
 340
 341 struct palmas_resource {
 342         struct palmas *palmas;
 343         struct device *dev;
 344 };
 345
 346 struct palmas_usb {
 347         struct palmas *palmas;
 348         struct device *dev;
 349
 350         /* for vbus reporting with irqs disabled */
 351         spinlock_t lock;
 352
 353         struct regulator *vbus_reg;
 354
 355         /* used to set vbus, in atomic path */
 356         struct work_struct set_vbus_work;
 357
 358         int irq1;
 359         int irq2;
 360         int irq3;
 361         int irq4;
 362
 363         int vbus_enable;
 364
 365         u8 linkstat;
 366 };
 367
 368 #define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)
 369
 370 enum usb_irq_events {
 371         /* Wakeup events from INT3 */
 372         PALMAS_USB_ID_WAKEPUP,
 373         PALMAS_USB_VBUS_WAKEUP,
 374
 375         /* ID_OTG_EVENTS */
 376         PALMAS_USB_ID_GND,
 377         N_PALMAS_USB_ID_GND,
 378         PALMAS_USB_ID_C,
 379         N_PALMAS_USB_ID_C,
 380         PALMAS_USB_ID_B,
 381         N_PALMAS_USB_ID_B,
 382         PALMAS_USB_ID_A,
 383         N_PALMAS_USB_ID_A,
 384         PALMAS_USB_ID_FLOAT,
 385         N_PALMAS_USB_ID_FLOAT,
 386
 387         /* VBUS_OTG_EVENTS */
 388         PALMAS_USB_VB_SESS_END,
 389         N_PALMAS_USB_VB_SESS_END,
 390         PALMAS_USB_VB_SESS_VLD,
 391         N_PALMAS_USB_VB_SESS_VLD,
 392         PALMAS_USB_VA_SESS_VLD,
 393         N_PALMAS_USB_VA_SESS_VLD,
 394         PALMAS_USB_VA_VBUS_VLD,
 395         N_PALMAS_USB_VA_VBUS_VLD,
 396         PALMAS_USB_VADP_SNS,
 397         N_PALMAS_USB_VADP_SNS,
 398         PALMAS_USB_VADP_PRB,
 399         N_PALMAS_USB_VADP_PRB,
 400         PALMAS_USB_VOTG_SESS_VLD,
 401         N_PALMAS_USB_VOTG_SESS_VLD,
 402 };
 403
 404 /* defines so we can store the mux settings */
 405 #define PALMAS_GPIO_0_MUXED                                     (1 << 0)
 406 #define PALMAS_GPIO_1_MUXED                                     (1 << 1)
 407 #define PALMAS_GPIO_2_MUXED                                     (1 << 2)
 408 #define PALMAS_GPIO_3_MUXED                                     (1 << 3)
 409 #define PALMAS_GPIO_4_MUXED                                     (1 << 4)
 410 #define PALMAS_GPIO_5_MUXED                                     (1 << 5)
 411 #define PALMAS_GPIO_6_MUXED                                     (1 << 6)
 412 #define PALMAS_GPIO_7_MUXED                                     (1 << 7)
 413
 414 #define PALMAS_LED1_MUXED                                       (1 << 0)
 415 #define PALMAS_LED2_MUXED                                       (1 << 1)
 416
 417 #define PALMAS_PWM1_MUXED                                       (1 << 0)
 418 #define PALMAS_PWM2_MUXED                                       (1 << 1)
 419
 420 /* helper macro to get correct slave number */
 421 #define PALMAS_BASE_TO_SLAVE(x)         ((x >> 8) - 1)
 422 #define PALMAS_BASE_TO_REG(x, y)        ((x & 0xff) + y)
 423
 424 /* Base addresses of IP blocks in Palmas */
 425 #define PALMAS_SMPS_DVS_BASE                                    0x20
 426 #define PALMAS_RTC_BASE                                         0x100
 427 #define PALMAS_VALIDITY_BASE                                    0x118
 428 #define PALMAS_SMPS_BASE                                        0x120
 429 #define PALMAS_LDO_BASE                                         0x150
 430 #define PALMAS_DVFS_BASE                                        0x180
 431 #define PALMAS_PMU_CONTROL_BASE                                 0x1A0
 432 #define PALMAS_RESOURCE_BASE                                    0x1D4
 433 #define PALMAS_PU_PD_OD_BASE                                    0x1F4
 434 #define PALMAS_LED_BASE                                         0x200
 435 #define PALMAS_INTERRUPT_BASE                                   0x210
 436 #define PALMAS_USB_OTG_BASE                                     0x250
 437 #define PALMAS_VIBRATOR_BASE                                    0x270
 438 #define PALMAS_GPIO_BASE                                        0x280
 439 #define PALMAS_USB_BASE                                         0x290
 440 #define PALMAS_GPADC_BASE                                       0x2C0
 441 #define PALMAS_TRIM_GPADC_BASE                                  0x3CD
 442
 443 /* Registers for function RTC */
 444 #define PALMAS_SECONDS_REG                                      0x0
 445 #define PALMAS_MINUTES_REG                                      0x1
 446 #define PALMAS_HOURS_REG                                        0x2
 447 #define PALMAS_DAYS_REG                                         0x3
 448 #define PALMAS_MONTHS_REG                                       0x4
 449 #define PALMAS_YEARS_REG                                        0x5
 450 #define PALMAS_WEEKS_REG                                        0x6
 451 #define PALMAS_ALARM_SECONDS_REG                                0x8
 452 #define PALMAS_ALARM_MINUTES_REG                                0x9
 453 #define PALMAS_ALARM_HOURS_REG                                  0xA
 454 #define PALMAS_ALARM_DAYS_REG                                   0xB
 455 #define PALMAS_ALARM_MONTHS_REG                                 0xC
 456 #define PALMAS_ALARM_YEARS_REG                                  0xD
 457 #define PALMAS_RTC_CTRL_REG                                     0x10
 458 #define PALMAS_RTC_STATUS_REG                                   0x11
 459 #define PALMAS_RTC_INTERRUPTS_REG                               0x12
 460 #define PALMAS_RTC_COMP_LSB_REG                                 0x13
 461 #define PALMAS_RTC_COMP_MSB_REG                                 0x14
 462 #define PALMAS_RTC_RES_PROG_REG                                 0x15
 463 #define PALMAS_RTC_RESET_STATUS_REG                             0x16
 464
 465 /* Bit definitions for SECONDS_REG */
 466 #define PALMAS_SECONDS_REG_SEC1_MASK                            0x70
 467 #define PALMAS_SECONDS_REG_SEC1_SHIFT                           4
 468 #define PALMAS_SECONDS_REG_SEC0_MASK                            0x0f
 469 #define PALMAS_SECONDS_REG_SEC0_SHIFT                           0
 470
 471 /* Bit definitions for MINUTES_REG */
 472 #define PALMAS_MINUTES_REG_MIN1_MASK                            0x70
 473 #define PALMAS_MINUTES_REG_MIN1_SHIFT                           4
 474 #define PALMAS_MINUTES_REG_MIN0_MASK                            0x0f
 475 #define PALMAS_MINUTES_REG_MIN0_SHIFT                           0
 476
 477 /* Bit definitions for HOURS_REG */
 478 #define PALMAS_HOURS_REG_PM_NAM                                 0x80
 479 #define PALMAS_HOURS_REG_PM_NAM_SHIFT                           7
 480 #define PALMAS_HOURS_REG_HOUR1_MASK                             0x30
 481 #define PALMAS_HOURS_REG_HOUR1_SHIFT                            4
 482 #define PALMAS_HOURS_REG_HOUR0_MASK                             0x0f
 483 #define PALMAS_HOURS_REG_HOUR0_SHIFT                            0
 484
 485 /* Bit definitions for DAYS_REG */
 486 #define PALMAS_DAYS_REG_DAY1_MASK                               0x30
 487 #define PALMAS_DAYS_REG_DAY1_SHIFT                              4
 488 #define PALMAS_DAYS_REG_DAY0_MASK                               0x0f
 489 #define PALMAS_DAYS_REG_DAY0_SHIFT                              0
 490
 491 /* Bit definitions for MONTHS_REG */
 492 #define PALMAS_MONTHS_REG_MONTH1                                0x10
 493 #define PALMAS_MONTHS_REG_MONTH1_SHIFT                          4
 494 #define PALMAS_MONTHS_REG_MONTH0_MASK                           0x0f
 495 #define PALMAS_MONTHS_REG_MONTH0_SHIFT                          0
 496
 497 /* Bit definitions for YEARS_REG */
 498 #define PALMAS_YEARS_REG_YEAR1_MASK                             0xf0
 499 #define PALMAS_YEARS_REG_YEAR1_SHIFT                            4
 500 #define PALMAS_YEARS_REG_YEAR0_MASK                             0x0f
 501 #define PALMAS_YEARS_REG_YEAR0_SHIFT                            0
 502
 503 /* Bit definitions for WEEKS_REG */
 504 #define PALMAS_WEEKS_REG_WEEK_MASK                              0x07
 505 #define PALMAS_WEEKS_REG_WEEK_SHIFT                             0
 506
 507 /* Bit definitions for ALARM_SECONDS_REG */
 508 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK                0x70
 509 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT               4
 510 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK                0x0f
 511 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT               0
 512
 513 /* Bit definitions for ALARM_MINUTES_REG */
 514 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK                0x70
 515 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT               4
 516 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK                0x0f
 517 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT               0
 518
 519 /* Bit definitions for ALARM_HOURS_REG */
 520 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM                     0x80
 521 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT               7
 522 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK                 0x30
 523 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT                4
 524 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK                 0x0f
 525 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT                0
 526
 527 /* Bit definitions for ALARM_DAYS_REG */
 528 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK                   0x30
 529 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT                  4
 530 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK                   0x0f
 531 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT                  0
 532
 533 /* Bit definitions for ALARM_MONTHS_REG */
 534 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1                    0x10
 535 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT              4
 536 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK               0x0f
 537 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT              0
 538
 539 /* Bit definitions for ALARM_YEARS_REG */
 540 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK                 0xf0
 541 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT                4
 542 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK                 0x0f
 543 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT                0
 544
 545 /* Bit definitions for RTC_CTRL_REG */
 546 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT                           0x80
 547 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT                     7
 548 #define PALMAS_RTC_CTRL_REG_GET_TIME                            0x40
 549 #define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT                      6
 550 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER                      0x20
 551 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT                5
 552 #define PALMAS_RTC_CTRL_REG_TEST_MODE                           0x10
 553 #define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT                     4
 554 #define PALMAS_RTC_CTRL_REG_MODE_12_24                          0x08
 555 #define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT                    3
 556 #define PALMAS_RTC_CTRL_REG_AUTO_COMP                           0x04
 557 #define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT                     2
 558 #define PALMAS_RTC_CTRL_REG_ROUND_30S                           0x02
 559 #define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT                     1
 560 #define PALMAS_RTC_CTRL_REG_STOP_RTC                            0x01
 561 #define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT                      0
 562
 563 /* Bit definitions for RTC_STATUS_REG */
 564 #define PALMAS_RTC_STATUS_REG_POWER_UP                          0x80
 565 #define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT                    7
 566 #define PALMAS_RTC_STATUS_REG_ALARM                             0x40
 567 #define PALMAS_RTC_STATUS_REG_ALARM_SHIFT                       6
 568 #define PALMAS_RTC_STATUS_REG_EVENT_1D                          0x20
 569 #define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT                    5
 570 #define PALMAS_RTC_STATUS_REG_EVENT_1H                          0x10
 571 #define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT                    4
 572 #define PALMAS_RTC_STATUS_REG_EVENT_1M                          0x08
 573 #define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT                    3
 574 #define PALMAS_RTC_STATUS_REG_EVENT_1S                          0x04
 575 #define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT                    2
 576 #define PALMAS_RTC_STATUS_REG_RUN                               0x02
 577 #define PALMAS_RTC_STATUS_REG_RUN_SHIFT                         1
 578
 579 /* Bit definitions for RTC_INTERRUPTS_REG */
 580 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN              0x10
 581 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT        4
 582 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM                      0x08
 583 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT                3
 584 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER                      0x04
 585 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT                2
 586 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK                    0x03
 587 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT                   0
 588
 589 /* Bit definitions for RTC_COMP_LSB_REG */
 590 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK               0xff
 591 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT              0
 592
 593 /* Bit definitions for RTC_COMP_MSB_REG */
 594 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK               0xff
 595 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT              0
 596
 597 /* Bit definitions for RTC_RES_PROG_REG */
 598 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK                0x3f
 599 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT               0
 600
 601 /* Bit definitions for RTC_RESET_STATUS_REG */
 602 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS                0x01
 603 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT          0
 604
 605 /* Registers for function BACKUP */
 606 #define PALMAS_BACKUP0                                          0x0
 607 #define PALMAS_BACKUP1                                          0x1
 608 #define PALMAS_BACKUP2                                          0x2
 609 #define PALMAS_BACKUP3                                          0x3
 610 #define PALMAS_BACKUP4                                          0x4
 611 #define PALMAS_BACKUP5                                          0x5
 612 #define PALMAS_BACKUP6                                          0x6
 613 #define PALMAS_BACKUP7                                          0x7
 614
 615 /* Bit definitions for BACKUP0 */
 616 #define PALMAS_BACKUP0_BACKUP_MASK                              0xff
 617 #define PALMAS_BACKUP0_BACKUP_SHIFT                             0
 618
 619 /* Bit definitions for BACKUP1 */
 620 #define PALMAS_BACKUP1_BACKUP_MASK                              0xff
 621 #define PALMAS_BACKUP1_BACKUP_SHIFT                             0
 622
 623 /* Bit definitions for BACKUP2 */
 624 #define PALMAS_BACKUP2_BACKUP_MASK                              0xff
 625 #define PALMAS_BACKUP2_BACKUP_SHIFT                             0
 626
 627 /* Bit definitions for BACKUP3 */
 628 #define PALMAS_BACKUP3_BACKUP_MASK                              0xff
 629 #define PALMAS_BACKUP3_BACKUP_SHIFT                             0
 630
 631 /* Bit definitions for BACKUP4 */
 632 #define PALMAS_BACKUP4_BACKUP_MASK                              0xff
 633 #define PALMAS_BACKUP4_BACKUP_SHIFT                             0
 634
 635 /* Bit definitions for BACKUP5 */
 636 #define PALMAS_BACKUP5_BACKUP_MASK                              0xff
 637 #define PALMAS_BACKUP5_BACKUP_SHIFT                             0
 638
 639 /* Bit definitions for BACKUP6 */
 640 #define PALMAS_BACKUP6_BACKUP_MASK                              0xff
 641 #define PALMAS_BACKUP6_BACKUP_SHIFT                             0
 642
 643 /* Bit definitions for BACKUP7 */
 644 #define PALMAS_BACKUP7_BACKUP_MASK                              0xff
 645 #define PALMAS_BACKUP7_BACKUP_SHIFT                             0
 646
 647 /* Registers for function SMPS */
 648 #define PALMAS_SMPS12_CTRL                                      0x0
 649 #define PALMAS_SMPS12_TSTEP                                     0x1
 650 #define PALMAS_SMPS12_FORCE                                     0x2
 651 #define PALMAS_SMPS12_VOLTAGE                                   0x3
 652 #define PALMAS_SMPS3_CTRL                                       0x4
 653 #define PALMAS_SMPS3_VOLTAGE                                    0x7
 654 #define PALMAS_SMPS45_CTRL                                      0x8
 655 #define PALMAS_SMPS45_TSTEP                                     0x9
 656 #define PALMAS_SMPS45_FORCE                                     0xA
 657 #define PALMAS_SMPS45_VOLTAGE                                   0xB
 658 #define PALMAS_SMPS6_CTRL                                       0xC
 659 #define PALMAS_SMPS6_TSTEP                                      0xD
 660 #define PALMAS_SMPS6_FORCE                                      0xE
 661 #define PALMAS_SMPS6_VOLTAGE                                    0xF
 662 #define PALMAS_SMPS7_CTRL                                       0x10
 663 #define PALMAS_SMPS7_VOLTAGE                                    0x13
 664 #define PALMAS_SMPS8_CTRL                                       0x14
 665 #define PALMAS_SMPS8_TSTEP                                      0x15
 666 #define PALMAS_SMPS8_FORCE                                      0x16
 667 #define PALMAS_SMPS8_VOLTAGE                                    0x17
 668 #define PALMAS_SMPS9_CTRL                                       0x18
 669 #define PALMAS_SMPS9_VOLTAGE                                    0x1B
 670 #define PALMAS_SMPS10_CTRL                                      0x1C
 671 #define PALMAS_SMPS10_STATUS                                    0x1F
 672 #define PALMAS_SMPS_CTRL                                        0x24
 673 #define PALMAS_SMPS_PD_CTRL                                     0x25
 674 #define PALMAS_SMPS_DITHER_EN                                   0x26
 675 #define PALMAS_SMPS_THERMAL_EN                                  0x27
 676 #define PALMAS_SMPS_THERMAL_STATUS                              0x28
 677 #define PALMAS_SMPS_SHORT_STATUS                                0x29
 678 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN                   0x2A
 679 #define PALMAS_SMPS_POWERGOOD_MASK1                             0x2B
 680 #define PALMAS_SMPS_POWERGOOD_MASK2                             0x2C
 681
 682 /* Bit definitions for SMPS12_CTRL */
 683 #define PALMAS_SMPS12_CTRL_WR_S                                 0x80
 684 #define PALMAS_SMPS12_CTRL_WR_S_SHIFT                           7
 685 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN                        0x40
 686 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT                  6
 687 #define PALMAS_SMPS12_CTRL_STATUS_MASK                          0x30
 688 #define PALMAS_SMPS12_CTRL_STATUS_SHIFT                         4
 689 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK                      0x0c
 690 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT                     2
 691 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK                     0x03
 692 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT                    0
 693
 694 /* Bit definitions for SMPS12_TSTEP */
 695 #define PALMAS_SMPS12_TSTEP_TSTEP_MASK                          0x03
 696 #define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT                         0
 697
 698 /* Bit definitions for SMPS12_FORCE */
 699 #define PALMAS_SMPS12_FORCE_CMD                                 0x80
 700 #define PALMAS_SMPS12_FORCE_CMD_SHIFT                           7
 701 #define PALMAS_SMPS12_FORCE_VSEL_MASK                           0x7f
 702 #define PALMAS_SMPS12_FORCE_VSEL_SHIFT                          0
 703
 704 /* Bit definitions for SMPS12_VOLTAGE */
 705 #define PALMAS_SMPS12_VOLTAGE_RANGE                             0x80
 706 #define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT                       7
 707 #define PALMAS_SMPS12_VOLTAGE_VSEL_MASK                         0x7f
 708 #define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT                        0
 709
 710 /* Bit definitions for SMPS3_CTRL */
 711 #define PALMAS_SMPS3_CTRL_WR_S                                  0x80
 712 #define PALMAS_SMPS3_CTRL_WR_S_SHIFT                            7
 713 #define PALMAS_SMPS3_CTRL_STATUS_MASK                           0x30
 714 #define PALMAS_SMPS3_CTRL_STATUS_SHIFT                          4
 715 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK                       0x0c
 716 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT                      2
 717 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK                      0x03
 718 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT                     0
 719
 720 /* Bit definitions for SMPS3_VOLTAGE */
 721 #define PALMAS_SMPS3_VOLTAGE_RANGE                              0x80
 722 #define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT                        7
 723 #define PALMAS_SMPS3_VOLTAGE_VSEL_MASK                          0x7f
 724 #define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT                         0
 725
 726 /* Bit definitions for SMPS45_CTRL */
 727 #define PALMAS_SMPS45_CTRL_WR_S                                 0x80
 728 #define PALMAS_SMPS45_CTRL_WR_S_SHIFT                           7
 729 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN                        0x40
 730 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT                  6
 731 #define PALMAS_SMPS45_CTRL_STATUS_MASK                          0x30
 732 #define PALMAS_SMPS45_CTRL_STATUS_SHIFT                         4
 733 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK                      0x0c
 734 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT                     2
 735 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK                     0x03
 736 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT                    0
 737
 738 /* Bit definitions for SMPS45_TSTEP */
 739 #define PALMAS_SMPS45_TSTEP_TSTEP_MASK                          0x03
 740 #define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT                         0
 741
 742 /* Bit definitions for SMPS45_FORCE */
 743 #define PALMAS_SMPS45_FORCE_CMD                                 0x80
 744 #define PALMAS_SMPS45_FORCE_CMD_SHIFT                           7
 745 #define PALMAS_SMPS45_FORCE_VSEL_MASK                           0x7f
 746 #define PALMAS_SMPS45_FORCE_VSEL_SHIFT                          0
 747
 748 /* Bit definitions for SMPS45_VOLTAGE */
 749 #define PALMAS_SMPS45_VOLTAGE_RANGE                             0x80
 750 #define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT                       7
 751 #define PALMAS_SMPS45_VOLTAGE_VSEL_MASK                         0x7f
 752 #define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT                        0
 753
 754 /* Bit definitions for SMPS6_CTRL */
 755 #define PALMAS_SMPS6_CTRL_WR_S                                  0x80
 756 #define PALMAS_SMPS6_CTRL_WR_S_SHIFT                            7
 757 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN                         0x40
 758 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT                   6
 759 #define PALMAS_SMPS6_CTRL_STATUS_MASK                           0x30
 760 #define PALMAS_SMPS6_CTRL_STATUS_SHIFT                          4
 761 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK                       0x0c
 762 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT                      2
 763 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK                      0x03
 764 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT                     0
 765
 766 /* Bit definitions for SMPS6_TSTEP */
 767 #define PALMAS_SMPS6_TSTEP_TSTEP_MASK                           0x03
 768 #define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT                          0
 769
 770 /* Bit definitions for SMPS6_FORCE */
 771 #define PALMAS_SMPS6_FORCE_CMD                                  0x80
 772 #define PALMAS_SMPS6_FORCE_CMD_SHIFT                            7
 773 #define PALMAS_SMPS6_FORCE_VSEL_MASK                            0x7f
 774 #define PALMAS_SMPS6_FORCE_VSEL_SHIFT                           0
 775
 776 /* Bit definitions for SMPS6_VOLTAGE */
 777 #define PALMAS_SMPS6_VOLTAGE_RANGE                              0x80
 778 #define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT                        7
 779 #define PALMAS_SMPS6_VOLTAGE_VSEL_MASK                          0x7f
 780 #define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT                         0
 781
 782 /* Bit definitions for SMPS7_CTRL */
 783 #define PALMAS_SMPS7_CTRL_WR_S                                  0x80
 784 #define PALMAS_SMPS7_CTRL_WR_S_SHIFT                            7
 785 #define PALMAS_SMPS7_CTRL_STATUS_MASK                           0x30
 786 #define PALMAS_SMPS7_CTRL_STATUS_SHIFT                          4
 787 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK                       0x0c
 788 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT                      2
 789 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK                      0x03
 790 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT                     0
 791
 792 /* Bit definitions for SMPS7_VOLTAGE */
 793 #define PALMAS_SMPS7_VOLTAGE_RANGE                              0x80
 794 #define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT                        7
 795 #define PALMAS_SMPS7_VOLTAGE_VSEL_MASK                          0x7f
 796 #define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT                         0
 797
 798 /* Bit definitions for SMPS8_CTRL */
 799 #define PALMAS_SMPS8_CTRL_WR_S                                  0x80
 800 #define PALMAS_SMPS8_CTRL_WR_S_SHIFT                            7
 801 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN                         0x40
 802 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT                   6
 803 #define PALMAS_SMPS8_CTRL_STATUS_MASK                           0x30
 804 #define PALMAS_SMPS8_CTRL_STATUS_SHIFT                          4
 805 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK                       0x0c
 806 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT                      2
 807 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK                      0x03
 808 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT                     0
 809
 810 /* Bit definitions for SMPS8_TSTEP */
 811 #define PALMAS_SMPS8_TSTEP_TSTEP_MASK                           0x03
 812 #define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT                          0
 813
 814 /* Bit definitions for SMPS8_FORCE */
 815 #define PALMAS_SMPS8_FORCE_CMD                                  0x80
 816 #define PALMAS_SMPS8_FORCE_CMD_SHIFT                            7
 817 #define PALMAS_SMPS8_FORCE_VSEL_MASK                            0x7f
 818 #define PALMAS_SMPS8_FORCE_VSEL_SHIFT                           0
 819
 820 /* Bit definitions for SMPS8_VOLTAGE */
 821 #define PALMAS_SMPS8_VOLTAGE_RANGE                              0x80
 822 #define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT                        7
 823 #define PALMAS_SMPS8_VOLTAGE_VSEL_MASK                          0x7f
 824 #define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT                         0
 825
 826 /* Bit definitions for SMPS9_CTRL */
 827 #define PALMAS_SMPS9_CTRL_WR_S                                  0x80
 828 #define PALMAS_SMPS9_CTRL_WR_S_SHIFT                            7
 829 #define PALMAS_SMPS9_CTRL_STATUS_MASK                           0x30
 830 #define PALMAS_SMPS9_CTRL_STATUS_SHIFT                          4
 831 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK                       0x0c
 832 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT                      2
 833 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK                      0x03
 834 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT                     0
 835
 836 /* Bit definitions for SMPS9_VOLTAGE */
 837 #define PALMAS_SMPS9_VOLTAGE_RANGE                              0x80
 838 #define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT                        7
 839 #define PALMAS_SMPS9_VOLTAGE_VSEL_MASK                          0x7f
 840 #define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT                         0
 841
 842 /* Bit definitions for SMPS10_CTRL */
 843 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK                      0xf0
 844 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT                     4
 845 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK                     0x0f
 846 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT                    0
 847
 848 /* Bit definitions for SMPS10_STATUS */
 849 #define PALMAS_SMPS10_STATUS_STATUS_MASK                        0x0f
 850 #define PALMAS_SMPS10_STATUS_STATUS_SHIFT                       0
 851
 852 /* Bit definitions for SMPS_CTRL */
 853 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN                      0x20
 854 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT                5
 855 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN                      0x10
 856 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT                4
 857 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK                 0x0c
 858 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT                2
 859 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK                0x03
 860 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT               0
 861
 862 /* Bit definitions for SMPS_PD_CTRL */
 863 #define PALMAS_SMPS_PD_CTRL_SMPS9                               0x40
 864 #define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT                         6
 865 #define PALMAS_SMPS_PD_CTRL_SMPS8                               0x20
 866 #define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT                         5
 867 #define PALMAS_SMPS_PD_CTRL_SMPS7                               0x10
 868 #define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT                         4
 869 #define PALMAS_SMPS_PD_CTRL_SMPS6                               0x08
 870 #define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT                         3
 871 #define PALMAS_SMPS_PD_CTRL_SMPS45                              0x04
 872 #define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT                        2
 873 #define PALMAS_SMPS_PD_CTRL_SMPS3                               0x02
 874 #define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT                         1
 875 #define PALMAS_SMPS_PD_CTRL_SMPS12                              0x01
 876 #define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT                        0
 877
 878 /* Bit definitions for SMPS_THERMAL_EN */
 879 #define PALMAS_SMPS_THERMAL_EN_SMPS9                            0x40
 880 #define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT                      6
 881 #define PALMAS_SMPS_THERMAL_EN_SMPS8                            0x20
 882 #define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT                      5
 883 #define PALMAS_SMPS_THERMAL_EN_SMPS6                            0x08
 884 #define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT                      3
 885 #define PALMAS_SMPS_THERMAL_EN_SMPS457                          0x04
 886 #define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT                    2
 887 #define PALMAS_SMPS_THERMAL_EN_SMPS123                          0x01
 888 #define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT                    0
 889
 890 /* Bit definitions for SMPS_THERMAL_STATUS */
 891 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9                        0x40
 892 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT                  6
 893 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8                        0x20
 894 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT                  5
 895 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6                        0x08
 896 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT                  3
 897 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457                      0x04
 898 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT                2
 899 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123                      0x01
 900 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT                0
 901
 902 /* Bit definitions for SMPS_SHORT_STATUS */
 903 #define PALMAS_SMPS_SHORT_STATUS_SMPS10                         0x80
 904 #define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT                   7
 905 #define PALMAS_SMPS_SHORT_STATUS_SMPS9                          0x40
 906 #define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT                    6
 907 #define PALMAS_SMPS_SHORT_STATUS_SMPS8                          0x20
 908 #define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT                    5
 909 #define PALMAS_SMPS_SHORT_STATUS_SMPS7                          0x10
 910 #define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT                    4
 911 #define PALMAS_SMPS_SHORT_STATUS_SMPS6                          0x08
 912 #define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT                    3
 913 #define PALMAS_SMPS_SHORT_STATUS_SMPS45                         0x04
 914 #define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT                   2
 915 #define PALMAS_SMPS_SHORT_STATUS_SMPS3                          0x02
 916 #define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT                    1
 917 #define PALMAS_SMPS_SHORT_STATUS_SMPS12                         0x01
 918 #define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT                   0
 919
 920 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
 921 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9             0x40
 922 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT       6
 923 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8             0x20
 924 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT       5
 925 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7             0x10
 926 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT       4
 927 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6             0x08
 928 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT       3
 929 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45            0x04
 930 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT      2
 931 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3             0x02
 932 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT       1
 933 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12            0x01
 934 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT      0
 935
 936 /* Bit definitions for SMPS_POWERGOOD_MASK1 */
 937 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10                      0x80
 938 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT                7
 939 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9                       0x40
 940 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT                 6
 941 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8                       0x20
 942 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT                 5
 943 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7                       0x10
 944 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT                 4
 945 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6                       0x08
 946 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT                 3
 947 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45                      0x04
 948 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT                2
 949 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3                       0x02
 950 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT                 1
 951 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12                      0x01
 952 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT                0
 953
 954 /* Bit definitions for SMPS_POWERGOOD_MASK2 */
 955 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT       0x80
 956 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7
 957 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7                      0x04
 958 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT                2
 959 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS                        0x02
 960 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT                  1
 961 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK                        0x01
 962 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT                  0
 963
 964 /* Registers for function LDO */
 965 #define PALMAS_LDO1_CTRL                                        0x0
 966 #define PALMAS_LDO1_VOLTAGE                                     0x1
 967 #define PALMAS_LDO2_CTRL                                        0x2
 968 #define PALMAS_LDO2_VOLTAGE                                     0x3
 969 #define PALMAS_LDO3_CTRL                                        0x4
 970 #define PALMAS_LDO3_VOLTAGE                                     0x5
 971 #define PALMAS_LDO4_CTRL                                        0x6
 972 #define PALMAS_LDO4_VOLTAGE                                     0x7
 973 #define PALMAS_LDO5_CTRL                                        0x8
 974 #define PALMAS_LDO5_VOLTAGE                                     0x9
 975 #define PALMAS_LDO6_CTRL                                        0xA
 976 #define PALMAS_LDO6_VOLTAGE                                     0xB
 977 #define PALMAS_LDO7_CTRL                                        0xC
 978 #define PALMAS_LDO7_VOLTAGE                                     0xD
 979 #define PALMAS_LDO8_CTRL                                        0xE
 980 #define PALMAS_LDO8_VOLTAGE                                     0xF
 981 #define PALMAS_LDO9_CTRL                                        0x10
 982 #define PALMAS_LDO9_VOLTAGE                                     0x11
 983 #define PALMAS_LDOLN_CTRL                                       0x12
 984 #define PALMAS_LDOLN_VOLTAGE                                    0x13
 985 #define PALMAS_LDOUSB_CTRL                                      0x14
 986 #define PALMAS_LDOUSB_VOLTAGE                                   0x15
 987 #define PALMAS_LDO_CTRL                                         0x1A
 988 #define PALMAS_LDO_PD_CTRL1                                     0x1B
 989 #define PALMAS_LDO_PD_CTRL2                                     0x1C
 990 #define PALMAS_LDO_SHORT_STATUS1                                0x1D
 991 #define PALMAS_LDO_SHORT_STATUS2                                0x1E
 992
 993 /* Bit definitions for LDO1_CTRL */
 994 #define PALMAS_LDO1_CTRL_WR_S                                   0x80
 995 #define PALMAS_LDO1_CTRL_WR_S_SHIFT                             7
 996 #define PALMAS_LDO1_CTRL_STATUS                                 0x10
 997 #define PALMAS_LDO1_CTRL_STATUS_SHIFT                           4
 998 #define PALMAS_LDO1_CTRL_MODE_SLEEP                             0x04
 999 #define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT                       2
1000 #define PALMAS_LDO1_CTRL_MODE_ACTIVE                            0x01
1001 #define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT                      0
1002
1003 /* Bit definitions for LDO1_VOLTAGE */
1004 #define PALMAS_LDO1_VOLTAGE_VSEL_MASK                           0x3f
1005 #define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT                          0
1006
1007 /* Bit definitions for LDO2_CTRL */
1008 #define PALMAS_LDO2_CTRL_WR_S                                   0x80
1009 #define PALMAS_LDO2_CTRL_WR_S_SHIFT                             7
1010 #define PALMAS_LDO2_CTRL_STATUS                                 0x10
1011 #define PALMAS_LDO2_CTRL_STATUS_SHIFT                           4
1012 #define PALMAS_LDO2_CTRL_MODE_SLEEP                             0x04
1013 #define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT                       2
1014 #define PALMAS_LDO2_CTRL_MODE_ACTIVE                            0x01
1015 #define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT                      0
1016
1017 /* Bit definitions for LDO2_VOLTAGE */
1018 #define PALMAS_LDO2_VOLTAGE_VSEL_MASK                           0x3f
1019 #define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT                          0
1020
1021 /* Bit definitions for LDO3_CTRL */
1022 #define PALMAS_LDO3_CTRL_WR_S                                   0x80
1023 #define PALMAS_LDO3_CTRL_WR_S_SHIFT                             7
1024 #define PALMAS_LDO3_CTRL_STATUS                                 0x10
1025 #define PALMAS_LDO3_CTRL_STATUS_SHIFT                           4
1026 #define PALMAS_LDO3_CTRL_MODE_SLEEP                             0x04
1027 #define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT                       2
1028 #define PALMAS_LDO3_CTRL_MODE_ACTIVE                            0x01
1029 #define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT                      0
1030
1031 /* Bit definitions for LDO3_VOLTAGE */
1032 #define PALMAS_LDO3_VOLTAGE_VSEL_MASK                           0x3f
1033 #define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT                          0
1034
1035 /* Bit definitions for LDO4_CTRL */
1036 #define PALMAS_LDO4_CTRL_WR_S                                   0x80
1037 #define PALMAS_LDO4_CTRL_WR_S_SHIFT                             7
1038 #define PALMAS_LDO4_CTRL_STATUS                                 0x10
1039 #define PALMAS_LDO4_CTRL_STATUS_SHIFT                           4
1040 #define PALMAS_LDO4_CTRL_MODE_SLEEP                             0x04
1041 #define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT                       2
1042 #define PALMAS_LDO4_CTRL_MODE_ACTIVE                            0x01
1043 #define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT                      0
1044
1045 /* Bit definitions for LDO4_VOLTAGE */
1046 #define PALMAS_LDO4_VOLTAGE_VSEL_MASK                           0x3f
1047 #define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT                          0
1048
1049 /* Bit definitions for LDO5_CTRL */
1050 #define PALMAS_LDO5_CTRL_WR_S                                   0x80
1051 #define PALMAS_LDO5_CTRL_WR_S_SHIFT                             7
1052 #define PALMAS_LDO5_CTRL_STATUS                                 0x10
1053 #define PALMAS_LDO5_CTRL_STATUS_SHIFT                           4
1054 #define PALMAS_LDO5_CTRL_MODE_SLEEP                             0x04
1055 #define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT                       2
1056 #define PALMAS_LDO5_CTRL_MODE_ACTIVE                            0x01
1057 #define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT                      0
1058
1059 /* Bit definitions for LDO5_VOLTAGE */
1060 #define PALMAS_LDO5_VOLTAGE_VSEL_MASK                           0x3f
1061 #define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT                          0
1062
1063 /* Bit definitions for LDO6_CTRL */
1064 #define PALMAS_LDO6_CTRL_WR_S                                   0x80
1065 #define PALMAS_LDO6_CTRL_WR_S_SHIFT                             7
1066 #define PALMAS_LDO6_CTRL_LDO_VIB_EN                             0x40
1067 #define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT                       6
1068 #define PALMAS_LDO6_CTRL_STATUS                                 0x10
1069 #define PALMAS_LDO6_CTRL_STATUS_SHIFT                           4
1070 #define PALMAS_LDO6_CTRL_MODE_SLEEP                             0x04
1071 #define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT                       2
1072 #define PALMAS_LDO6_CTRL_MODE_ACTIVE                            0x01
1073 #define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT                      0
1074
1075 /* Bit definitions for LDO6_VOLTAGE */
1076 #define PALMAS_LDO6_VOLTAGE_VSEL_MASK                           0x3f
1077 #define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT                          0
1078
1079 /* Bit definitions for LDO7_CTRL */
1080 #define PALMAS_LDO7_CTRL_WR_S                                   0x80
1081 #define PALMAS_LDO7_CTRL_WR_S_SHIFT                             7
1082 #define PALMAS_LDO7_CTRL_STATUS                                 0x10
1083 #define PALMAS_LDO7_CTRL_STATUS_SHIFT                           4
1084 #define PALMAS_LDO7_CTRL_MODE_SLEEP                             0x04
1085 #define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT                       2
1086 #define PALMAS_LDO7_CTRL_MODE_ACTIVE                            0x01
1087 #define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT                      0
1088
1089 /* Bit definitions for LDO7_VOLTAGE */
1090 #define PALMAS_LDO7_VOLTAGE_VSEL_MASK                           0x3f
1091 #define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT                          0
1092
1093 /* Bit definitions for LDO8_CTRL */
1094 #define PALMAS_LDO8_CTRL_WR_S                                   0x80
1095 #define PALMAS_LDO8_CTRL_WR_S_SHIFT                             7
1096 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN                        0x40
1097 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT                  6
1098 #define PALMAS_LDO8_CTRL_STATUS                                 0x10
1099 #define PALMAS_LDO8_CTRL_STATUS_SHIFT                           4
1100 #define PALMAS_LDO8_CTRL_MODE_SLEEP                             0x04
1101 #define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT                       2
1102 #define PALMAS_LDO8_CTRL_MODE_ACTIVE                            0x01
1103 #define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT                      0
1104
1105 /* Bit definitions for LDO8_VOLTAGE */
1106 #define PALMAS_LDO8_VOLTAGE_VSEL_MASK                           0x3f
1107 #define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT                          0
1108
1109 /* Bit definitions for LDO9_CTRL */
1110 #define PALMAS_LDO9_CTRL_WR_S                                   0x80
1111 #define PALMAS_LDO9_CTRL_WR_S_SHIFT                             7
1112 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN                          0x40
1113 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT                    6
1114 #define PALMAS_LDO9_CTRL_STATUS                                 0x10
1115 #define PALMAS_LDO9_CTRL_STATUS_SHIFT                           4
1116 #define PALMAS_LDO9_CTRL_MODE_SLEEP                             0x04
1117 #define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT                       2
1118 #define PALMAS_LDO9_CTRL_MODE_ACTIVE                            0x01
1119 #define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT                      0
1120
1121 /* Bit definitions for LDO9_VOLTAGE */
1122 #define PALMAS_LDO9_VOLTAGE_VSEL_MASK                           0x3f
1123 #define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT                          0
1124
1125 /* Bit definitions for LDOLN_CTRL */
1126 #define PALMAS_LDOLN_CTRL_WR_S                                  0x80
1127 #define PALMAS_LDOLN_CTRL_WR_S_SHIFT                            7
1128 #define PALMAS_LDOLN_CTRL_STATUS                                0x10
1129 #define PALMAS_LDOLN_CTRL_STATUS_SHIFT                          4
1130 #define PALMAS_LDOLN_CTRL_MODE_SLEEP                            0x04
1131 #define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT                      2
1132 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE                           0x01
1133 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT                     0
1134
1135 /* Bit definitions for LDOLN_VOLTAGE */
1136 #define PALMAS_LDOLN_VOLTAGE_VSEL_MASK                          0x3f
1137 #define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT                         0
1138
1139 /* Bit definitions for LDOUSB_CTRL */
1140 #define PALMAS_LDOUSB_CTRL_WR_S                                 0x80
1141 #define PALMAS_LDOUSB_CTRL_WR_S_SHIFT                           7
1142 #define PALMAS_LDOUSB_CTRL_STATUS                               0x10
1143 #define PALMAS_LDOUSB_CTRL_STATUS_SHIFT                         4
1144 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP                           0x04
1145 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT                     2
1146 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE                          0x01
1147 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT                    0
1148
1149 /* Bit definitions for LDOUSB_VOLTAGE */
1150 #define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK                         0x3f
1151 #define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT                        0
1152
1153 /* Bit definitions for LDO_CTRL */
1154 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS                     0x01
1155 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT               0
1156
1157 /* Bit definitions for LDO_PD_CTRL1 */
1158 #define PALMAS_LDO_PD_CTRL1_LDO8                                0x80
1159 #define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT                          7
1160 #define PALMAS_LDO_PD_CTRL1_LDO7                                0x40
1161 #define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT                          6
1162 #define PALMAS_LDO_PD_CTRL1_LDO6                                0x20
1163 #define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT                          5
1164 #define PALMAS_LDO_PD_CTRL1_LDO5                                0x10
1165 #define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT                          4
1166 #define PALMAS_LDO_PD_CTRL1_LDO4                                0x08
1167 #define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT                          3
1168 #define PALMAS_LDO_PD_CTRL1_LDO3                                0x04
1169 #define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT                          2
1170 #define PALMAS_LDO_PD_CTRL1_LDO2                                0x02
1171 #define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT                          1
1172 #define PALMAS_LDO_PD_CTRL1_LDO1                                0x01
1173 #define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT                          0
1174
1175 /* Bit definitions for LDO_PD_CTRL2 */
1176 #define PALMAS_LDO_PD_CTRL2_LDOUSB                              0x04
1177 #define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT                        2
1178 #define PALMAS_LDO_PD_CTRL2_LDOLN                               0x02
1179 #define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT                         1
1180 #define PALMAS_LDO_PD_CTRL2_LDO9                                0x01
1181 #define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT                          0
1182
1183 /* Bit definitions for LDO_SHORT_STATUS1 */
1184 #define PALMAS_LDO_SHORT_STATUS1_LDO8                           0x80
1185 #define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT                     7
1186 #define PALMAS_LDO_SHORT_STATUS1_LDO7                           0x40
1187 #define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT                     6
1188 #define PALMAS_LDO_SHORT_STATUS1_LDO6                           0x20
1189 #define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT                     5
1190 #define PALMAS_LDO_SHORT_STATUS1_LDO5                           0x10
1191 #define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT                     4
1192 #define PALMAS_LDO_SHORT_STATUS1_LDO4                           0x08
1193 #define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT                     3
1194 #define PALMAS_LDO_SHORT_STATUS1_LDO3                           0x04
1195 #define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT                     2
1196 #define PALMAS_LDO_SHORT_STATUS1_LDO2                           0x02
1197 #define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT                     1
1198 #define PALMAS_LDO_SHORT_STATUS1_LDO1                           0x01
1199 #define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT                     0
1200
1201 /* Bit definitions for LDO_SHORT_STATUS2 */
1202 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA                        0x08
1203 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT                  3
1204 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB                         0x04
1205 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT                   2
1206 #define PALMAS_LDO_SHORT_STATUS2_LDOLN                          0x02
1207 #define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT                    1
1208 #define PALMAS_LDO_SHORT_STATUS2_LDO9                           0x01
1209 #define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT                     0
1210
1211 /* Registers for function PMU_CONTROL */
1212 #define PALMAS_DEV_CTRL                                         0x0
1213 #define PALMAS_POWER_CTRL                                       0x1
1214 #define PALMAS_VSYS_LO                                          0x2
1215 #define PALMAS_VSYS_MON                                         0x3
1216 #define PALMAS_VBAT_MON                                         0x4
1217 #define PALMAS_WATCHDOG                                         0x5
1218 #define PALMAS_BOOT_STATUS                                      0x6
1219 #define PALMAS_BATTERY_BOUNCE                                   0x7
1220 #define PALMAS_BACKUP_BATTERY_CTRL                              0x8
1221 #define PALMAS_LONG_PRESS_KEY                                   0x9
1222 #define PALMAS_OSC_THERM_CTRL                                   0xA
1223 #define PALMAS_BATDEBOUNCING                                    0xB
1224 #define PALMAS_SWOFF_HWRST                                      0xF
1225 #define PALMAS_SWOFF_COLDRST                                    0x10
1226 #define PALMAS_SWOFF_STATUS                                     0x11
1227 #define PALMAS_PMU_CONFIG                                       0x12
1228 #define PALMAS_SPARE                                            0x14
1229 #define PALMAS_PMU_SECONDARY_INT                                0x15
1230 #define PALMAS_SW_REVISION                                      0x17
1231 #define PALMAS_EXT_CHRG_CTRL                                    0x18
1232 #define PALMAS_PMU_SECONDARY_INT2                               0x19
1233
1234 /* Bit definitions for DEV_CTRL */
1235 #define PALMAS_DEV_CTRL_DEV_STATUS_MASK                         0x0c
1236 #define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT                        2
1237 #define PALMAS_DEV_CTRL_SW_RST                                  0x02
1238 #define PALMAS_DEV_CTRL_SW_RST_SHIFT                            1
1239 #define PALMAS_DEV_CTRL_DEV_ON                                  0x01
1240 #define PALMAS_DEV_CTRL_DEV_ON_SHIFT                            0
1241
1242 /* Bit definitions for POWER_CTRL */
1243 #define PALMAS_POWER_CTRL_ENABLE2_MASK                          0x04
1244 #define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT                    2
1245 #define PALMAS_POWER_CTRL_ENABLE1_MASK                          0x02
1246 #define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT                    1
1247 #define PALMAS_POWER_CTRL_NSLEEP_MASK                           0x01
1248 #define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT                     0
1249
1250 /* Bit definitions for VSYS_LO */
1251 #define PALMAS_VSYS_LO_THRESHOLD_MASK                           0x1f
1252 #define PALMAS_VSYS_LO_THRESHOLD_SHIFT                          0
1253
1254 /* Bit definitions for VSYS_MON */
1255 #define PALMAS_VSYS_MON_ENABLE                                  0x80
1256 #define PALMAS_VSYS_MON_ENABLE_SHIFT                            7
1257 #define PALMAS_VSYS_MON_THRESHOLD_MASK                          0x3f
1258 #define PALMAS_VSYS_MON_THRESHOLD_SHIFT                         0
1259
1260 /* Bit definitions for VBAT_MON */
1261 #define PALMAS_VBAT_MON_ENABLE                                  0x80
1262 #define PALMAS_VBAT_MON_ENABLE_SHIFT                            7
1263 #define PALMAS_VBAT_MON_THRESHOLD_MASK                          0x3f
1264 #define PALMAS_VBAT_MON_THRESHOLD_SHIFT                         0
1265
1266 /* Bit definitions for WATCHDOG */
1267 #define PALMAS_WATCHDOG_LOCK                                    0x20
1268 #define PALMAS_WATCHDOG_LOCK_SHIFT                              5
1269 #define PALMAS_WATCHDOG_ENABLE                                  0x10
1270 #define PALMAS_WATCHDOG_ENABLE_SHIFT                            4
1271 #define PALMAS_WATCHDOG_MODE                                    0x08
1272 #define PALMAS_WATCHDOG_MODE_SHIFT                              3
1273 #define PALMAS_WATCHDOG_TIMER_MASK                              0x07
1274 #define PALMAS_WATCHDOG_TIMER_SHIFT                             0
1275
1276 /* Bit definitions for BOOT_STATUS */
1277 #define PALMAS_BOOT_STATUS_BOOT1                                0x02
1278 #define PALMAS_BOOT_STATUS_BOOT1_SHIFT                          1
1279 #define PALMAS_BOOT_STATUS_BOOT0                                0x01
1280 #define PALMAS_BOOT_STATUS_BOOT0_SHIFT                          0
1281
1282 /* Bit definitions for BATTERY_BOUNCE */
1283 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK                     0x3f
1284 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT                    0
1285
1286 /* Bit definitions for BACKUP_BATTERY_CTRL */
1287 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15                   0x80
1288 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT             7
1289 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP                  0x40
1290 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT            6
1291 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF                  0x20
1292 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT            5
1293 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN                    0x10
1294 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT              4
1295 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG            0x08
1296 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT      3
1297 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK                  0x06
1298 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT                 1
1299 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN                    0x01
1300 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT              0
1301
1302 /* Bit definitions for LONG_PRESS_KEY */
1303 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK                          0x80
1304 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT                    7
1305 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR                       0x10
1306 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT                 4
1307 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK                     0x0c
1308 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT                    2
1309 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK               0x03
1310 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT              0
1311
1312 /* Bit definitions for OSC_THERM_CTRL */
1313 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP                  0x80
1314 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT            7
1315 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP                 0x40
1316 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT           6
1317 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP               0x20
1318 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT         5
1319 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP                0x10
1320 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT          4
1321 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK                 0x0c
1322 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT                2
1323 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS                        0x02
1324 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT                  1
1325 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE                        0x01
1326 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT                  0
1327
1328 /* Bit definitions for BATDEBOUNCING */
1329 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS                     0x80
1330 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT               7
1331 #define PALMAS_BATDEBOUNCING_BINS_DEB_MASK                      0x78
1332 #define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT                     3
1333 #define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK                      0x07
1334 #define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT                     0
1335
1336 /* Bit definitions for SWOFF_HWRST */
1337 #define PALMAS_SWOFF_HWRST_PWRON_LPK                            0x80
1338 #define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT                      7
1339 #define PALMAS_SWOFF_HWRST_PWRDOWN                              0x40
1340 #define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT                        6
1341 #define PALMAS_SWOFF_HWRST_WTD                                  0x20
1342 #define PALMAS_SWOFF_HWRST_WTD_SHIFT                            5
1343 #define PALMAS_SWOFF_HWRST_TSHUT                                0x10
1344 #define PALMAS_SWOFF_HWRST_TSHUT_SHIFT                          4
1345 #define PALMAS_SWOFF_HWRST_RESET_IN                             0x08
1346 #define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT                       3
1347 #define PALMAS_SWOFF_HWRST_SW_RST                               0x04
1348 #define PALMAS_SWOFF_HWRST_SW_RST_SHIFT                         2
1349 #define PALMAS_SWOFF_HWRST_VSYS_LO                              0x02
1350 #define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT                        1
1351 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN                       0x01
1352 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT                 0
1353
1354 /* Bit definitions for SWOFF_COLDRST */
1355 #define PALMAS_SWOFF_COLDRST_PWRON_LPK                          0x80
1356 #define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT                    7
1357 #define PALMAS_SWOFF_COLDRST_PWRDOWN                            0x40
1358 #define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT                      6
1359 #define PALMAS_SWOFF_COLDRST_WTD                                0x20
1360 #define PALMAS_SWOFF_COLDRST_WTD_SHIFT                          5
1361 #define PALMAS_SWOFF_COLDRST_TSHUT                              0x10
1362 #define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT                        4
1363 #define PALMAS_SWOFF_COLDRST_RESET_IN                           0x08
1364 #define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT                     3
1365 #define PALMAS_SWOFF_COLDRST_SW_RST                             0x04
1366 #define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT                       2
1367 #define PALMAS_SWOFF_COLDRST_VSYS_LO                            0x02
1368 #define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT                      1
1369 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN                     0x01
1370 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT               0
1371
1372 /* Bit definitions for SWOFF_STATUS */
1373 #define PALMAS_SWOFF_STATUS_PWRON_LPK                           0x80
1374 #define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT                     7
1375 #define PALMAS_SWOFF_STATUS_PWRDOWN                             0x40
1376 #define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT                       6
1377 #define PALMAS_SWOFF_STATUS_WTD                                 0x20
1378 #define PALMAS_SWOFF_STATUS_WTD_SHIFT                           5
1379 #define PALMAS_SWOFF_STATUS_TSHUT                               0x10
1380 #define PALMAS_SWOFF_STATUS_TSHUT_SHIFT                         4
1381 #define PALMAS_SWOFF_STATUS_RESET_IN                            0x08
1382 #define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT                      3
1383 #define PALMAS_SWOFF_STATUS_SW_RST                              0x04
1384 #define PALMAS_SWOFF_STATUS_SW_RST_SHIFT                        2
1385 #define PALMAS_SWOFF_STATUS_VSYS_LO                             0x02
1386 #define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT                       1
1387 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN                      0x01
1388 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT                0
1389
1390 /* Bit definitions for PMU_CONFIG */
1391 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN                         0x40
1392 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT                   6
1393 #define PALMAS_PMU_CONFIG_SPARE_MASK                            0x30
1394 #define PALMAS_PMU_CONFIG_SPARE_SHIFT                           4
1395 #define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK                        0x0c
1396 #define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT                       2
1397 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT                        0x02
1398 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT                  1
1399 #define PALMAS_PMU_CONFIG_AUTODEVON                             0x01
1400 #define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT                       0
1401
1402 /* Bit definitions for SPARE */
1403 #define PALMAS_SPARE_SPARE_MASK                                 0xf8
1404 #define PALMAS_SPARE_SPARE_SHIFT                                3
1405 #define PALMAS_SPARE_REGEN3_OD                                  0x04
1406 #define PALMAS_SPARE_REGEN3_OD_SHIFT                            2
1407 #define PALMAS_SPARE_REGEN2_OD                                  0x02
1408 #define PALMAS_SPARE_REGEN2_OD_SHIFT                            1
1409 #define PALMAS_SPARE_REGEN1_OD                                  0x01
1410 #define PALMAS_SPARE_REGEN1_OD_SHIFT                            0
1411
1412 /* Bit definitions for PMU_SECONDARY_INT */
1413 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC               0x80
1414 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT         7
1415 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC            0x40
1416 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT      6
1417 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC                     0x20
1418 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT               5
1419 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC                    0x10
1420 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT              4
1421 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK                  0x08
1422 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT            3
1423 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK               0x04
1424 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT         2
1425 #define PALMAS_PMU_SECONDARY_INT_BB_MASK                        0x02
1426 #define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT                  1
1427 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK                       0x01
1428 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT                 0
1429
1430 /* Bit definitions for SW_REVISION */
1431 #define PALMAS_SW_REVISION_SW_REVISION_MASK                     0xff
1432 #define PALMAS_SW_REVISION_SW_REVISION_SHIFT                    0
1433
1434 /* Bit definitions for EXT_CHRG_CTRL */
1435 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS                    0x80
1436 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT              7
1437 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS                 0x40
1438 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT           6
1439 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY                0x08
1440 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT          3
1441 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N                         0x04
1442 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT                   2
1443 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN                        0x02
1444 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT                  1
1445 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN                     0x01
1446 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT               0
1447
1448 /* Bit definitions for PMU_SECONDARY_INT2 */
1449 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC                 0x20
1450 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT           5
1451 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC                 0x10
1452 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT           4
1453 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK                    0x02
1454 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT              1
1455 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK                    0x01
1456 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT              0
1457
1458 /* Registers for function RESOURCE */
1459 #define PALMAS_CLK32KG_CTRL                                     0x0
1460 #define PALMAS_CLK32KGAUDIO_CTRL                                0x1
1461 #define PALMAS_REGEN1_CTRL                                      0x2
1462 #define PALMAS_REGEN2_CTRL                                      0x3
1463 #define PALMAS_SYSEN1_CTRL                                      0x4
1464 #define PALMAS_SYSEN2_CTRL                                      0x5
1465 #define PALMAS_NSLEEP_RES_ASSIGN                                0x6
1466 #define PALMAS_NSLEEP_SMPS_ASSIGN                               0x7
1467 #define PALMAS_NSLEEP_LDO_ASSIGN1                               0x8
1468 #define PALMAS_NSLEEP_LDO_ASSIGN2                               0x9
1469 #define PALMAS_ENABLE1_RES_ASSIGN                               0xA
1470 #define PALMAS_ENABLE1_SMPS_ASSIGN                              0xB
1471 #define PALMAS_ENABLE1_LDO_ASSIGN1                              0xC
1472 #define PALMAS_ENABLE1_LDO_ASSIGN2                              0xD
1473 #define PALMAS_ENABLE2_RES_ASSIGN                               0xE
1474 #define PALMAS_ENABLE2_SMPS_ASSIGN                              0xF
1475 #define PALMAS_ENABLE2_LDO_ASSIGN1                              0x10
1476 #define PALMAS_ENABLE2_LDO_ASSIGN2                              0x11
1477 #define PALMAS_REGEN3_CTRL                                      0x12
1478
1479 /* Bit definitions for CLK32KG_CTRL */
1480 #define PALMAS_CLK32KG_CTRL_STATUS                              0x10
1481 #define PALMAS_CLK32KG_CTRL_STATUS_SHIFT                        4
1482 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP                          0x04
1483 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT                    2
1484 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE                         0x01
1485 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT                   0
1486
1487 /* Bit definitions for CLK32KGAUDIO_CTRL */
1488 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS                         0x10
1489 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT                   4
1490 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3                      0x08
1491 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT                3
1492 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP                     0x04
1493 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT               2
1494 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE                    0x01
1495 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT              0
1496
1497 /* Bit definitions for REGEN1_CTRL */
1498 #define PALMAS_REGEN1_CTRL_STATUS                               0x10
1499 #define PALMAS_REGEN1_CTRL_STATUS_SHIFT                         4
1500 #define PALMAS_REGEN1_CTRL_MODE_SLEEP                           0x04
1501 #define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT                     2
1502 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE                          0x01
1503 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT                    0
1504
1505 /* Bit definitions for REGEN2_CTRL */
1506 #define PALMAS_REGEN2_CTRL_STATUS                               0x10
1507 #define PALMAS_REGEN2_CTRL_STATUS_SHIFT                         4
1508 #define PALMAS_REGEN2_CTRL_MODE_SLEEP                           0x04
1509 #define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT                     2
1510 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE                          0x01
1511 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT                    0
1512
1513 /* Bit definitions for SYSEN1_CTRL */
1514 #define PALMAS_SYSEN1_CTRL_STATUS                               0x10
1515 #define PALMAS_SYSEN1_CTRL_STATUS_SHIFT                         4
1516 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP                           0x04
1517 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT                     2
1518 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE                          0x01
1519 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT                    0
1520
1521 /* Bit definitions for SYSEN2_CTRL */
1522 #define PALMAS_SYSEN2_CTRL_STATUS                               0x10
1523 #define PALMAS_SYSEN2_CTRL_STATUS_SHIFT                         4
1524 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP                           0x04
1525 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT                     2
1526 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE                          0x01
1527 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT                    0
1528
1529 /* Bit definitions for NSLEEP_RES_ASSIGN */
1530 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3                         0x40
1531 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT                   6
1532 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO                   0x20
1533 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT             5
1534 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG                        0x10
1535 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT                  4
1536 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2                         0x08
1537 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT                   3
1538 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1                         0x04
1539 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT                   2
1540 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2                         0x02
1541 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT                   1
1542 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1                         0x01
1543 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT                   0
1544
1545 /* Bit definitions for NSLEEP_SMPS_ASSIGN */
1546 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10                        0x80
1547 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT                  7
1548 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9                         0x40
1549 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT                   6
1550 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8                         0x20
1551 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT                   5
1552 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7                         0x10
1553 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT                   4
1554 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6                         0x08
1555 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT                   3
1556 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45                        0x04
1557 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT                  2
1558 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3                         0x02
1559 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT                   1
1560 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12                        0x01
1561 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT                  0
1562
1563 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */
1564 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8                          0x80
1565 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT                    7
1566 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7                          0x40
1567 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT                    6
1568 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6                          0x20
1569 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT                    5
1570 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5                          0x10
1571 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT                    4
1572 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4                          0x08
1573 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT                    3
1574 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3                          0x04
1575 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT                    2
1576 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2                          0x02
1577 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT                    1
1578 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1                          0x01
1579 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT                    0
1580
1581 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */
1582 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB                        0x04
1583 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT                  2
1584 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN                         0x02
1585 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT                   1
1586 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9                          0x01
1587 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT                    0
1588
1589 /* Bit definitions for ENABLE1_RES_ASSIGN */
1590 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3                        0x40
1591 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT                  6
1592 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO                  0x20
1593 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT            5
1594 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG                       0x10
1595 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT                 4
1596 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2                        0x08
1597 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT                  3
1598 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1                        0x04
1599 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT                  2
1600 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2                        0x02
1601 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT                  1
1602 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1                        0x01
1603 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT                  0
1604
1605 /* Bit definitions for ENABLE1_SMPS_ASSIGN */
1606 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10                       0x80
1607 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT                 7
1608 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9                        0x40
1609 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT                  6
1610 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8                        0x20
1611 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT                  5
1612 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7                        0x10
1613 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT                  4
1614 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6                        0x08
1615 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT                  3
1616 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45                       0x04
1617 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT                 2
1618 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3                        0x02
1619 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT                  1
1620 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12                       0x01
1621 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT                 0
1622
1623 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */
1624 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8                         0x80
1625 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT                   7
1626 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7                         0x40
1627 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT                   6
1628 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6                         0x20
1629 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT                   5
1630 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5                         0x10
1631 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT                   4
1632 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4                         0x08
1633 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT                   3
1634 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3                         0x04
1635 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT                   2
1636 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2                         0x02
1637 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT                   1
1638 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1                         0x01
1639 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT                   0
1640
1641 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */
1642 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB                       0x04
1643 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT                 2
1644 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN                        0x02
1645 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT                  1
1646 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9                         0x01
1647 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT                   0
1648
1649 /* Bit definitions for ENABLE2_RES_ASSIGN */
1650 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3                        0x40
1651 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT                  6
1652 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO                  0x20
1653 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT            5
1654 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG                       0x10
1655 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT                 4
1656 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2                        0x08
1657 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT                  3
1658 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1                        0x04
1659 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT                  2
1660 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2                        0x02
1661 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT                  1
1662 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1                        0x01
1663 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT                  0
1664
1665 /* Bit definitions for ENABLE2_SMPS_ASSIGN */
1666 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10                       0x80
1667 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT                 7
1668 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9                        0x40
1669 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT                  6
1670 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8                        0x20
1671 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT                  5
1672 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7                        0x10
1673 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT                  4
1674 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6                        0x08
1675 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT                  3
1676 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45                       0x04
1677 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT                 2
1678 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3                        0x02
1679 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT                  1
1680 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12                       0x01
1681 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT                 0
1682
1683 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */
1684 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8                         0x80
1685 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT                   7
1686 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7                         0x40
1687 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT                   6
1688 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6                         0x20
1689 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT                   5
1690 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5                         0x10
1691 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT                   4
1692 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4                         0x08
1693 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT                   3
1694 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3                         0x04
1695 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT                   2
1696 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2                         0x02
1697 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT                   1
1698 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1                         0x01
1699 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT                   0
1700
1701 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */
1702 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB                       0x04
1703 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT                 2
1704 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN                        0x02
1705 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT                  1
1706 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9                         0x01
1707 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT                   0
1708
1709 /* Bit definitions for REGEN3_CTRL */
1710 #define PALMAS_REGEN3_CTRL_STATUS                               0x10
1711 #define PALMAS_REGEN3_CTRL_STATUS_SHIFT                         4
1712 #define PALMAS_REGEN3_CTRL_MODE_SLEEP                           0x04
1713 #define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT                     2
1714 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE                          0x01
1715 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT                    0
1716
1717 /* Registers for function PAD_CONTROL */
1718 #define PALMAS_PU_PD_INPUT_CTRL1                                0x0
1719 #define PALMAS_PU_PD_INPUT_CTRL2                                0x1
1720 #define PALMAS_PU_PD_INPUT_CTRL3                                0x2
1721 #define PALMAS_OD_OUTPUT_CTRL                                   0x4
1722 #define PALMAS_POLARITY_CTRL                                    0x5
1723 #define PALMAS_PRIMARY_SECONDARY_PAD1                           0x6
1724 #define PALMAS_PRIMARY_SECONDARY_PAD2                           0x7
1725 #define PALMAS_I2C_SPI                                          0x8
1726 #define PALMAS_PU_PD_INPUT_CTRL4                                0x9
1727 #define PALMAS_PRIMARY_SECONDARY_PAD3                           0xA
1728
1729 /* Bit definitions for PU_PD_INPUT_CTRL1 */
1730 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD                    0x40
1731 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT              6
1732 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU                 0x20
1733 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT           5
1734 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD                 0x10
1735 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT           4
1736 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD                     0x04
1737 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT               2
1738 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU                    0x02
1739 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT              1
1740
1741 /* Bit definitions for PU_PD_INPUT_CTRL2 */
1742 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU                     0x20
1743 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT               5
1744 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD                     0x10
1745 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT               4
1746 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU                     0x08
1747 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT               3
1748 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD                     0x04
1749 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT               2
1750 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU                      0x02
1751 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT                1
1752 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD                      0x01
1753 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT                0
1754
1755 /* Bit definitions for PU_PD_INPUT_CTRL3 */
1756 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD                        0x40
1757 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT                  6
1758 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD                  0x10
1759 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT            4
1760 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD                   0x04
1761 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT             2
1762 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD                     0x01
1763 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT               0
1764
1765 /* Bit definitions for OD_OUTPUT_CTRL */
1766 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD                          0x80
1767 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT                    7
1768 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD                        0x40
1769 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT                  6
1770 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD                          0x20
1771 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT                    5
1772 #define PALMAS_OD_OUTPUT_CTRL_INT_OD                            0x08
1773 #define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT                      3
1774
1775 /* Bit definitions for POLARITY_CTRL */
1776 #define PALMAS_POLARITY_CTRL_INT_POLARITY                       0x80
1777 #define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT                 7
1778 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY                   0x40
1779 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT             6
1780 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY                   0x20
1781 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT             5
1782 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY                    0x10
1783 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT              4
1784 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY                  0x08
1785 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT            3
1786 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY         0x04
1787 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT   2
1788 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY        0x02
1789 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT  1
1790 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY                   0x01
1791 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT             0
1792
1793 /* Bit definitions for PRIMARY_SECONDARY_PAD1 */
1794 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3                    0x80
1795 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT              7
1796 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK               0x60
1797 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT              5
1798 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK               0x18
1799 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT              3
1800 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0                    0x04
1801 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT              2
1802 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC                       0x02
1803 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT                 1
1804 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD                 0x01
1805 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT           0
1806
1807 /* Bit definitions for PRIMARY_SECONDARY_PAD2 */
1808 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK               0x30
1809 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT              4
1810 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6                    0x08
1811 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT              3
1812 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK               0x06
1813 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT              1
1814 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4                    0x01
1815 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT              0
1816
1817 /* Bit definitions for I2C_SPI */
1818 #define PALMAS_I2C_SPI_I2C2OTP_EN                               0x80
1819 #define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT                         7
1820 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL                          0x40
1821 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT                    6
1822 #define PALMAS_I2C_SPI_ID_I2C2                                  0x20
1823 #define PALMAS_I2C_SPI_ID_I2C2_SHIFT                            5
1824 #define PALMAS_I2C_SPI_I2C_SPI                                  0x10
1825 #define PALMAS_I2C_SPI_I2C_SPI_SHIFT                            4
1826 #define PALMAS_I2C_SPI_ID_I2C1_MASK                             0x0f
1827 #define PALMAS_I2C_SPI_ID_I2C1_SHIFT                            0
1828
1829 /* Bit definitions for PU_PD_INPUT_CTRL4 */
1830 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD                   0x40
1831 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT             6
1832 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD                   0x10
1833 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT             4
1834 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD                   0x04
1835 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT             2
1836 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD                   0x01
1837 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT             0
1838
1839 /* Bit definitions for PRIMARY_SECONDARY_PAD3 */
1840 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2                     0x02
1841 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT               1
1842 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1                     0x01
1843 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT               0
1844
1845 /* Registers for function LED_PWM */
1846 #define PALMAS_LED_PERIOD_CTRL                                  0x0
1847 #define PALMAS_LED_CTRL                                         0x1
1848 #define PALMAS_PWM_CTRL1                                        0x2
1849 #define PALMAS_PWM_CTRL2                                        0x3
1850
1851 /* Bit definitions for LED_PERIOD_CTRL */
1852 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK                0x38
1853 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT               3
1854 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK                0x07
1855 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT               0
1856
1857 /* Bit definitions for LED_CTRL */
1858 #define PALMAS_LED_CTRL_LED_2_SEQ                               0x20
1859 #define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT                         5
1860 #define PALMAS_LED_CTRL_LED_1_SEQ                               0x10
1861 #define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT                         4
1862 #define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK                      0x0c
1863 #define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT                     2
1864 #define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK                      0x03
1865 #define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT                     0
1866
1867 /* Bit definitions for PWM_CTRL1 */
1868 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN                            0x02
1869 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT                      1
1870 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL                           0x01
1871 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT                     0
1872
1873 /* Bit definitions for PWM_CTRL2 */
1874 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK                      0xff
1875 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT                     0
1876
1877 /* Registers for function INTERRUPT */
1878 #define PALMAS_INT1_STATUS                                      0x0
1879 #define PALMAS_INT1_MASK                                        0x1
1880 #define PALMAS_INT1_LINE_STATE                                  0x2
1881 #define PALMAS_INT1_EDGE_DETECT1_RESERVED                       0x3
1882 #define PALMAS_INT1_EDGE_DETECT2_RESERVED                       0x4
1883 #define PALMAS_INT2_STATUS                                      0x5
1884 #define PALMAS_INT2_MASK                                        0x6
1885 #define PALMAS_INT2_LINE_STATE                                  0x7
1886 #define PALMAS_INT2_EDGE_DETECT1_RESERVED                       0x8
1887 #define PALMAS_INT2_EDGE_DETECT2_RESERVED                       0x9
1888 #define PALMAS_INT3_STATUS                                      0xA
1889 #define PALMAS_INT3_MASK                                        0xB
1890 #define PALMAS_INT3_LINE_STATE                                  0xC
1891 #define PALMAS_INT3_EDGE_DETECT1_RESERVED                       0xD
1892 #define PALMAS_INT3_EDGE_DETECT2_RESERVED                       0xE
1893 #define PALMAS_INT4_STATUS                                      0xF
1894 #define PALMAS_INT4_MASK                                        0x10
1895 #define PALMAS_INT4_LINE_STATE                                  0x11
1896 #define PALMAS_INT4_EDGE_DETECT1                                0x12
1897 #define PALMAS_INT4_EDGE_DETECT2                                0x13
1898 #define PALMAS_INT_CTRL                                         0x14
1899
1900 /* Bit definitions for INT1_STATUS */
1901 #define PALMAS_INT1_STATUS_VBAT_MON                             0x80
1902 #define PALMAS_INT1_STATUS_VBAT_MON_SHIFT                       7
1903 #define PALMAS_INT1_STATUS_VSYS_MON                             0x40
1904 #define PALMAS_INT1_STATUS_VSYS_MON_SHIFT                       6
1905 #define PALMAS_INT1_STATUS_HOTDIE                               0x20
1906 #define PALMAS_INT1_STATUS_HOTDIE_SHIFT                         5
1907 #define PALMAS_INT1_STATUS_PWRDOWN                              0x10
1908 #define PALMAS_INT1_STATUS_PWRDOWN_SHIFT                        4
1909 #define PALMAS_INT1_STATUS_RPWRON                               0x08
1910 #define PALMAS_INT1_STATUS_RPWRON_SHIFT                         3
1911 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY                       0x04
1912 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT                 2
1913 #define PALMAS_INT1_STATUS_PWRON                                0x02
1914 #define PALMAS_INT1_STATUS_PWRON_SHIFT                          1
1915 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV                 0x01
1916 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT           0
1917
1918 /* Bit definitions for INT1_MASK */
1919 #define PALMAS_INT1_MASK_VBAT_MON                               0x80
1920 #define PALMAS_INT1_MASK_VBAT_MON_SHIFT                         7
1921 #define PALMAS_INT1_MASK_VSYS_MON                               0x40
1922 #define PALMAS_INT1_MASK_VSYS_MON_SHIFT                         6
1923 #define PALMAS_INT1_MASK_HOTDIE                                 0x20
1924 #define PALMAS_INT1_MASK_HOTDIE_SHIFT                           5
1925 #define PALMAS_INT1_MASK_PWRDOWN                                0x10
1926 #define PALMAS_INT1_MASK_PWRDOWN_SHIFT                          4
1927 #define PALMAS_INT1_MASK_RPWRON                                 0x08
1928 #define PALMAS_INT1_MASK_RPWRON_SHIFT                           3
1929 #define PALMAS_INT1_MASK_LONG_PRESS_KEY                         0x04
1930 #define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT                   2
1931 #define PALMAS_INT1_MASK_PWRON                                  0x02
1932 #define PALMAS_INT1_MASK_PWRON_SHIFT                            1
1933 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV                   0x01
1934 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT             0
1935
1936 /* Bit definitions for INT1_LINE_STATE */
1937 #define PALMAS_INT1_LINE_STATE_VBAT_MON                         0x80
1938 #define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT                   7
1939 #define PALMAS_INT1_LINE_STATE_VSYS_MON                         0x40
1940 #define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT                   6
1941 #define PALMAS_INT1_LINE_STATE_HOTDIE                           0x20
1942 #define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT                     5
1943 #define PALMAS_INT1_LINE_STATE_PWRDOWN                          0x10
1944 #define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT                    4
1945 #define PALMAS_INT1_LINE_STATE_RPWRON                           0x08
1946 #define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT                     3
1947 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY                   0x04
1948 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT             2
1949 #define PALMAS_INT1_LINE_STATE_PWRON                            0x02
1950 #define PALMAS_INT1_LINE_STATE_PWRON_SHIFT                      1
1951 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV             0x01
1952 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT       0
1953
1954 /* Bit definitions for INT2_STATUS */
1955 #define PALMAS_INT2_STATUS_VAC_ACOK                             0x80
1956 #define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT                       7
1957 #define PALMAS_INT2_STATUS_SHORT                                0x40
1958 #define PALMAS_INT2_STATUS_SHORT_SHIFT                          6
1959 #define PALMAS_INT2_STATUS_FBI_BB                               0x20
1960 #define PALMAS_INT2_STATUS_FBI_BB_SHIFT                         5
1961 #define PALMAS_INT2_STATUS_RESET_IN                             0x10
1962 #define PALMAS_INT2_STATUS_RESET_IN_SHIFT                       4
1963 #define PALMAS_INT2_STATUS_BATREMOVAL                           0x08
1964 #define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT                     3
1965 #define PALMAS_INT2_STATUS_WDT                                  0x04
1966 #define PALMAS_INT2_STATUS_WDT_SHIFT                            2
1967 #define PALMAS_INT2_STATUS_RTC_TIMER                            0x02
1968 #define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT                      1
1969 #define PALMAS_INT2_STATUS_RTC_ALARM                            0x01
1970 #define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT                      0
1971
1972 /* Bit definitions for INT2_MASK */
1973 #define PALMAS_INT2_MASK_VAC_ACOK                               0x80
1974 #define PALMAS_INT2_MASK_VAC_ACOK_SHIFT                         7
1975 #define PALMAS_INT2_MASK_SHORT                                  0x40
1976 #define PALMAS_INT2_MASK_SHORT_SHIFT                            6
1977 #define PALMAS_INT2_MASK_FBI_BB                                 0x20
1978 #define PALMAS_INT2_MASK_FBI_BB_SHIFT                           5
1979 #define PALMAS_INT2_MASK_RESET_IN                               0x10
1980 #define PALMAS_INT2_MASK_RESET_IN_SHIFT                         4
1981 #define PALMAS_INT2_MASK_BATREMOVAL                             0x08
1982 #define PALMAS_INT2_MASK_BATREMOVAL_SHIFT                       3
1983 #define PALMAS_INT2_MASK_WDT                                    0x04
1984 #define PALMAS_INT2_MASK_WDT_SHIFT                              2
1985 #define PALMAS_INT2_MASK_RTC_TIMER                              0x02
1986 #define PALMAS_INT2_MASK_RTC_TIMER_SHIFT                        1
1987 #define PALMAS_INT2_MASK_RTC_ALARM                              0x01
1988 #define PALMAS_INT2_MASK_RTC_ALARM_SHIFT                        0
1989
1990 /* Bit definitions for INT2_LINE_STATE */
1991 #define PALMAS_INT2_LINE_STATE_VAC_ACOK                         0x80
1992 #define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT                   7
1993 #define PALMAS_INT2_LINE_STATE_SHORT                            0x40
1994 #define PALMAS_INT2_LINE_STATE_SHORT_SHIFT                      6
1995 #define PALMAS_INT2_LINE_STATE_FBI_BB                           0x20
1996 #define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT                     5
1997 #define PALMAS_INT2_LINE_STATE_RESET_IN                         0x10
1998 #define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT                   4
1999 #define PALMAS_INT2_LINE_STATE_BATREMOVAL                       0x08
2000 #define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT                 3
2001 #define PALMAS_INT2_LINE_STATE_WDT                              0x04
2002 #define PALMAS_INT2_LINE_STATE_WDT_SHIFT                        2
2003 #define PALMAS_INT2_LINE_STATE_RTC_TIMER                        0x02
2004 #define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT                  1
2005 #define PALMAS_INT2_LINE_STATE_RTC_ALARM                        0x01
2006 #define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT                  0
2007
2008 /* Bit definitions for INT3_STATUS */
2009 #define PALMAS_INT3_STATUS_VBUS                                 0x80
2010 #define PALMAS_INT3_STATUS_VBUS_SHIFT                           7
2011 #define PALMAS_INT3_STATUS_VBUS_OTG                             0x40
2012 #define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT                       6
2013 #define PALMAS_INT3_STATUS_ID                                   0x20
2014 #define PALMAS_INT3_STATUS_ID_SHIFT                             5
2015 #define PALMAS_INT3_STATUS_ID_OTG                               0x10
2016 #define PALMAS_INT3_STATUS_ID_OTG_SHIFT                         4
2017 #define PALMAS_INT3_STATUS_GPADC_EOC_RT                         0x08
2018 #define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT                   3
2019 #define PALMAS_INT3_STATUS_GPADC_EOC_SW                         0x04
2020 #define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT                   2
2021 #define PALMAS_INT3_STATUS_GPADC_AUTO_1                         0x02
2022 #define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT                   1
2023 #define PALMAS_INT3_STATUS_GPADC_AUTO_0                         0x01
2024 #define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT                   0
2025
2026 /* Bit definitions for INT3_MASK */
2027 #define PALMAS_INT3_MASK_VBUS                                   0x80
2028 #define PALMAS_INT3_MASK_VBUS_SHIFT                             7
2029 #define PALMAS_INT3_MASK_VBUS_OTG                               0x40
2030 #define PALMAS_INT3_MASK_VBUS_OTG_SHIFT                         6
2031 #define PALMAS_INT3_MASK_ID                                     0x20
2032 #define PALMAS_INT3_MASK_ID_SHIFT                               5
2033 #define PALMAS_INT3_MASK_ID_OTG                                 0x10
2034 #define PALMAS_INT3_MASK_ID_OTG_SHIFT                           4
2035 #define PALMAS_INT3_MASK_GPADC_EOC_RT                           0x08
2036 #define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT                     3
2037 #define PALMAS_INT3_MASK_GPADC_EOC_SW                           0x04
2038 #define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT                     2
2039 #define PALMAS_INT3_MASK_GPADC_AUTO_1                           0x02
2040 #define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT                     1
2041 #define PALMAS_INT3_MASK_GPADC_AUTO_0                           0x01
2042 #define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT                     0
2043
2044 /* Bit definitions for INT3_LINE_STATE */
2045 #define PALMAS_INT3_LINE_STATE_VBUS                             0x80
2046 #define PALMAS_INT3_LINE_STATE_VBUS_SHIFT                       7
2047 #define PALMAS_INT3_LINE_STATE_VBUS_OTG                         0x40
2048 #define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT                   6
2049 #define PALMAS_INT3_LINE_STATE_ID                               0x20
2050 #define PALMAS_INT3_LINE_STATE_ID_SHIFT                         5
2051 #define PALMAS_INT3_LINE_STATE_ID_OTG                           0x10
2052 #define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT                     4
2053 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT                     0x08
2054 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT               3
2055 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW                     0x04
2056 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT               2
2057 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1                     0x02
2058 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT               1
2059 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0                     0x01
2060 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT               0
2061
2062 /* Bit definitions for INT4_STATUS */
2063 #define PALMAS_INT4_STATUS_GPIO_7                               0x80
2064 #define PALMAS_INT4_STATUS_GPIO_7_SHIFT                         7
2065 #define PALMAS_INT4_STATUS_GPIO_6                               0x40
2066 #define PALMAS_INT4_STATUS_GPIO_6_SHIFT                         6
2067 #define PALMAS_INT4_STATUS_GPIO_5                               0x20
2068 #define PALMAS_INT4_STATUS_GPIO_5_SHIFT                         5
2069 #define PALMAS_INT4_STATUS_GPIO_4                               0x10
2070 #define PALMAS_INT4_STATUS_GPIO_4_SHIFT                         4
2071 #define PALMAS_INT4_STATUS_GPIO_3                               0x08
2072 #define PALMAS_INT4_STATUS_GPIO_3_SHIFT                         3
2073 #define PALMAS_INT4_STATUS_GPIO_2                               0x04
2074 #define PALMAS_INT4_STATUS_GPIO_2_SHIFT                         2
2075 #define PALMAS_INT4_STATUS_GPIO_1                               0x02
2076 #define PALMAS_INT4_STATUS_GPIO_1_SHIFT                         1
2077 #define PALMAS_INT4_STATUS_GPIO_0                               0x01
2078 #define PALMAS_INT4_STATUS_GPIO_0_SHIFT                         0
2079
2080 /* Bit definitions for INT4_MASK */
2081 #define PALMAS_INT4_MASK_GPIO_7                                 0x80
2082 #define PALMAS_INT4_MASK_GPIO_7_SHIFT                           7
2083 #define PALMAS_INT4_MASK_GPIO_6                                 0x40
2084 #define PALMAS_INT4_MASK_GPIO_6_SHIFT                           6
2085 #define PALMAS_INT4_MASK_GPIO_5                                 0x20
2086 #define PALMAS_INT4_MASK_GPIO_5_SHIFT                           5
2087 #define PALMAS_INT4_MASK_GPIO_4                                 0x10
2088 #define PALMAS_INT4_MASK_GPIO_4_SHIFT                           4
2089 #define PALMAS_INT4_MASK_GPIO_3                                 0x08
2090 #define PALMAS_INT4_MASK_GPIO_3_SHIFT                           3
2091 #define PALMAS_INT4_MASK_GPIO_2                                 0x04
2092 #define PALMAS_INT4_MASK_GPIO_2_SHIFT                           2
2093 #define PALMAS_INT4_MASK_GPIO_1                                 0x02
2094 #define PALMAS_INT4_MASK_GPIO_1_SHIFT                           1
2095 #define PALMAS_INT4_MASK_GPIO_0                                 0x01
2096 #define PALMAS_INT4_MASK_GPIO_0_SHIFT                           0
2097
2098 /* Bit definitions for INT4_LINE_STATE */
2099 #define PALMAS_INT4_LINE_STATE_GPIO_7                           0x80
2100 #define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT                     7
2101 #define PALMAS_INT4_LINE_STATE_GPIO_6                           0x40
2102 #define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT                     6
2103 #define PALMAS_INT4_LINE_STATE_GPIO_5                           0x20
2104 #define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT                     5
2105 #define PALMAS_INT4_LINE_STATE_GPIO_4                           0x10
2106 #define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT                     4
2107 #define PALMAS_INT4_LINE_STATE_GPIO_3                           0x08
2108 #define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT                     3
2109 #define PALMAS_INT4_LINE_STATE_GPIO_2                           0x04
2110 #define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT                     2
2111 #define PALMAS_INT4_LINE_STATE_GPIO_1                           0x02
2112 #define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT                     1
2113 #define PALMAS_INT4_LINE_STATE_GPIO_0                           0x01
2114 #define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT                     0
2115
2116 /* Bit definitions for INT4_EDGE_DETECT1 */
2117 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING                  0x80
2118 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT            7
2119 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING                 0x40
2120 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT           6
2121 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING                  0x20
2122 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT            5
2123 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING                 0x10
2124 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT           4
2125 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING                  0x08
2126 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT            3
2127 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING                 0x04
2128 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT           2
2129 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING                  0x02
2130 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT            1
2131 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING                 0x01
2132 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT           0
2133
2134 /* Bit definitions for INT4_EDGE_DETECT2 */
2135 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING                  0x80
2136 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT            7
2137 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING                 0x40
2138 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT           6
2139 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING                  0x20
2140 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT            5
2141 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING                 0x10
2142 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT           4
2143 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING                  0x08
2144 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT            3
2145 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING                 0x04
2146 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT           2
2147 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING                  0x02
2148 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT            1
2149 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING                 0x01
2150 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT           0
2151
2152 /* Bit definitions for INT_CTRL */
2153 #define PALMAS_INT_CTRL_INT_PENDING                             0x04
2154 #define PALMAS_INT_CTRL_INT_PENDING_SHIFT                       2
2155 #define PALMAS_INT_CTRL_INT_CLEAR                               0x01
2156 #define PALMAS_INT_CTRL_INT_CLEAR_SHIFT                         0
2157
2158 /* Registers for function USB_OTG */
2159 #define PALMAS_USB_WAKEUP                                       0x3
2160 #define PALMAS_USB_VBUS_CTRL_SET                                0x4
2161 #define PALMAS_USB_VBUS_CTRL_CLR                                0x5
2162 #define PALMAS_USB_ID_CTRL_SET                                  0x6
2163 #define PALMAS_USB_ID_CTRL_CLEAR                                0x7
2164 #define PALMAS_USB_VBUS_INT_SRC                                 0x8
2165 #define PALMAS_USB_VBUS_INT_LATCH_SET                           0x9
2166 #define PALMAS_USB_VBUS_INT_LATCH_CLR                           0xA
2167 #define PALMAS_USB_VBUS_INT_EN_LO_SET                           0xB
2168 #define PALMAS_USB_VBUS_INT_EN_LO_CLR                           0xC
2169 #define PALMAS_USB_VBUS_INT_EN_HI_SET                           0xD
2170 #define PALMAS_USB_VBUS_INT_EN_HI_CLR                           0xE
2171 #define PALMAS_USB_ID_INT_SRC                                   0xF
2172 #define PALMAS_USB_ID_INT_LATCH_SET                             0x10
2173 #define PALMAS_USB_ID_INT_LATCH_CLR                             0x11
2174 #define PALMAS_USB_ID_INT_EN_LO_SET                             0x12
2175 #define PALMAS_USB_ID_INT_EN_LO_CLR                             0x13
2176 #define PALMAS_USB_ID_INT_EN_HI_SET                             0x14
2177 #define PALMAS_USB_ID_INT_EN_HI_CLR                             0x15
2178 #define PALMAS_USB_OTG_ADP_CTRL                                 0x16
2179 #define PALMAS_USB_OTG_ADP_HIGH                                 0x17
2180 #define PALMAS_USB_OTG_ADP_LOW                                  0x18
2181 #define PALMAS_USB_OTG_ADP_RISE                                 0x19
2182 #define PALMAS_USB_OTG_REVISION                                 0x1A
2183
2184 /* Bit definitions for USB_WAKEUP */
2185 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP                         0x01
2186 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT                   0
2187
2188 /* Bit definitions for USB_VBUS_CTRL_SET */
2189 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS                 0x80
2190 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT           7
2191 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG                   0x20
2192 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT             5
2193 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC                  0x10
2194 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT            4
2195 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK                 0x08
2196 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT           3
2197 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP                  0x04
2198 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT            2
2199
2200 /* Bit definitions for USB_VBUS_CTRL_CLR */
2201 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS                 0x80
2202 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT           7
2203 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG                   0x20
2204 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT             5
2205 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC                  0x10
2206 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT            4
2207 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK                 0x08
2208 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT           3
2209 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP                  0x04
2210 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT            2
2211
2212 /* Bit definitions for USB_ID_CTRL_SET */
2213 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K                       0x80
2214 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT                 7
2215 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K                       0x40
2216 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT                 6
2217 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV                       0x20
2218 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT                 5
2219 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U                       0x10
2220 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT                 4
2221 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U                        0x08
2222 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT                  3
2223 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP                      0x04
2224 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT                2
2225
2226 /* Bit definitions for USB_ID_CTRL_CLEAR */
2227 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K                     0x80
2228 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT               7
2229 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K                     0x40
2230 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT               6
2231 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV                     0x20
2232 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT               5
2233 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U                     0x10
2234 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT               4
2235 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U                      0x08
2236 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT                3
2237 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP                    0x04
2238 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT              2
2239
2240 /* Bit definitions for USB_VBUS_INT_SRC */
2241 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD                   0x80
2242 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT             7
2243 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB                        0x40
2244 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT                  6
2245 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS                        0x20
2246 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT                  5
2247 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD                     0x08
2248 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT               3
2249 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD                     0x04
2250 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT               2
2251 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD                     0x02
2252 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT               1
2253 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END                     0x01
2254 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT               0
2255
2256 /* Bit definitions for USB_VBUS_INT_LATCH_SET */
2257 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD             0x80
2258 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT       7
2259 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB                  0x40
2260 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT            6
2261 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS                  0x20
2262 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT            5
2263 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP                       0x10
2264 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT                 4
2265 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD               0x08
2266 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT         3
2267 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD               0x04
2268 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT         2
2269 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD               0x02
2270 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT         1
2271 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END               0x01
2272 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT         0
2273
2274 /* Bit definitions for USB_VBUS_INT_LATCH_CLR */
2275 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD             0x80
2276 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT       7
2277 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB                  0x40
2278 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT            6
2279 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS                  0x20
2280 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT            5
2281 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP                       0x10
2282 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT                 4
2283 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD               0x08
2284 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT         3
2285 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD               0x04
2286 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT         2
2287 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD               0x02
2288 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT         1
2289 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END               0x01
2290 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT         0
2291
2292 /* Bit definitions for USB_VBUS_INT_EN_LO_SET */
2293 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD             0x80
2294 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT       7
2295 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB                  0x40
2296 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT            6
2297 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS                  0x20
2298 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT            5
2299 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD               0x08
2300 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT         3
2301 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD               0x04
2302 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT         2
2303 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD               0x02
2304 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT         1
2305 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END               0x01
2306 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT         0
2307
2308 /* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
2309 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD             0x80
2310 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT       7
2311 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB                  0x40
2312 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT            6
2313 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS                  0x20
2314 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT            5
2315 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD               0x08
2316 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT         3
2317 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD               0x04
2318 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT         2
2319 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD               0x02
2320 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT         1
2321 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END               0x01
2322 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT         0
2323
2324 /* Bit definitions for USB_VBUS_INT_EN_HI_SET */
2325 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD             0x80
2326 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT       7
2327 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB                  0x40
2328 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT            6
2329 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS                  0x20
2330 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT            5
2331 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP                       0x10
2332 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT                 4
2333 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD               0x08
2334 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT         3
2335 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD               0x04
2336 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT         2
2337 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD               0x02
2338 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT         1
2339 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END               0x01
2340 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT         0
2341
2342 /* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
2343 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD             0x80
2344 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT       7
2345 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB                  0x40
2346 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT            6
2347 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS                  0x20
2348 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT            5
2349 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP                       0x10
2350 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT                 4
2351 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD               0x08
2352 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT         3
2353 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD               0x04
2354 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT         2
2355 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD               0x02
2356 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT         1
2357 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END               0x01
2358 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT         0
2359
2360 /* Bit definitions for USB_ID_INT_SRC */
2361 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT                          0x10
2362 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT                    4
2363 #define PALMAS_USB_ID_INT_SRC_ID_A                              0x08
2364 #define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT                        3
2365 #define PALMAS_USB_ID_INT_SRC_ID_B                              0x04
2366 #define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT                        2
2367 #define PALMAS_USB_ID_INT_SRC_ID_C                              0x02
2368 #define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT                        1
2369 #define PALMAS_USB_ID_INT_SRC_ID_GND                            0x01
2370 #define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT                      0
2371
2372 /* Bit definitions for USB_ID_INT_LATCH_SET */
2373 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT                    0x10
2374 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT              4
2375 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A                        0x08
2376 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT                  3
2377 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B                        0x04
2378 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT                  2
2379 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C                        0x02
2380 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT                  1
2381 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND                      0x01
2382 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT                0
2383
2384 /* Bit definitions for USB_ID_INT_LATCH_CLR */
2385 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT                    0x10
2386 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT              4
2387 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A                        0x08
2388 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT                  3
2389 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B                        0x04
2390 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT                  2
2391 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C                        0x02
2392 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT                  1
2393 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND                      0x01
2394 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT                0
2395
2396 /* Bit definitions for USB_ID_INT_EN_LO_SET */
2397 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT                    0x10
2398 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT              4
2399 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A                        0x08
2400 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT                  3
2401 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B                        0x04
2402 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT                  2
2403 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C                        0x02
2404 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT                  1
2405 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND                      0x01
2406 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT                0
2407
2408 /* Bit definitions for USB_ID_INT_EN_LO_CLR */
2409 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT                    0x10
2410 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT              4
2411 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A                        0x08
2412 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT                  3
2413 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B                        0x04
2414 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT                  2
2415 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C                        0x02
2416 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT                  1
2417 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND                      0x01
2418 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT                0
2419
2420 /* Bit definitions for USB_ID_INT_EN_HI_SET */
2421 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT                    0x10
2422 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT              4
2423 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A                        0x08
2424 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT                  3
2425 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B                        0x04
2426 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT                  2
2427 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C                        0x02
2428 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT                  1
2429 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND                      0x01
2430 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT                0
2431
2432 /* Bit definitions for USB_ID_INT_EN_HI_CLR */
2433 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT                    0x10
2434 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT              4
2435 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A                        0x08
2436 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT                  3
2437 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B                        0x04
2438 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT                  2
2439 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C                        0x02
2440 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT                  1
2441 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND                      0x01
2442 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT                0
2443
2444 /* Bit definitions for USB_OTG_ADP_CTRL */
2445 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN                          0x04
2446 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT                    2
2447 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK                   0x03
2448 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT                  0
2449
2450 /* Bit definitions for USB_OTG_ADP_HIGH */
2451 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK                 0xff
2452 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT                0
2453
2454 /* Bit definitions for USB_OTG_ADP_LOW */
2455 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK                   0xff
2456 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT                  0
2457
2458 /* Bit definitions for USB_OTG_ADP_RISE */
2459 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK                 0xff
2460 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT                0
2461
2462 /* Bit definitions for USB_OTG_REVISION */
2463 #define PALMAS_USB_OTG_REVISION_OTG_REV                         0x01
2464 #define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT                   0
2465
2466 /* Registers for function VIBRATOR */
2467 #define PALMAS_VIBRA_CTRL                                       0x0
2468
2469 /* Bit definitions for VIBRA_CTRL */
2470 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK                     0x06
2471 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT                    1
2472 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL                          0x01
2473 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT                    0
2474
2475 /* Registers for function GPIO */
2476 #define PALMAS_GPIO_DATA_IN                                     0x0
2477 #define PALMAS_GPIO_DATA_DIR                                    0x1
2478 #define PALMAS_GPIO_DATA_OUT                                    0x2
2479 #define PALMAS_GPIO_DEBOUNCE_EN                                 0x3
2480 #define PALMAS_GPIO_CLEAR_DATA_OUT                              0x4
2481 #define PALMAS_GPIO_SET_DATA_OUT                                0x5
2482 #define PALMAS_PU_PD_GPIO_CTRL1                                 0x6
2483 #define PALMAS_PU_PD_GPIO_CTRL2                                 0x7
2484 #define PALMAS_OD_OUTPUT_GPIO_CTRL                              0x8
2485
2486 /* Bit definitions for GPIO_DATA_IN */
2487 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN                           0x80
2488 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT                     7
2489 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN                           0x40
2490 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT                     6
2491 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN                           0x20
2492 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT                     5
2493 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN                           0x10
2494 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT                     4
2495 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN                           0x08
2496 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT                     3
2497 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN                           0x04
2498 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT                     2
2499 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN                           0x02
2500 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT                     1
2501 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN                           0x01
2502 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT                     0
2503
2504 /* Bit definitions for GPIO_DATA_DIR */
2505 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR                         0x80
2506 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT                   7
2507 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR                         0x40
2508 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT                   6
2509 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR                         0x20
2510 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT                   5
2511 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR                         0x10
2512 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT                   4
2513 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR                         0x08
2514 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT                   3
2515 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR                         0x04
2516 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT                   2
2517 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR                         0x02
2518 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT                   1
2519 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR                         0x01
2520 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT                   0
2521
2522 /* Bit definitions for GPIO_DATA_OUT */
2523 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT                         0x80
2524 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT                   7
2525 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT                         0x40
2526 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT                   6
2527 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT                         0x20
2528 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT                   5
2529 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT                         0x10
2530 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT                   4
2531 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT                         0x08
2532 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT                   3
2533 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT                         0x04
2534 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT                   2
2535 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT                         0x02
2536 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT                   1
2537 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT                         0x01
2538 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT                   0
2539
2540 /* Bit definitions for GPIO_DEBOUNCE_EN */
2541 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN              0x80
2542 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT        7
2543 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN              0x40
2544 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT        6
2545 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN              0x20
2546 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT        5
2547 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN              0x10
2548 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT        4
2549 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN              0x08
2550 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT        3
2551 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN              0x04
2552 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT        2
2553 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN              0x02
2554 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT        1
2555 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN              0x01
2556 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT        0
2557
2558 /* Bit definitions for GPIO_CLEAR_DATA_OUT */
2559 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT        0x80
2560 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT  7
2561 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT        0x40
2562 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT  6
2563 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT        0x20
2564 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT  5
2565 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT        0x10
2566 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT  4
2567 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT        0x08
2568 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT  3
2569 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT        0x04
2570 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT  2
2571 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT        0x02
2572 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT  1
2573 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT        0x01
2574 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT  0
2575
2576 /* Bit definitions for GPIO_SET_DATA_OUT */
2577 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT            0x80
2578 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT      7
2579 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT            0x40
2580 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT      6
2581 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT            0x20
2582 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT      5
2583 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT            0x10
2584 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT      4
2585 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT            0x08
2586 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT      3
2587 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT            0x04
2588 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT      2
2589 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT            0x02
2590 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT      1
2591 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT            0x01
2592 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT      0
2593
2594 /* Bit definitions for PU_PD_GPIO_CTRL1 */
2595 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD                       0x40
2596 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT                 6
2597 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU                       0x20
2598 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT                 5
2599 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD                       0x10
2600 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT                 4
2601 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU                       0x08
2602 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT                 3
2603 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD                       0x04
2604 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT                 2
2605 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD                       0x01
2606 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT                 0
2607
2608 /* Bit definitions for PU_PD_GPIO_CTRL2 */
2609 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD                       0x40
2610 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT                 6
2611 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU                       0x20
2612 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT                 5
2613 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD                       0x10
2614 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT                 4
2615 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU                       0x08
2616 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT                 3
2617 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD                       0x04
2618 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT                 2
2619 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU                       0x02
2620 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT                 1
2621 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD                       0x01
2622 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT                 0
2623
2624 /* Bit definitions for OD_OUTPUT_GPIO_CTRL */
2625 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD                    0x20
2626 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT              5
2627 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD                    0x04
2628 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT              2
2629 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD                    0x02
2630 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT              1
2631
2632 /* Registers for function GPADC */
2633 #define PALMAS_GPADC_CTRL1                                      0x0
2634 #define PALMAS_GPADC_CTRL2                                      0x1
2635 #define PALMAS_GPADC_RT_CTRL                                    0x2
2636 #define PALMAS_GPADC_AUTO_CTRL                                  0x3
2637 #define PALMAS_GPADC_STATUS                                     0x4
2638 #define PALMAS_GPADC_RT_SELECT                                  0x5
2639 #define PALMAS_GPADC_RT_CONV0_LSB                               0x6
2640 #define PALMAS_GPADC_RT_CONV0_MSB                               0x7
2641 #define PALMAS_GPADC_AUTO_SELECT                                0x8
2642 #define PALMAS_GPADC_AUTO_CONV0_LSB                             0x9
2643 #define PALMAS_GPADC_AUTO_CONV0_MSB                             0xA
2644 #define PALMAS_GPADC_AUTO_CONV1_LSB                             0xB
2645 #define PALMAS_GPADC_AUTO_CONV1_MSB                             0xC
2646 #define PALMAS_GPADC_SW_SELECT                                  0xD
2647 #define PALMAS_GPADC_SW_CONV0_LSB                               0xE
2648 #define PALMAS_GPADC_SW_CONV0_MSB                               0xF
2649 #define PALMAS_GPADC_THRES_CONV0_LSB                            0x10
2650 #define PALMAS_GPADC_THRES_CONV0_MSB                            0x11
2651 #define PALMAS_GPADC_THRES_CONV1_LSB                            0x12
2652 #define PALMAS_GPADC_THRES_CONV1_MSB                            0x13
2653 #define PALMAS_GPADC_SMPS_ILMONITOR_EN                          0x14
2654 #define PALMAS_GPADC_SMPS_VSEL_MONITORING                       0x15
2655
2656 /* Bit definitions for GPADC_CTRL1 */
2657 #define PALMAS_GPADC_CTRL1_RESERVED_MASK                        0xc0
2658 #define PALMAS_GPADC_CTRL1_RESERVED_SHIFT                       6
2659 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK                 0x30
2660 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT                4
2661 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK                 0x0c
2662 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT                2
2663 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET                      0x02
2664 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT                1
2665 #define PALMAS_GPADC_CTRL1_GPADC_FORCE                          0x01
2666 #define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT                    0
2667
2668 /* Bit definitions for GPADC_CTRL2 */
2669 #define PALMAS_GPADC_CTRL2_RESERVED_MASK                        0x06
2670 #define PALMAS_GPADC_CTRL2_RESERVED_SHIFT                       1
2671
2672 /* Bit definitions for GPADC_RT_CTRL */
2673 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY                       0x02
2674 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT                 1
2675 #define PALMAS_GPADC_RT_CTRL_START_POLARITY                     0x01
2676 #define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT               0
2677
2678 /* Bit definitions for GPADC_AUTO_CTRL */
2679 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1                   0x80
2680 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT             7
2681 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0                   0x40
2682 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT             6
2683 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN                    0x20
2684 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT              5
2685 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN                    0x10
2686 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT              4
2687 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK                0x0f
2688 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT               0
2689
2690 /* Bit definitions for GPADC_STATUS */
2691 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE                     0x10
2692 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT               4
2693
2694 /* Bit definitions for GPADC_RT_SELECT */
2695 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN                       0x80
2696 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT                 7
2697 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK                0x0f
2698 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT               0
2699
2700 /* Bit definitions for GPADC_RT_CONV0_LSB */
2701 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK             0xff
2702 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT            0
2703
2704 /* Bit definitions for GPADC_RT_CONV0_MSB */
2705 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK             0x0f
2706 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT            0
2707
2708 /* Bit definitions for GPADC_AUTO_SELECT */
2709 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK            0xf0
2710 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT           4
2711 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK            0x0f
2712 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT           0
2713
2714 /* Bit definitions for GPADC_AUTO_CONV0_LSB */
2715 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK         0xff
2716 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT        0
2717
2718 /* Bit definitions for GPADC_AUTO_CONV0_MSB */
2719 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK         0x0f
2720 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT        0
2721
2722 /* Bit definitions for GPADC_AUTO_CONV1_LSB */
2723 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK         0xff
2724 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT        0
2725
2726 /* Bit definitions for GPADC_AUTO_CONV1_MSB */
2727 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK         0x0f
2728 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT        0
2729
2730 /* Bit definitions for GPADC_SW_SELECT */
2731 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN                       0x80
2732 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT                 7
2733 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0                   0x10
2734 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT             4
2735 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK                0x0f
2736 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT               0
2737
2738 /* Bit definitions for GPADC_SW_CONV0_LSB */
2739 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK             0xff
2740 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT            0
2741
2742 /* Bit definitions for GPADC_SW_CONV0_MSB */
2743 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK             0x0f
2744 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT            0
2745
2746 /* Bit definitions for GPADC_THRES_CONV0_LSB */
2747 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK       0xff
2748 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT      0
2749
2750 /* Bit definitions for GPADC_THRES_CONV0_MSB */
2751 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL            0x80
2752 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT      7
2753 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK       0x0f
2754 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT      0
2755
2756 /* Bit definitions for GPADC_THRES_CONV1_LSB */
2757 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK       0xff
2758 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT      0
2759
2760 /* Bit definitions for GPADC_THRES_CONV1_MSB */
2761 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL            0x80
2762 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT      7
2763 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK       0x0f
2764 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT      0
2765
2766 /* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
2767 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN            0x20
2768 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT      5
2769 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT          0x10
2770 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT    4
2771 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK      0x0f
2772 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT     0
2773
2774 /* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
2775 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE          0x80
2776 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT    7
2777 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK     0x7f
2778 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT    0
2779
2780 /* Registers for function GPADC */
2781 #define PALMAS_GPADC_TRIM1                                      0x0
2782 #define PALMAS_GPADC_TRIM2                                      0x1
2783 #define PALMAS_GPADC_TRIM3                                      0x2
2784 #define PALMAS_GPADC_TRIM4                                      0x3
2785 #define PALMAS_GPADC_TRIM5                                      0x4
2786 #define PALMAS_GPADC_TRIM6                                      0x5
2787 #define PALMAS_GPADC_TRIM7                                      0x6
2788 #define PALMAS_GPADC_TRIM8                                      0x7
2789 #define PALMAS_GPADC_TRIM9                                      0x8
2790 #define PALMAS_GPADC_TRIM10                                     0x9
2791 #define PALMAS_GPADC_TRIM11                                     0xA
2792 #define PALMAS_GPADC_TRIM12                                     0xB
2793 #define PALMAS_GPADC_TRIM13                                     0xC
2794 #define PALMAS_GPADC_TRIM14                                     0xD
2795 #define PALMAS_GPADC_TRIM15                                     0xE
2796 #define PALMAS_GPADC_TRIM16                                     0xF
2797
2798 static inline int palmas_read(struct palmas *palmas, unsigned int base,
2799                 unsigned int reg, unsigned int *val)
2800 {
2801         unsigned int addr =  PALMAS_BASE_TO_REG(base, reg);
2802         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2803
2804         return regmap_read(palmas->regmap[slave_id], addr, val);
2805 }
2806
2807 static inline int palmas_write(struct palmas *palmas, unsigned int base,
2808                 unsigned int reg, unsigned int value)
2809 {
2810         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2811         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2812
2813         return regmap_write(palmas->regmap[slave_id], addr, value);
2814 }
2815
2816 static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base,
2817         unsigned int reg, const void *val, size_t val_count)
2818 {
2819         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2820         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2821
2822         return regmap_bulk_write(palmas->regmap[slave_id], addr,
2823                         val, val_count);
2824 }
2825
2826 static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base,
2827                 unsigned int reg, void *val, size_t val_count)
2828 {
2829         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2830         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2831
2832         return regmap_bulk_read(palmas->regmap[slave_id], addr,
2833                 val, val_count);
2834 }
2835
2836 static inline int palmas_update_bits(struct palmas *palmas, unsigned int base,
2837         unsigned int reg, unsigned int mask, unsigned int val)
2838 {
2839         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2840         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2841
2842         return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val);
2843 }
2844
2845 static inline int palmas_irq_get_virq(struct palmas *palmas, int irq)
2846 {
2847         return regmap_irq_get_virq(palmas->irq_data, irq);
2848 }
2849
2850 #endif /*  __LINUX_MFD_PALMAS_H */