4 * Copyright 2011 Texas Instruments Inc.
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
15 #ifndef __LINUX_MFD_PALMAS_H
16 #define __LINUX_MFD_PALMAS_H
18 #include <linux/usb/otg.h>
19 #include <linux/leds.h>
20 #include <linux/regmap.h>
21 #include <linux/regulator/driver.h>
23 #define PALMAS_NUM_CLIENTS 3
27 struct palmas_resource;
33 struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
34 struct regmap *regmap[PALMAS_NUM_CLIENTS];
42 struct mutex irq_lock;
43 struct regmap_irq_chip_data *irq_data;
46 struct palmas_pmic *pmic;
47 struct palmas_gpadc *gpadc;
48 struct palmas_resource *resource;
49 struct palmas_usb *usb;
57 struct palmas_gpadc_platform_data {
58 /* Channel 3 current source is only enabled during conversion */
61 /* Channel 0 current source can be used for battery detection.
62 * If used for battery detection this will cause a permanent current
63 * consumption depending on current level set here.
67 /* default BAT_REMOVAL_DAT setting on device probe */
70 /* Sets the START_POLARITY bit in the RT_CTRL register */
74 struct palmas_reg_init {
75 /* warm_rest controls the voltage levels after a warm reset
77 * 0: reload default values from OTP on warm reset
78 * 1: maintain voltage from VSEL on warm reset
82 /* roof_floor controls whether the regulator uses the i2c style
83 * of DVS or uses the method where a GPIO or other control method is
84 * attached to the NSLEEP/ENABLE1/ENABLE2 pins
88 * 0: i2c selection of voltage
89 * 1: pin selection of voltage.
95 /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
112 /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
113 * register. Set this is the default voltage set in OTP needs
120 enum palmas_regulators {
121 /* SMPS regulators */
144 /* External regulators */
150 /* Total number of regulators */
154 struct palmas_pmic_platform_data {
155 /* An array of pointers to regulator init data indexed by regulator
158 struct regulator_init_data *reg_data[PALMAS_NUM_REGS];
160 /* An array of pointers to structures containing sleep mode and DVS
161 * configuration for regulators indexed by ID
163 struct palmas_reg_init *reg_init[PALMAS_NUM_REGS];
165 /* use LDO6 for vibrator control */
168 /* Enable tracking mode of LDO8 */
169 bool enable_ldo8_tracking;
172 struct palmas_usb_platform_data {
173 /* Set this if platform wishes its own vbus control */
176 /* Do we enable the wakeup comparator on probe */
180 struct palmas_resource_platform_data {
181 int regen1_mode_sleep;
182 int regen2_mode_sleep;
183 int sysen1_mode_sleep;
184 int sysen2_mode_sleep;
186 /* bitfield to be loaded to NSLEEP_RES_ASSIGN */
188 /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */
190 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */
192 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */
195 /* bitfield to be loaded to ENABLE1_RES_ASSIGN */
197 /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */
199 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */
201 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */
204 /* bitfield to be loaded to ENABLE2_RES_ASSIGN */
206 /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */
208 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */
210 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */
214 struct palmas_clk_platform_data {
215 int clk32kg_mode_sleep;
216 int clk32kgaudio_mode_sleep;
219 struct palmas_platform_data {
222 /* bit value to be loaded to the POWER_CTRL register */
226 * boolean to select if we want to configure muxing here
227 * then the two value to load into the registers if true
232 struct palmas_pmic_platform_data *pmic_pdata;
233 struct palmas_gpadc_platform_data *gpadc_pdata;
234 struct palmas_usb_platform_data *usb_pdata;
235 struct palmas_resource_platform_data *resource_pdata;
236 struct palmas_clk_platform_data *clk_pdata;
239 struct palmas_gpadc_calibration {
245 struct palmas_gpadc {
247 struct palmas *palmas;
256 struct mutex reading_lock;
257 struct completion irq_complete;
261 struct palmas_gpadc_calibration *palmas_cal_tbl;
268 struct palmas_gpadc_result {
274 #define PALMAS_MAX_CHANNELS 16
276 /* Define the palmas IRQ numbers */
279 PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
281 PALMAS_LONG_PRESS_KEY_IRQ,
288 PALMAS_RTC_ALARM_IRQ,
289 PALMAS_RTC_TIMER_IRQ,
291 PALMAS_BATREMOVAL_IRQ,
297 PALMAS_GPADC_AUTO_0_IRQ,
298 PALMAS_GPADC_AUTO_1_IRQ,
299 PALMAS_GPADC_EOC_SW_IRQ,
300 PALMAS_GPADC_EOC_RT_IRQ,
314 /* Total Number IRQs */
319 struct palmas *palmas;
321 struct regulator_desc desc[PALMAS_NUM_REGS];
322 struct regulator_dev *rdev[PALMAS_NUM_REGS];
328 int range[PALMAS_REG_SMPS10];
329 unsigned int ramp_delay[PALMAS_REG_SMPS10];
330 unsigned int current_reg_mode[PALMAS_REG_SMPS10];
333 struct palmas_resource {
334 struct palmas *palmas;
339 struct palmas *palmas;
342 /* for vbus reporting with irqs disabled */
345 struct regulator *vbus_reg;
347 /* used to set vbus, in atomic path */
348 struct work_struct set_vbus_work;
360 #define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)
362 enum usb_irq_events {
363 /* Wakeup events from INT3 */
364 PALMAS_USB_ID_WAKEPUP,
365 PALMAS_USB_VBUS_WAKEUP,
377 N_PALMAS_USB_ID_FLOAT,
379 /* VBUS_OTG_EVENTS */
380 PALMAS_USB_VB_SESS_END,
381 N_PALMAS_USB_VB_SESS_END,
382 PALMAS_USB_VB_SESS_VLD,
383 N_PALMAS_USB_VB_SESS_VLD,
384 PALMAS_USB_VA_SESS_VLD,
385 N_PALMAS_USB_VA_SESS_VLD,
386 PALMAS_USB_VA_VBUS_VLD,
387 N_PALMAS_USB_VA_VBUS_VLD,
389 N_PALMAS_USB_VADP_SNS,
391 N_PALMAS_USB_VADP_PRB,
392 PALMAS_USB_VOTG_SESS_VLD,
393 N_PALMAS_USB_VOTG_SESS_VLD,
396 /* defines so we can store the mux settings */
397 #define PALMAS_GPIO_0_MUXED (1 << 0)
398 #define PALMAS_GPIO_1_MUXED (1 << 1)
399 #define PALMAS_GPIO_2_MUXED (1 << 2)
400 #define PALMAS_GPIO_3_MUXED (1 << 3)
401 #define PALMAS_GPIO_4_MUXED (1 << 4)
402 #define PALMAS_GPIO_5_MUXED (1 << 5)
403 #define PALMAS_GPIO_6_MUXED (1 << 6)
404 #define PALMAS_GPIO_7_MUXED (1 << 7)
406 #define PALMAS_LED1_MUXED (1 << 0)
407 #define PALMAS_LED2_MUXED (1 << 1)
409 #define PALMAS_PWM1_MUXED (1 << 0)
410 #define PALMAS_PWM2_MUXED (1 << 1)
412 /* helper macro to get correct slave number */
413 #define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1)
414 #define PALMAS_BASE_TO_REG(x, y) ((x & 0xff) + y)
416 /* Base addresses of IP blocks in Palmas */
417 #define PALMAS_SMPS_DVS_BASE 0x20
418 #define PALMAS_RTC_BASE 0x100
419 #define PALMAS_VALIDITY_BASE 0x118
420 #define PALMAS_SMPS_BASE 0x120
421 #define PALMAS_LDO_BASE 0x150
422 #define PALMAS_DVFS_BASE 0x180
423 #define PALMAS_PMU_CONTROL_BASE 0x1A0
424 #define PALMAS_RESOURCE_BASE 0x1D4
425 #define PALMAS_PU_PD_OD_BASE 0x1F4
426 #define PALMAS_LED_BASE 0x200
427 #define PALMAS_INTERRUPT_BASE 0x210
428 #define PALMAS_USB_OTG_BASE 0x250
429 #define PALMAS_VIBRATOR_BASE 0x270
430 #define PALMAS_GPIO_BASE 0x280
431 #define PALMAS_USB_BASE 0x290
432 #define PALMAS_GPADC_BASE 0x2C0
433 #define PALMAS_TRIM_GPADC_BASE 0x3CD
435 /* Registers for function RTC */
436 #define PALMAS_SECONDS_REG 0x0
437 #define PALMAS_MINUTES_REG 0x1
438 #define PALMAS_HOURS_REG 0x2
439 #define PALMAS_DAYS_REG 0x3
440 #define PALMAS_MONTHS_REG 0x4
441 #define PALMAS_YEARS_REG 0x5
442 #define PALMAS_WEEKS_REG 0x6
443 #define PALMAS_ALARM_SECONDS_REG 0x8
444 #define PALMAS_ALARM_MINUTES_REG 0x9
445 #define PALMAS_ALARM_HOURS_REG 0xA
446 #define PALMAS_ALARM_DAYS_REG 0xB
447 #define PALMAS_ALARM_MONTHS_REG 0xC
448 #define PALMAS_ALARM_YEARS_REG 0xD
449 #define PALMAS_RTC_CTRL_REG 0x10
450 #define PALMAS_RTC_STATUS_REG 0x11
451 #define PALMAS_RTC_INTERRUPTS_REG 0x12
452 #define PALMAS_RTC_COMP_LSB_REG 0x13
453 #define PALMAS_RTC_COMP_MSB_REG 0x14
454 #define PALMAS_RTC_RES_PROG_REG 0x15
455 #define PALMAS_RTC_RESET_STATUS_REG 0x16
457 /* Bit definitions for SECONDS_REG */
458 #define PALMAS_SECONDS_REG_SEC1_MASK 0x70
459 #define PALMAS_SECONDS_REG_SEC1_SHIFT 4
460 #define PALMAS_SECONDS_REG_SEC0_MASK 0x0f
461 #define PALMAS_SECONDS_REG_SEC0_SHIFT 0
463 /* Bit definitions for MINUTES_REG */
464 #define PALMAS_MINUTES_REG_MIN1_MASK 0x70
465 #define PALMAS_MINUTES_REG_MIN1_SHIFT 4
466 #define PALMAS_MINUTES_REG_MIN0_MASK 0x0f
467 #define PALMAS_MINUTES_REG_MIN0_SHIFT 0
469 /* Bit definitions for HOURS_REG */
470 #define PALMAS_HOURS_REG_PM_NAM 0x80
471 #define PALMAS_HOURS_REG_PM_NAM_SHIFT 7
472 #define PALMAS_HOURS_REG_HOUR1_MASK 0x30
473 #define PALMAS_HOURS_REG_HOUR1_SHIFT 4
474 #define PALMAS_HOURS_REG_HOUR0_MASK 0x0f
475 #define PALMAS_HOURS_REG_HOUR0_SHIFT 0
477 /* Bit definitions for DAYS_REG */
478 #define PALMAS_DAYS_REG_DAY1_MASK 0x30
479 #define PALMAS_DAYS_REG_DAY1_SHIFT 4
480 #define PALMAS_DAYS_REG_DAY0_MASK 0x0f
481 #define PALMAS_DAYS_REG_DAY0_SHIFT 0
483 /* Bit definitions for MONTHS_REG */
484 #define PALMAS_MONTHS_REG_MONTH1 0x10
485 #define PALMAS_MONTHS_REG_MONTH1_SHIFT 4
486 #define PALMAS_MONTHS_REG_MONTH0_MASK 0x0f
487 #define PALMAS_MONTHS_REG_MONTH0_SHIFT 0
489 /* Bit definitions for YEARS_REG */
490 #define PALMAS_YEARS_REG_YEAR1_MASK 0xf0
491 #define PALMAS_YEARS_REG_YEAR1_SHIFT 4
492 #define PALMAS_YEARS_REG_YEAR0_MASK 0x0f
493 #define PALMAS_YEARS_REG_YEAR0_SHIFT 0
495 /* Bit definitions for WEEKS_REG */
496 #define PALMAS_WEEKS_REG_WEEK_MASK 0x07
497 #define PALMAS_WEEKS_REG_WEEK_SHIFT 0
499 /* Bit definitions for ALARM_SECONDS_REG */
500 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70
501 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 4
502 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0f
503 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0
505 /* Bit definitions for ALARM_MINUTES_REG */
506 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70
507 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 4
508 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0f
509 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0
511 /* Bit definitions for ALARM_HOURS_REG */
512 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80
513 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 7
514 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30
515 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 4
516 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0f
517 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0
519 /* Bit definitions for ALARM_DAYS_REG */
520 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30
521 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 4
522 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0f
523 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0
525 /* Bit definitions for ALARM_MONTHS_REG */
526 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10
527 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 4
528 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0f
529 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0
531 /* Bit definitions for ALARM_YEARS_REG */
532 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0
533 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 4
534 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0f
535 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0
537 /* Bit definitions for RTC_CTRL_REG */
538 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80
539 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 7
540 #define PALMAS_RTC_CTRL_REG_GET_TIME 0x40
541 #define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 6
542 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20
543 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 5
544 #define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10
545 #define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 4
546 #define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08
547 #define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 3
548 #define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04
549 #define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 2
550 #define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02
551 #define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 1
552 #define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01
553 #define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0
555 /* Bit definitions for RTC_STATUS_REG */
556 #define PALMAS_RTC_STATUS_REG_POWER_UP 0x80
557 #define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 7
558 #define PALMAS_RTC_STATUS_REG_ALARM 0x40
559 #define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 6
560 #define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20
561 #define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 5
562 #define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10
563 #define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 4
564 #define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08
565 #define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 3
566 #define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04
567 #define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 2
568 #define PALMAS_RTC_STATUS_REG_RUN 0x02
569 #define PALMAS_RTC_STATUS_REG_RUN_SHIFT 1
571 /* Bit definitions for RTC_INTERRUPTS_REG */
572 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10
573 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 4
574 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08
575 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 3
576 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04
577 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 2
578 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03
579 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0
581 /* Bit definitions for RTC_COMP_LSB_REG */
582 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xff
583 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0
585 /* Bit definitions for RTC_COMP_MSB_REG */
586 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xff
587 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0
589 /* Bit definitions for RTC_RES_PROG_REG */
590 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3f
591 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0
593 /* Bit definitions for RTC_RESET_STATUS_REG */
594 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01
595 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0
597 /* Registers for function BACKUP */
598 #define PALMAS_BACKUP0 0x0
599 #define PALMAS_BACKUP1 0x1
600 #define PALMAS_BACKUP2 0x2
601 #define PALMAS_BACKUP3 0x3
602 #define PALMAS_BACKUP4 0x4
603 #define PALMAS_BACKUP5 0x5
604 #define PALMAS_BACKUP6 0x6
605 #define PALMAS_BACKUP7 0x7
607 /* Bit definitions for BACKUP0 */
608 #define PALMAS_BACKUP0_BACKUP_MASK 0xff
609 #define PALMAS_BACKUP0_BACKUP_SHIFT 0
611 /* Bit definitions for BACKUP1 */
612 #define PALMAS_BACKUP1_BACKUP_MASK 0xff
613 #define PALMAS_BACKUP1_BACKUP_SHIFT 0
615 /* Bit definitions for BACKUP2 */
616 #define PALMAS_BACKUP2_BACKUP_MASK 0xff
617 #define PALMAS_BACKUP2_BACKUP_SHIFT 0
619 /* Bit definitions for BACKUP3 */
620 #define PALMAS_BACKUP3_BACKUP_MASK 0xff
621 #define PALMAS_BACKUP3_BACKUP_SHIFT 0
623 /* Bit definitions for BACKUP4 */
624 #define PALMAS_BACKUP4_BACKUP_MASK 0xff
625 #define PALMAS_BACKUP4_BACKUP_SHIFT 0
627 /* Bit definitions for BACKUP5 */
628 #define PALMAS_BACKUP5_BACKUP_MASK 0xff
629 #define PALMAS_BACKUP5_BACKUP_SHIFT 0
631 /* Bit definitions for BACKUP6 */
632 #define PALMAS_BACKUP6_BACKUP_MASK 0xff
633 #define PALMAS_BACKUP6_BACKUP_SHIFT 0
635 /* Bit definitions for BACKUP7 */
636 #define PALMAS_BACKUP7_BACKUP_MASK 0xff
637 #define PALMAS_BACKUP7_BACKUP_SHIFT 0
639 /* Registers for function SMPS */
640 #define PALMAS_SMPS12_CTRL 0x0
641 #define PALMAS_SMPS12_TSTEP 0x1
642 #define PALMAS_SMPS12_FORCE 0x2
643 #define PALMAS_SMPS12_VOLTAGE 0x3
644 #define PALMAS_SMPS3_CTRL 0x4
645 #define PALMAS_SMPS3_VOLTAGE 0x7
646 #define PALMAS_SMPS45_CTRL 0x8
647 #define PALMAS_SMPS45_TSTEP 0x9
648 #define PALMAS_SMPS45_FORCE 0xA
649 #define PALMAS_SMPS45_VOLTAGE 0xB
650 #define PALMAS_SMPS6_CTRL 0xC
651 #define PALMAS_SMPS6_TSTEP 0xD
652 #define PALMAS_SMPS6_FORCE 0xE
653 #define PALMAS_SMPS6_VOLTAGE 0xF
654 #define PALMAS_SMPS7_CTRL 0x10
655 #define PALMAS_SMPS7_VOLTAGE 0x13
656 #define PALMAS_SMPS8_CTRL 0x14
657 #define PALMAS_SMPS8_TSTEP 0x15
658 #define PALMAS_SMPS8_FORCE 0x16
659 #define PALMAS_SMPS8_VOLTAGE 0x17
660 #define PALMAS_SMPS9_CTRL 0x18
661 #define PALMAS_SMPS9_VOLTAGE 0x1B
662 #define PALMAS_SMPS10_CTRL 0x1C
663 #define PALMAS_SMPS10_STATUS 0x1F
664 #define PALMAS_SMPS_CTRL 0x24
665 #define PALMAS_SMPS_PD_CTRL 0x25
666 #define PALMAS_SMPS_DITHER_EN 0x26
667 #define PALMAS_SMPS_THERMAL_EN 0x27
668 #define PALMAS_SMPS_THERMAL_STATUS 0x28
669 #define PALMAS_SMPS_SHORT_STATUS 0x29
670 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
671 #define PALMAS_SMPS_POWERGOOD_MASK1 0x2B
672 #define PALMAS_SMPS_POWERGOOD_MASK2 0x2C
674 /* Bit definitions for SMPS12_CTRL */
675 #define PALMAS_SMPS12_CTRL_WR_S 0x80
676 #define PALMAS_SMPS12_CTRL_WR_S_SHIFT 7
677 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40
678 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 6
679 #define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30
680 #define PALMAS_SMPS12_CTRL_STATUS_SHIFT 4
681 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c
682 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 2
683 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03
684 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0
686 /* Bit definitions for SMPS12_TSTEP */
687 #define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03
688 #define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0
690 /* Bit definitions for SMPS12_FORCE */
691 #define PALMAS_SMPS12_FORCE_CMD 0x80
692 #define PALMAS_SMPS12_FORCE_CMD_SHIFT 7
693 #define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7f
694 #define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0
696 /* Bit definitions for SMPS12_VOLTAGE */
697 #define PALMAS_SMPS12_VOLTAGE_RANGE 0x80
698 #define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 7
699 #define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7f
700 #define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0
702 /* Bit definitions for SMPS3_CTRL */
703 #define PALMAS_SMPS3_CTRL_WR_S 0x80
704 #define PALMAS_SMPS3_CTRL_WR_S_SHIFT 7
705 #define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30
706 #define PALMAS_SMPS3_CTRL_STATUS_SHIFT 4
707 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c
708 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 2
709 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
710 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0
712 /* Bit definitions for SMPS3_VOLTAGE */
713 #define PALMAS_SMPS3_VOLTAGE_RANGE 0x80
714 #define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 7
715 #define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7f
716 #define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0
718 /* Bit definitions for SMPS45_CTRL */
719 #define PALMAS_SMPS45_CTRL_WR_S 0x80
720 #define PALMAS_SMPS45_CTRL_WR_S_SHIFT 7
721 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40
722 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 6
723 #define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30
724 #define PALMAS_SMPS45_CTRL_STATUS_SHIFT 4
725 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c
726 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 2
727 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03
728 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0
730 /* Bit definitions for SMPS45_TSTEP */
731 #define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03
732 #define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0
734 /* Bit definitions for SMPS45_FORCE */
735 #define PALMAS_SMPS45_FORCE_CMD 0x80
736 #define PALMAS_SMPS45_FORCE_CMD_SHIFT 7
737 #define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7f
738 #define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0
740 /* Bit definitions for SMPS45_VOLTAGE */
741 #define PALMAS_SMPS45_VOLTAGE_RANGE 0x80
742 #define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 7
743 #define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7f
744 #define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0
746 /* Bit definitions for SMPS6_CTRL */
747 #define PALMAS_SMPS6_CTRL_WR_S 0x80
748 #define PALMAS_SMPS6_CTRL_WR_S_SHIFT 7
749 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40
750 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 6
751 #define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30
752 #define PALMAS_SMPS6_CTRL_STATUS_SHIFT 4
753 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c
754 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 2
755 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03
756 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0
758 /* Bit definitions for SMPS6_TSTEP */
759 #define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03
760 #define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0
762 /* Bit definitions for SMPS6_FORCE */
763 #define PALMAS_SMPS6_FORCE_CMD 0x80
764 #define PALMAS_SMPS6_FORCE_CMD_SHIFT 7
765 #define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7f
766 #define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0
768 /* Bit definitions for SMPS6_VOLTAGE */
769 #define PALMAS_SMPS6_VOLTAGE_RANGE 0x80
770 #define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 7
771 #define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7f
772 #define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0
774 /* Bit definitions for SMPS7_CTRL */
775 #define PALMAS_SMPS7_CTRL_WR_S 0x80
776 #define PALMAS_SMPS7_CTRL_WR_S_SHIFT 7
777 #define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30
778 #define PALMAS_SMPS7_CTRL_STATUS_SHIFT 4
779 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c
780 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 2
781 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03
782 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0
784 /* Bit definitions for SMPS7_VOLTAGE */
785 #define PALMAS_SMPS7_VOLTAGE_RANGE 0x80
786 #define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 7
787 #define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7f
788 #define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0
790 /* Bit definitions for SMPS8_CTRL */
791 #define PALMAS_SMPS8_CTRL_WR_S 0x80
792 #define PALMAS_SMPS8_CTRL_WR_S_SHIFT 7
793 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40
794 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 6
795 #define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30
796 #define PALMAS_SMPS8_CTRL_STATUS_SHIFT 4
797 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c
798 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 2
799 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03
800 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0
802 /* Bit definitions for SMPS8_TSTEP */
803 #define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03
804 #define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0
806 /* Bit definitions for SMPS8_FORCE */
807 #define PALMAS_SMPS8_FORCE_CMD 0x80
808 #define PALMAS_SMPS8_FORCE_CMD_SHIFT 7
809 #define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7f
810 #define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0
812 /* Bit definitions for SMPS8_VOLTAGE */
813 #define PALMAS_SMPS8_VOLTAGE_RANGE 0x80
814 #define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 7
815 #define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7f
816 #define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0
818 /* Bit definitions for SMPS9_CTRL */
819 #define PALMAS_SMPS9_CTRL_WR_S 0x80
820 #define PALMAS_SMPS9_CTRL_WR_S_SHIFT 7
821 #define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30
822 #define PALMAS_SMPS9_CTRL_STATUS_SHIFT 4
823 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c
824 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 2
825 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03
826 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0
828 /* Bit definitions for SMPS9_VOLTAGE */
829 #define PALMAS_SMPS9_VOLTAGE_RANGE 0x80
830 #define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 7
831 #define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7f
832 #define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0
834 /* Bit definitions for SMPS10_CTRL */
835 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0
836 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 4
837 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0f
838 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0
840 /* Bit definitions for SMPS10_STATUS */
841 #define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0f
842 #define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0
844 /* Bit definitions for SMPS_CTRL */
845 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20
846 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 5
847 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10
848 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 4
849 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c
850 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 2
851 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03
852 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0
854 /* Bit definitions for SMPS_PD_CTRL */
855 #define PALMAS_SMPS_PD_CTRL_SMPS9 0x40
856 #define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 6
857 #define PALMAS_SMPS_PD_CTRL_SMPS8 0x20
858 #define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 5
859 #define PALMAS_SMPS_PD_CTRL_SMPS7 0x10
860 #define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 4
861 #define PALMAS_SMPS_PD_CTRL_SMPS6 0x08
862 #define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 3
863 #define PALMAS_SMPS_PD_CTRL_SMPS45 0x04
864 #define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 2
865 #define PALMAS_SMPS_PD_CTRL_SMPS3 0x02
866 #define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 1
867 #define PALMAS_SMPS_PD_CTRL_SMPS12 0x01
868 #define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0
870 /* Bit definitions for SMPS_THERMAL_EN */
871 #define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40
872 #define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 6
873 #define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20
874 #define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 5
875 #define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08
876 #define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 3
877 #define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04
878 #define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 2
879 #define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01
880 #define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0
882 /* Bit definitions for SMPS_THERMAL_STATUS */
883 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40
884 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 6
885 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20
886 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 5
887 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08
888 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 3
889 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04
890 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 2
891 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01
892 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0
894 /* Bit definitions for SMPS_SHORT_STATUS */
895 #define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80
896 #define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 7
897 #define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40
898 #define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 6
899 #define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20
900 #define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 5
901 #define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10
902 #define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 4
903 #define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08
904 #define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 3
905 #define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04
906 #define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 2
907 #define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02
908 #define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 1
909 #define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01
910 #define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0
912 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
913 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40
914 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 6
915 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20
916 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 5
917 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10
918 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 4
919 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08
920 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 3
921 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04
922 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 2
923 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02
924 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 1
925 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01
926 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0
928 /* Bit definitions for SMPS_POWERGOOD_MASK1 */
929 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80
930 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 7
931 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40
932 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 6
933 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20
934 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 5
935 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10
936 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 4
937 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08
938 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 3
939 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04
940 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 2
941 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02
942 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 1
943 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01
944 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0
946 /* Bit definitions for SMPS_POWERGOOD_MASK2 */
947 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
948 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7
949 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04
950 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 2
951 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02
952 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 1
953 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01
954 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0
956 /* Registers for function LDO */
957 #define PALMAS_LDO1_CTRL 0x0
958 #define PALMAS_LDO1_VOLTAGE 0x1
959 #define PALMAS_LDO2_CTRL 0x2
960 #define PALMAS_LDO2_VOLTAGE 0x3
961 #define PALMAS_LDO3_CTRL 0x4
962 #define PALMAS_LDO3_VOLTAGE 0x5
963 #define PALMAS_LDO4_CTRL 0x6
964 #define PALMAS_LDO4_VOLTAGE 0x7
965 #define PALMAS_LDO5_CTRL 0x8
966 #define PALMAS_LDO5_VOLTAGE 0x9
967 #define PALMAS_LDO6_CTRL 0xA
968 #define PALMAS_LDO6_VOLTAGE 0xB
969 #define PALMAS_LDO7_CTRL 0xC
970 #define PALMAS_LDO7_VOLTAGE 0xD
971 #define PALMAS_LDO8_CTRL 0xE
972 #define PALMAS_LDO8_VOLTAGE 0xF
973 #define PALMAS_LDO9_CTRL 0x10
974 #define PALMAS_LDO9_VOLTAGE 0x11
975 #define PALMAS_LDOLN_CTRL 0x12
976 #define PALMAS_LDOLN_VOLTAGE 0x13
977 #define PALMAS_LDOUSB_CTRL 0x14
978 #define PALMAS_LDOUSB_VOLTAGE 0x15
979 #define PALMAS_LDO_CTRL 0x1A
980 #define PALMAS_LDO_PD_CTRL1 0x1B
981 #define PALMAS_LDO_PD_CTRL2 0x1C
982 #define PALMAS_LDO_SHORT_STATUS1 0x1D
983 #define PALMAS_LDO_SHORT_STATUS2 0x1E
985 /* Bit definitions for LDO1_CTRL */
986 #define PALMAS_LDO1_CTRL_WR_S 0x80
987 #define PALMAS_LDO1_CTRL_WR_S_SHIFT 7
988 #define PALMAS_LDO1_CTRL_STATUS 0x10
989 #define PALMAS_LDO1_CTRL_STATUS_SHIFT 4
990 #define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04
991 #define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 2
992 #define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01
993 #define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0
995 /* Bit definitions for LDO1_VOLTAGE */
996 #define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3f
997 #define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0
999 /* Bit definitions for LDO2_CTRL */
1000 #define PALMAS_LDO2_CTRL_WR_S 0x80
1001 #define PALMAS_LDO2_CTRL_WR_S_SHIFT 7
1002 #define PALMAS_LDO2_CTRL_STATUS 0x10
1003 #define PALMAS_LDO2_CTRL_STATUS_SHIFT 4
1004 #define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04
1005 #define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 2
1006 #define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01
1007 #define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0
1009 /* Bit definitions for LDO2_VOLTAGE */
1010 #define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3f
1011 #define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0
1013 /* Bit definitions for LDO3_CTRL */
1014 #define PALMAS_LDO3_CTRL_WR_S 0x80
1015 #define PALMAS_LDO3_CTRL_WR_S_SHIFT 7
1016 #define PALMAS_LDO3_CTRL_STATUS 0x10
1017 #define PALMAS_LDO3_CTRL_STATUS_SHIFT 4
1018 #define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04
1019 #define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 2
1020 #define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01
1021 #define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0
1023 /* Bit definitions for LDO3_VOLTAGE */
1024 #define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3f
1025 #define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0
1027 /* Bit definitions for LDO4_CTRL */
1028 #define PALMAS_LDO4_CTRL_WR_S 0x80
1029 #define PALMAS_LDO4_CTRL_WR_S_SHIFT 7
1030 #define PALMAS_LDO4_CTRL_STATUS 0x10
1031 #define PALMAS_LDO4_CTRL_STATUS_SHIFT 4
1032 #define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04
1033 #define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 2
1034 #define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01
1035 #define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0
1037 /* Bit definitions for LDO4_VOLTAGE */
1038 #define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3f
1039 #define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0
1041 /* Bit definitions for LDO5_CTRL */
1042 #define PALMAS_LDO5_CTRL_WR_S 0x80
1043 #define PALMAS_LDO5_CTRL_WR_S_SHIFT 7
1044 #define PALMAS_LDO5_CTRL_STATUS 0x10
1045 #define PALMAS_LDO5_CTRL_STATUS_SHIFT 4
1046 #define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04
1047 #define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 2
1048 #define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01
1049 #define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0
1051 /* Bit definitions for LDO5_VOLTAGE */
1052 #define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3f
1053 #define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0
1055 /* Bit definitions for LDO6_CTRL */
1056 #define PALMAS_LDO6_CTRL_WR_S 0x80
1057 #define PALMAS_LDO6_CTRL_WR_S_SHIFT 7
1058 #define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40
1059 #define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 6
1060 #define PALMAS_LDO6_CTRL_STATUS 0x10
1061 #define PALMAS_LDO6_CTRL_STATUS_SHIFT 4
1062 #define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04
1063 #define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 2
1064 #define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01
1065 #define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0
1067 /* Bit definitions for LDO6_VOLTAGE */
1068 #define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3f
1069 #define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0
1071 /* Bit definitions for LDO7_CTRL */
1072 #define PALMAS_LDO7_CTRL_WR_S 0x80
1073 #define PALMAS_LDO7_CTRL_WR_S_SHIFT 7
1074 #define PALMAS_LDO7_CTRL_STATUS 0x10
1075 #define PALMAS_LDO7_CTRL_STATUS_SHIFT 4
1076 #define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04
1077 #define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 2
1078 #define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01
1079 #define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0
1081 /* Bit definitions for LDO7_VOLTAGE */
1082 #define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3f
1083 #define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0
1085 /* Bit definitions for LDO8_CTRL */
1086 #define PALMAS_LDO8_CTRL_WR_S 0x80
1087 #define PALMAS_LDO8_CTRL_WR_S_SHIFT 7
1088 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40
1089 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 6
1090 #define PALMAS_LDO8_CTRL_STATUS 0x10
1091 #define PALMAS_LDO8_CTRL_STATUS_SHIFT 4
1092 #define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04
1093 #define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 2
1094 #define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01
1095 #define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0
1097 /* Bit definitions for LDO8_VOLTAGE */
1098 #define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3f
1099 #define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0
1101 /* Bit definitions for LDO9_CTRL */
1102 #define PALMAS_LDO9_CTRL_WR_S 0x80
1103 #define PALMAS_LDO9_CTRL_WR_S_SHIFT 7
1104 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40
1105 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 6
1106 #define PALMAS_LDO9_CTRL_STATUS 0x10
1107 #define PALMAS_LDO9_CTRL_STATUS_SHIFT 4
1108 #define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04
1109 #define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 2
1110 #define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01
1111 #define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0
1113 /* Bit definitions for LDO9_VOLTAGE */
1114 #define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3f
1115 #define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0
1117 /* Bit definitions for LDOLN_CTRL */
1118 #define PALMAS_LDOLN_CTRL_WR_S 0x80
1119 #define PALMAS_LDOLN_CTRL_WR_S_SHIFT 7
1120 #define PALMAS_LDOLN_CTRL_STATUS 0x10
1121 #define PALMAS_LDOLN_CTRL_STATUS_SHIFT 4
1122 #define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04
1123 #define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 2
1124 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01
1125 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0
1127 /* Bit definitions for LDOLN_VOLTAGE */
1128 #define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3f
1129 #define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0
1131 /* Bit definitions for LDOUSB_CTRL */
1132 #define PALMAS_LDOUSB_CTRL_WR_S 0x80
1133 #define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 7
1134 #define PALMAS_LDOUSB_CTRL_STATUS 0x10
1135 #define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 4
1136 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04
1137 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 2
1138 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01
1139 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0
1141 /* Bit definitions for LDOUSB_VOLTAGE */
1142 #define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3f
1143 #define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0
1145 /* Bit definitions for LDO_CTRL */
1146 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01
1147 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0
1149 /* Bit definitions for LDO_PD_CTRL1 */
1150 #define PALMAS_LDO_PD_CTRL1_LDO8 0x80
1151 #define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 7
1152 #define PALMAS_LDO_PD_CTRL1_LDO7 0x40
1153 #define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 6
1154 #define PALMAS_LDO_PD_CTRL1_LDO6 0x20
1155 #define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 5
1156 #define PALMAS_LDO_PD_CTRL1_LDO5 0x10
1157 #define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 4
1158 #define PALMAS_LDO_PD_CTRL1_LDO4 0x08
1159 #define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 3
1160 #define PALMAS_LDO_PD_CTRL1_LDO3 0x04
1161 #define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 2
1162 #define PALMAS_LDO_PD_CTRL1_LDO2 0x02
1163 #define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 1
1164 #define PALMAS_LDO_PD_CTRL1_LDO1 0x01
1165 #define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0
1167 /* Bit definitions for LDO_PD_CTRL2 */
1168 #define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04
1169 #define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 2
1170 #define PALMAS_LDO_PD_CTRL2_LDOLN 0x02
1171 #define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 1
1172 #define PALMAS_LDO_PD_CTRL2_LDO9 0x01
1173 #define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0
1175 /* Bit definitions for LDO_SHORT_STATUS1 */
1176 #define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80
1177 #define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 7
1178 #define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40
1179 #define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 6
1180 #define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20
1181 #define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 5
1182 #define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10
1183 #define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 4
1184 #define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08
1185 #define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 3
1186 #define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04
1187 #define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 2
1188 #define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02
1189 #define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 1
1190 #define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01
1191 #define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0
1193 /* Bit definitions for LDO_SHORT_STATUS2 */
1194 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08
1195 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 3
1196 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04
1197 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 2
1198 #define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02
1199 #define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 1
1200 #define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01
1201 #define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0
1203 /* Registers for function PMU_CONTROL */
1204 #define PALMAS_DEV_CTRL 0x0
1205 #define PALMAS_POWER_CTRL 0x1
1206 #define PALMAS_VSYS_LO 0x2
1207 #define PALMAS_VSYS_MON 0x3
1208 #define PALMAS_VBAT_MON 0x4
1209 #define PALMAS_WATCHDOG 0x5
1210 #define PALMAS_BOOT_STATUS 0x6
1211 #define PALMAS_BATTERY_BOUNCE 0x7
1212 #define PALMAS_BACKUP_BATTERY_CTRL 0x8
1213 #define PALMAS_LONG_PRESS_KEY 0x9
1214 #define PALMAS_OSC_THERM_CTRL 0xA
1215 #define PALMAS_BATDEBOUNCING 0xB
1216 #define PALMAS_SWOFF_HWRST 0xF
1217 #define PALMAS_SWOFF_COLDRST 0x10
1218 #define PALMAS_SWOFF_STATUS 0x11
1219 #define PALMAS_PMU_CONFIG 0x12
1220 #define PALMAS_SPARE 0x14
1221 #define PALMAS_PMU_SECONDARY_INT 0x15
1222 #define PALMAS_SW_REVISION 0x17
1223 #define PALMAS_EXT_CHRG_CTRL 0x18
1224 #define PALMAS_PMU_SECONDARY_INT2 0x19
1226 /* Bit definitions for DEV_CTRL */
1227 #define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c
1228 #define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 2
1229 #define PALMAS_DEV_CTRL_SW_RST 0x02
1230 #define PALMAS_DEV_CTRL_SW_RST_SHIFT 1
1231 #define PALMAS_DEV_CTRL_DEV_ON 0x01
1232 #define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0
1234 /* Bit definitions for POWER_CTRL */
1235 #define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04
1236 #define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 2
1237 #define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02
1238 #define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 1
1239 #define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01
1240 #define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0
1242 /* Bit definitions for VSYS_LO */
1243 #define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1f
1244 #define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0
1246 /* Bit definitions for VSYS_MON */
1247 #define PALMAS_VSYS_MON_ENABLE 0x80
1248 #define PALMAS_VSYS_MON_ENABLE_SHIFT 7
1249 #define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3f
1250 #define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0
1252 /* Bit definitions for VBAT_MON */
1253 #define PALMAS_VBAT_MON_ENABLE 0x80
1254 #define PALMAS_VBAT_MON_ENABLE_SHIFT 7
1255 #define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3f
1256 #define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0
1258 /* Bit definitions for WATCHDOG */
1259 #define PALMAS_WATCHDOG_LOCK 0x20
1260 #define PALMAS_WATCHDOG_LOCK_SHIFT 5
1261 #define PALMAS_WATCHDOG_ENABLE 0x10
1262 #define PALMAS_WATCHDOG_ENABLE_SHIFT 4
1263 #define PALMAS_WATCHDOG_MODE 0x08
1264 #define PALMAS_WATCHDOG_MODE_SHIFT 3
1265 #define PALMAS_WATCHDOG_TIMER_MASK 0x07
1266 #define PALMAS_WATCHDOG_TIMER_SHIFT 0
1268 /* Bit definitions for BOOT_STATUS */
1269 #define PALMAS_BOOT_STATUS_BOOT1 0x02
1270 #define PALMAS_BOOT_STATUS_BOOT1_SHIFT 1
1271 #define PALMAS_BOOT_STATUS_BOOT0 0x01
1272 #define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0
1274 /* Bit definitions for BATTERY_BOUNCE */
1275 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3f
1276 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0
1278 /* Bit definitions for BACKUP_BATTERY_CTRL */
1279 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80
1280 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 7
1281 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40
1282 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 6
1283 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20
1284 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 5
1285 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10
1286 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 4
1287 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08
1288 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 3
1289 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06
1290 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 1
1291 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01
1292 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0
1294 /* Bit definitions for LONG_PRESS_KEY */
1295 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80
1296 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 7
1297 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10
1298 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 4
1299 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c
1300 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 2
1301 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03
1302 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0
1304 /* Bit definitions for OSC_THERM_CTRL */
1305 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80
1306 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 7
1307 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40
1308 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 6
1309 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20
1310 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 5
1311 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10
1312 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 4
1313 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c
1314 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 2
1315 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02
1316 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 1
1317 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01
1318 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0
1320 /* Bit definitions for BATDEBOUNCING */
1321 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80
1322 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 7
1323 #define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78
1324 #define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 3
1325 #define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07
1326 #define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0
1328 /* Bit definitions for SWOFF_HWRST */
1329 #define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80
1330 #define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 7
1331 #define PALMAS_SWOFF_HWRST_PWRDOWN 0x40
1332 #define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 6
1333 #define PALMAS_SWOFF_HWRST_WTD 0x20
1334 #define PALMAS_SWOFF_HWRST_WTD_SHIFT 5
1335 #define PALMAS_SWOFF_HWRST_TSHUT 0x10
1336 #define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 4
1337 #define PALMAS_SWOFF_HWRST_RESET_IN 0x08
1338 #define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 3
1339 #define PALMAS_SWOFF_HWRST_SW_RST 0x04
1340 #define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 2
1341 #define PALMAS_SWOFF_HWRST_VSYS_LO 0x02
1342 #define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 1
1343 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01
1344 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0
1346 /* Bit definitions for SWOFF_COLDRST */
1347 #define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80
1348 #define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 7
1349 #define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40
1350 #define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 6
1351 #define PALMAS_SWOFF_COLDRST_WTD 0x20
1352 #define PALMAS_SWOFF_COLDRST_WTD_SHIFT 5
1353 #define PALMAS_SWOFF_COLDRST_TSHUT 0x10
1354 #define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 4
1355 #define PALMAS_SWOFF_COLDRST_RESET_IN 0x08
1356 #define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 3
1357 #define PALMAS_SWOFF_COLDRST_SW_RST 0x04
1358 #define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 2
1359 #define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02
1360 #define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 1
1361 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01
1362 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0
1364 /* Bit definitions for SWOFF_STATUS */
1365 #define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80
1366 #define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 7
1367 #define PALMAS_SWOFF_STATUS_PWRDOWN 0x40
1368 #define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 6
1369 #define PALMAS_SWOFF_STATUS_WTD 0x20
1370 #define PALMAS_SWOFF_STATUS_WTD_SHIFT 5
1371 #define PALMAS_SWOFF_STATUS_TSHUT 0x10
1372 #define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 4
1373 #define PALMAS_SWOFF_STATUS_RESET_IN 0x08
1374 #define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 3
1375 #define PALMAS_SWOFF_STATUS_SW_RST 0x04
1376 #define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 2
1377 #define PALMAS_SWOFF_STATUS_VSYS_LO 0x02
1378 #define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 1
1379 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01
1380 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0
1382 /* Bit definitions for PMU_CONFIG */
1383 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40
1384 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 6
1385 #define PALMAS_PMU_CONFIG_SPARE_MASK 0x30
1386 #define PALMAS_PMU_CONFIG_SPARE_SHIFT 4
1387 #define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c
1388 #define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 2
1389 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02
1390 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 1
1391 #define PALMAS_PMU_CONFIG_AUTODEVON 0x01
1392 #define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0
1394 /* Bit definitions for SPARE */
1395 #define PALMAS_SPARE_SPARE_MASK 0xf8
1396 #define PALMAS_SPARE_SPARE_SHIFT 3
1397 #define PALMAS_SPARE_REGEN3_OD 0x04
1398 #define PALMAS_SPARE_REGEN3_OD_SHIFT 2
1399 #define PALMAS_SPARE_REGEN2_OD 0x02
1400 #define PALMAS_SPARE_REGEN2_OD_SHIFT 1
1401 #define PALMAS_SPARE_REGEN1_OD 0x01
1402 #define PALMAS_SPARE_REGEN1_OD_SHIFT 0
1404 /* Bit definitions for PMU_SECONDARY_INT */
1405 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80
1406 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 7
1407 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40
1408 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 6
1409 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20
1410 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 5
1411 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10
1412 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 4
1413 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08
1414 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 3
1415 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04
1416 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 2
1417 #define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02
1418 #define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 1
1419 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01
1420 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0
1422 /* Bit definitions for SW_REVISION */
1423 #define PALMAS_SW_REVISION_SW_REVISION_MASK 0xff
1424 #define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0
1426 /* Bit definitions for EXT_CHRG_CTRL */
1427 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80
1428 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 7
1429 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40
1430 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 6
1431 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08
1432 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 3
1433 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04
1434 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 2
1435 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02
1436 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 1
1437 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01
1438 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0
1440 /* Bit definitions for PMU_SECONDARY_INT2 */
1441 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20
1442 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 5
1443 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10
1444 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 4
1445 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02
1446 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 1
1447 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01
1448 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0
1450 /* Registers for function RESOURCE */
1451 #define PALMAS_CLK32KG_CTRL 0x0
1452 #define PALMAS_CLK32KGAUDIO_CTRL 0x1
1453 #define PALMAS_REGEN1_CTRL 0x2
1454 #define PALMAS_REGEN2_CTRL 0x3
1455 #define PALMAS_SYSEN1_CTRL 0x4
1456 #define PALMAS_SYSEN2_CTRL 0x5
1457 #define PALMAS_NSLEEP_RES_ASSIGN 0x6
1458 #define PALMAS_NSLEEP_SMPS_ASSIGN 0x7
1459 #define PALMAS_NSLEEP_LDO_ASSIGN1 0x8
1460 #define PALMAS_NSLEEP_LDO_ASSIGN2 0x9
1461 #define PALMAS_ENABLE1_RES_ASSIGN 0xA
1462 #define PALMAS_ENABLE1_SMPS_ASSIGN 0xB
1463 #define PALMAS_ENABLE1_LDO_ASSIGN1 0xC
1464 #define PALMAS_ENABLE1_LDO_ASSIGN2 0xD
1465 #define PALMAS_ENABLE2_RES_ASSIGN 0xE
1466 #define PALMAS_ENABLE2_SMPS_ASSIGN 0xF
1467 #define PALMAS_ENABLE2_LDO_ASSIGN1 0x10
1468 #define PALMAS_ENABLE2_LDO_ASSIGN2 0x11
1469 #define PALMAS_REGEN3_CTRL 0x12
1471 /* Bit definitions for CLK32KG_CTRL */
1472 #define PALMAS_CLK32KG_CTRL_STATUS 0x10
1473 #define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 4
1474 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04
1475 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 2
1476 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01
1477 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0
1479 /* Bit definitions for CLK32KGAUDIO_CTRL */
1480 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10
1481 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 4
1482 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08
1483 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 3
1484 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04
1485 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 2
1486 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01
1487 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0
1489 /* Bit definitions for REGEN1_CTRL */
1490 #define PALMAS_REGEN1_CTRL_STATUS 0x10
1491 #define PALMAS_REGEN1_CTRL_STATUS_SHIFT 4
1492 #define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04
1493 #define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 2
1494 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01
1495 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0
1497 /* Bit definitions for REGEN2_CTRL */
1498 #define PALMAS_REGEN2_CTRL_STATUS 0x10
1499 #define PALMAS_REGEN2_CTRL_STATUS_SHIFT 4
1500 #define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04
1501 #define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 2
1502 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01
1503 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0
1505 /* Bit definitions for SYSEN1_CTRL */
1506 #define PALMAS_SYSEN1_CTRL_STATUS 0x10
1507 #define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 4
1508 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04
1509 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 2
1510 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01
1511 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0
1513 /* Bit definitions for SYSEN2_CTRL */
1514 #define PALMAS_SYSEN2_CTRL_STATUS 0x10
1515 #define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 4
1516 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04
1517 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 2
1518 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01
1519 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0
1521 /* Bit definitions for NSLEEP_RES_ASSIGN */
1522 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40
1523 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 6
1524 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20
1525 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5
1526 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10
1527 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 4
1528 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08
1529 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 3
1530 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04
1531 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 2
1532 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02
1533 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 1
1534 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01
1535 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0
1537 /* Bit definitions for NSLEEP_SMPS_ASSIGN */
1538 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80
1539 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 7
1540 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40
1541 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 6
1542 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20
1543 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 5
1544 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10
1545 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 4
1546 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08
1547 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 3
1548 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04
1549 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 2
1550 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02
1551 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 1
1552 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01
1553 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0
1555 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */
1556 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80
1557 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 7
1558 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40
1559 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 6
1560 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20
1561 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 5
1562 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10
1563 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 4
1564 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08
1565 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 3
1566 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04
1567 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 2
1568 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02
1569 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 1
1570 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01
1571 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0
1573 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */
1574 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04
1575 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 2
1576 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02
1577 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 1
1578 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01
1579 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0
1581 /* Bit definitions for ENABLE1_RES_ASSIGN */
1582 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40
1583 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 6
1584 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20
1585 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5
1586 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10
1587 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 4
1588 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08
1589 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 3
1590 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04
1591 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 2
1592 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02
1593 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 1
1594 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01
1595 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0
1597 /* Bit definitions for ENABLE1_SMPS_ASSIGN */
1598 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80
1599 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 7
1600 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40
1601 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 6
1602 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20
1603 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 5
1604 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10
1605 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 4
1606 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08
1607 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 3
1608 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04
1609 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 2
1610 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02
1611 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 1
1612 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01
1613 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0
1615 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */
1616 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80
1617 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 7
1618 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40
1619 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 6
1620 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20
1621 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 5
1622 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10
1623 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 4
1624 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08
1625 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 3
1626 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04
1627 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 2
1628 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02
1629 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 1
1630 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01
1631 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0
1633 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */
1634 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04
1635 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 2
1636 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02
1637 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 1
1638 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01
1639 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0
1641 /* Bit definitions for ENABLE2_RES_ASSIGN */
1642 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40
1643 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 6
1644 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20
1645 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5
1646 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10
1647 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 4
1648 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08
1649 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 3
1650 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04
1651 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 2
1652 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02
1653 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 1
1654 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01
1655 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0
1657 /* Bit definitions for ENABLE2_SMPS_ASSIGN */
1658 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80
1659 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 7
1660 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40
1661 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 6
1662 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20
1663 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 5
1664 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10
1665 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 4
1666 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08
1667 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 3
1668 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04
1669 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 2
1670 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02
1671 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 1
1672 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01
1673 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0
1675 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */
1676 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80
1677 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 7
1678 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40
1679 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 6
1680 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20
1681 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 5
1682 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10
1683 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 4
1684 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08
1685 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 3
1686 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04
1687 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 2
1688 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02
1689 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 1
1690 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01
1691 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0
1693 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */
1694 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04
1695 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 2
1696 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02
1697 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 1
1698 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01
1699 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0
1701 /* Bit definitions for REGEN3_CTRL */
1702 #define PALMAS_REGEN3_CTRL_STATUS 0x10
1703 #define PALMAS_REGEN3_CTRL_STATUS_SHIFT 4
1704 #define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04
1705 #define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 2
1706 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01
1707 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0
1709 /* Registers for function PAD_CONTROL */
1710 #define PALMAS_PU_PD_INPUT_CTRL1 0x0
1711 #define PALMAS_PU_PD_INPUT_CTRL2 0x1
1712 #define PALMAS_PU_PD_INPUT_CTRL3 0x2
1713 #define PALMAS_OD_OUTPUT_CTRL 0x4
1714 #define PALMAS_POLARITY_CTRL 0x5
1715 #define PALMAS_PRIMARY_SECONDARY_PAD1 0x6
1716 #define PALMAS_PRIMARY_SECONDARY_PAD2 0x7
1717 #define PALMAS_I2C_SPI 0x8
1718 #define PALMAS_PU_PD_INPUT_CTRL4 0x9
1719 #define PALMAS_PRIMARY_SECONDARY_PAD3 0xA
1721 /* Bit definitions for PU_PD_INPUT_CTRL1 */
1722 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40
1723 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 6
1724 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20
1725 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 5
1726 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10
1727 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 4
1728 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04
1729 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 2
1730 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02
1731 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 1
1733 /* Bit definitions for PU_PD_INPUT_CTRL2 */
1734 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20
1735 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 5
1736 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10
1737 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 4
1738 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08
1739 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 3
1740 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04
1741 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 2
1742 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02
1743 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 1
1744 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01
1745 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0
1747 /* Bit definitions for PU_PD_INPUT_CTRL3 */
1748 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40
1749 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 6
1750 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10
1751 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 4
1752 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04
1753 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 2
1754 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01
1755 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0
1757 /* Bit definitions for OD_OUTPUT_CTRL */
1758 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80
1759 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 7
1760 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40
1761 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 6
1762 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20
1763 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 5
1764 #define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08
1765 #define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 3
1767 /* Bit definitions for POLARITY_CTRL */
1768 #define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80
1769 #define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 7
1770 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40
1771 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 6
1772 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20
1773 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 5
1774 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10
1775 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 4
1776 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08
1777 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 3
1778 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04
1779 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 2
1780 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02
1781 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 1
1782 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01
1783 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0
1785 /* Bit definitions for PRIMARY_SECONDARY_PAD1 */
1786 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80
1787 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 7
1788 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60
1789 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 5
1790 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18
1791 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 3
1792 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04
1793 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 2
1794 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02
1795 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 1
1796 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01
1797 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0
1799 /* Bit definitions for PRIMARY_SECONDARY_PAD2 */
1800 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30
1801 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 4
1802 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08
1803 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 3
1804 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06
1805 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 1
1806 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01
1807 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0
1809 /* Bit definitions for I2C_SPI */
1810 #define PALMAS_I2C_SPI_I2C2OTP_EN 0x80
1811 #define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 7
1812 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40
1813 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 6
1814 #define PALMAS_I2C_SPI_ID_I2C2 0x20
1815 #define PALMAS_I2C_SPI_ID_I2C2_SHIFT 5
1816 #define PALMAS_I2C_SPI_I2C_SPI 0x10
1817 #define PALMAS_I2C_SPI_I2C_SPI_SHIFT 4
1818 #define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0f
1819 #define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0
1821 /* Bit definitions for PU_PD_INPUT_CTRL4 */
1822 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40
1823 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 6
1824 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10
1825 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 4
1826 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04
1827 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 2
1828 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01
1829 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0
1831 /* Bit definitions for PRIMARY_SECONDARY_PAD3 */
1832 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02
1833 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 1
1834 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01
1835 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0
1837 /* Registers for function LED_PWM */
1838 #define PALMAS_LED_PERIOD_CTRL 0x0
1839 #define PALMAS_LED_CTRL 0x1
1840 #define PALMAS_PWM_CTRL1 0x2
1841 #define PALMAS_PWM_CTRL2 0x3
1843 /* Bit definitions for LED_PERIOD_CTRL */
1844 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38
1845 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 3
1846 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07
1847 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0
1849 /* Bit definitions for LED_CTRL */
1850 #define PALMAS_LED_CTRL_LED_2_SEQ 0x20
1851 #define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 5
1852 #define PALMAS_LED_CTRL_LED_1_SEQ 0x10
1853 #define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 4
1854 #define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c
1855 #define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 2
1856 #define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03
1857 #define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0
1859 /* Bit definitions for PWM_CTRL1 */
1860 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02
1861 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 1
1862 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01
1863 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0
1865 /* Bit definitions for PWM_CTRL2 */
1866 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xff
1867 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0
1869 /* Registers for function INTERRUPT */
1870 #define PALMAS_INT1_STATUS 0x0
1871 #define PALMAS_INT1_MASK 0x1
1872 #define PALMAS_INT1_LINE_STATE 0x2
1873 #define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x3
1874 #define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x4
1875 #define PALMAS_INT2_STATUS 0x5
1876 #define PALMAS_INT2_MASK 0x6
1877 #define PALMAS_INT2_LINE_STATE 0x7
1878 #define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x8
1879 #define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x9
1880 #define PALMAS_INT3_STATUS 0xA
1881 #define PALMAS_INT3_MASK 0xB
1882 #define PALMAS_INT3_LINE_STATE 0xC
1883 #define PALMAS_INT3_EDGE_DETECT1_RESERVED 0xD
1884 #define PALMAS_INT3_EDGE_DETECT2_RESERVED 0xE
1885 #define PALMAS_INT4_STATUS 0xF
1886 #define PALMAS_INT4_MASK 0x10
1887 #define PALMAS_INT4_LINE_STATE 0x11
1888 #define PALMAS_INT4_EDGE_DETECT1 0x12
1889 #define PALMAS_INT4_EDGE_DETECT2 0x13
1890 #define PALMAS_INT_CTRL 0x14
1892 /* Bit definitions for INT1_STATUS */
1893 #define PALMAS_INT1_STATUS_VBAT_MON 0x80
1894 #define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 7
1895 #define PALMAS_INT1_STATUS_VSYS_MON 0x40
1896 #define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 6
1897 #define PALMAS_INT1_STATUS_HOTDIE 0x20
1898 #define PALMAS_INT1_STATUS_HOTDIE_SHIFT 5
1899 #define PALMAS_INT1_STATUS_PWRDOWN 0x10
1900 #define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 4
1901 #define PALMAS_INT1_STATUS_RPWRON 0x08
1902 #define PALMAS_INT1_STATUS_RPWRON_SHIFT 3
1903 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04
1904 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 2
1905 #define PALMAS_INT1_STATUS_PWRON 0x02
1906 #define PALMAS_INT1_STATUS_PWRON_SHIFT 1
1907 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01
1908 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0
1910 /* Bit definitions for INT1_MASK */
1911 #define PALMAS_INT1_MASK_VBAT_MON 0x80
1912 #define PALMAS_INT1_MASK_VBAT_MON_SHIFT 7
1913 #define PALMAS_INT1_MASK_VSYS_MON 0x40
1914 #define PALMAS_INT1_MASK_VSYS_MON_SHIFT 6
1915 #define PALMAS_INT1_MASK_HOTDIE 0x20
1916 #define PALMAS_INT1_MASK_HOTDIE_SHIFT 5
1917 #define PALMAS_INT1_MASK_PWRDOWN 0x10
1918 #define PALMAS_INT1_MASK_PWRDOWN_SHIFT 4
1919 #define PALMAS_INT1_MASK_RPWRON 0x08
1920 #define PALMAS_INT1_MASK_RPWRON_SHIFT 3
1921 #define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04
1922 #define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 2
1923 #define PALMAS_INT1_MASK_PWRON 0x02
1924 #define PALMAS_INT1_MASK_PWRON_SHIFT 1
1925 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01
1926 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0
1928 /* Bit definitions for INT1_LINE_STATE */
1929 #define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80
1930 #define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 7
1931 #define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40
1932 #define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 6
1933 #define PALMAS_INT1_LINE_STATE_HOTDIE 0x20
1934 #define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 5
1935 #define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10
1936 #define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 4
1937 #define PALMAS_INT1_LINE_STATE_RPWRON 0x08
1938 #define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 3
1939 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
1940 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 2
1941 #define PALMAS_INT1_LINE_STATE_PWRON 0x02
1942 #define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 1
1943 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01
1944 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0
1946 /* Bit definitions for INT2_STATUS */
1947 #define PALMAS_INT2_STATUS_VAC_ACOK 0x80
1948 #define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 7
1949 #define PALMAS_INT2_STATUS_SHORT 0x40
1950 #define PALMAS_INT2_STATUS_SHORT_SHIFT 6
1951 #define PALMAS_INT2_STATUS_FBI_BB 0x20
1952 #define PALMAS_INT2_STATUS_FBI_BB_SHIFT 5
1953 #define PALMAS_INT2_STATUS_RESET_IN 0x10
1954 #define PALMAS_INT2_STATUS_RESET_IN_SHIFT 4
1955 #define PALMAS_INT2_STATUS_BATREMOVAL 0x08
1956 #define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 3
1957 #define PALMAS_INT2_STATUS_WDT 0x04
1958 #define PALMAS_INT2_STATUS_WDT_SHIFT 2
1959 #define PALMAS_INT2_STATUS_RTC_TIMER 0x02
1960 #define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 1
1961 #define PALMAS_INT2_STATUS_RTC_ALARM 0x01
1962 #define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0
1964 /* Bit definitions for INT2_MASK */
1965 #define PALMAS_INT2_MASK_VAC_ACOK 0x80
1966 #define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 7
1967 #define PALMAS_INT2_MASK_SHORT 0x40
1968 #define PALMAS_INT2_MASK_SHORT_SHIFT 6
1969 #define PALMAS_INT2_MASK_FBI_BB 0x20
1970 #define PALMAS_INT2_MASK_FBI_BB_SHIFT 5
1971 #define PALMAS_INT2_MASK_RESET_IN 0x10
1972 #define PALMAS_INT2_MASK_RESET_IN_SHIFT 4
1973 #define PALMAS_INT2_MASK_BATREMOVAL 0x08
1974 #define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 3
1975 #define PALMAS_INT2_MASK_WDT 0x04
1976 #define PALMAS_INT2_MASK_WDT_SHIFT 2
1977 #define PALMAS_INT2_MASK_RTC_TIMER 0x02
1978 #define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 1
1979 #define PALMAS_INT2_MASK_RTC_ALARM 0x01
1980 #define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0
1982 /* Bit definitions for INT2_LINE_STATE */
1983 #define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80
1984 #define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 7
1985 #define PALMAS_INT2_LINE_STATE_SHORT 0x40
1986 #define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 6
1987 #define PALMAS_INT2_LINE_STATE_FBI_BB 0x20
1988 #define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 5
1989 #define PALMAS_INT2_LINE_STATE_RESET_IN 0x10
1990 #define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 4
1991 #define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08
1992 #define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 3
1993 #define PALMAS_INT2_LINE_STATE_WDT 0x04
1994 #define PALMAS_INT2_LINE_STATE_WDT_SHIFT 2
1995 #define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02
1996 #define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 1
1997 #define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01
1998 #define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0
2000 /* Bit definitions for INT3_STATUS */
2001 #define PALMAS_INT3_STATUS_VBUS 0x80
2002 #define PALMAS_INT3_STATUS_VBUS_SHIFT 7
2003 #define PALMAS_INT3_STATUS_VBUS_OTG 0x40
2004 #define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 6
2005 #define PALMAS_INT3_STATUS_ID 0x20
2006 #define PALMAS_INT3_STATUS_ID_SHIFT 5
2007 #define PALMAS_INT3_STATUS_ID_OTG 0x10
2008 #define PALMAS_INT3_STATUS_ID_OTG_SHIFT 4
2009 #define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08
2010 #define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 3
2011 #define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04
2012 #define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 2
2013 #define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02
2014 #define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 1
2015 #define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01
2016 #define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0
2018 /* Bit definitions for INT3_MASK */
2019 #define PALMAS_INT3_MASK_VBUS 0x80
2020 #define PALMAS_INT3_MASK_VBUS_SHIFT 7
2021 #define PALMAS_INT3_MASK_VBUS_OTG 0x40
2022 #define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 6
2023 #define PALMAS_INT3_MASK_ID 0x20
2024 #define PALMAS_INT3_MASK_ID_SHIFT 5
2025 #define PALMAS_INT3_MASK_ID_OTG 0x10
2026 #define PALMAS_INT3_MASK_ID_OTG_SHIFT 4
2027 #define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08
2028 #define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 3
2029 #define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04
2030 #define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 2
2031 #define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02
2032 #define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 1
2033 #define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01
2034 #define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0
2036 /* Bit definitions for INT3_LINE_STATE */
2037 #define PALMAS_INT3_LINE_STATE_VBUS 0x80
2038 #define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 7
2039 #define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40
2040 #define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 6
2041 #define PALMAS_INT3_LINE_STATE_ID 0x20
2042 #define PALMAS_INT3_LINE_STATE_ID_SHIFT 5
2043 #define PALMAS_INT3_LINE_STATE_ID_OTG 0x10
2044 #define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 4
2045 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08
2046 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 3
2047 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04
2048 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 2
2049 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02
2050 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 1
2051 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01
2052 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0
2054 /* Bit definitions for INT4_STATUS */
2055 #define PALMAS_INT4_STATUS_GPIO_7 0x80
2056 #define PALMAS_INT4_STATUS_GPIO_7_SHIFT 7
2057 #define PALMAS_INT4_STATUS_GPIO_6 0x40
2058 #define PALMAS_INT4_STATUS_GPIO_6_SHIFT 6
2059 #define PALMAS_INT4_STATUS_GPIO_5 0x20
2060 #define PALMAS_INT4_STATUS_GPIO_5_SHIFT 5
2061 #define PALMAS_INT4_STATUS_GPIO_4 0x10
2062 #define PALMAS_INT4_STATUS_GPIO_4_SHIFT 4
2063 #define PALMAS_INT4_STATUS_GPIO_3 0x08
2064 #define PALMAS_INT4_STATUS_GPIO_3_SHIFT 3
2065 #define PALMAS_INT4_STATUS_GPIO_2 0x04
2066 #define PALMAS_INT4_STATUS_GPIO_2_SHIFT 2
2067 #define PALMAS_INT4_STATUS_GPIO_1 0x02
2068 #define PALMAS_INT4_STATUS_GPIO_1_SHIFT 1
2069 #define PALMAS_INT4_STATUS_GPIO_0 0x01
2070 #define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0
2072 /* Bit definitions for INT4_MASK */
2073 #define PALMAS_INT4_MASK_GPIO_7 0x80
2074 #define PALMAS_INT4_MASK_GPIO_7_SHIFT 7
2075 #define PALMAS_INT4_MASK_GPIO_6 0x40
2076 #define PALMAS_INT4_MASK_GPIO_6_SHIFT 6
2077 #define PALMAS_INT4_MASK_GPIO_5 0x20
2078 #define PALMAS_INT4_MASK_GPIO_5_SHIFT 5
2079 #define PALMAS_INT4_MASK_GPIO_4 0x10
2080 #define PALMAS_INT4_MASK_GPIO_4_SHIFT 4
2081 #define PALMAS_INT4_MASK_GPIO_3 0x08
2082 #define PALMAS_INT4_MASK_GPIO_3_SHIFT 3
2083 #define PALMAS_INT4_MASK_GPIO_2 0x04
2084 #define PALMAS_INT4_MASK_GPIO_2_SHIFT 2
2085 #define PALMAS_INT4_MASK_GPIO_1 0x02
2086 #define PALMAS_INT4_MASK_GPIO_1_SHIFT 1
2087 #define PALMAS_INT4_MASK_GPIO_0 0x01
2088 #define PALMAS_INT4_MASK_GPIO_0_SHIFT 0
2090 /* Bit definitions for INT4_LINE_STATE */
2091 #define PALMAS_INT4_LINE_STATE_GPIO_7 0x80
2092 #define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 7
2093 #define PALMAS_INT4_LINE_STATE_GPIO_6 0x40
2094 #define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 6
2095 #define PALMAS_INT4_LINE_STATE_GPIO_5 0x20
2096 #define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 5
2097 #define PALMAS_INT4_LINE_STATE_GPIO_4 0x10
2098 #define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 4
2099 #define PALMAS_INT4_LINE_STATE_GPIO_3 0x08
2100 #define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 3
2101 #define PALMAS_INT4_LINE_STATE_GPIO_2 0x04
2102 #define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 2
2103 #define PALMAS_INT4_LINE_STATE_GPIO_1 0x02
2104 #define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 1
2105 #define PALMAS_INT4_LINE_STATE_GPIO_0 0x01
2106 #define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0
2108 /* Bit definitions for INT4_EDGE_DETECT1 */
2109 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
2110 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 7
2111 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
2112 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 6
2113 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
2114 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 5
2115 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
2116 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 4
2117 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
2118 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 3
2119 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
2120 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 2
2121 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
2122 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 1
2123 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
2124 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0
2126 /* Bit definitions for INT4_EDGE_DETECT2 */
2127 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80
2128 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 7
2129 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40
2130 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 6
2131 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
2132 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 5
2133 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
2134 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 4
2135 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
2136 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 3
2137 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
2138 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 2
2139 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
2140 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 1
2141 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
2142 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0
2144 /* Bit definitions for INT_CTRL */
2145 #define PALMAS_INT_CTRL_INT_PENDING 0x04
2146 #define PALMAS_INT_CTRL_INT_PENDING_SHIFT 2
2147 #define PALMAS_INT_CTRL_INT_CLEAR 0x01
2148 #define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0
2150 /* Registers for function USB_OTG */
2151 #define PALMAS_USB_WAKEUP 0x3
2152 #define PALMAS_USB_VBUS_CTRL_SET 0x4
2153 #define PALMAS_USB_VBUS_CTRL_CLR 0x5
2154 #define PALMAS_USB_ID_CTRL_SET 0x6
2155 #define PALMAS_USB_ID_CTRL_CLEAR 0x7
2156 #define PALMAS_USB_VBUS_INT_SRC 0x8
2157 #define PALMAS_USB_VBUS_INT_LATCH_SET 0x9
2158 #define PALMAS_USB_VBUS_INT_LATCH_CLR 0xA
2159 #define PALMAS_USB_VBUS_INT_EN_LO_SET 0xB
2160 #define PALMAS_USB_VBUS_INT_EN_LO_CLR 0xC
2161 #define PALMAS_USB_VBUS_INT_EN_HI_SET 0xD
2162 #define PALMAS_USB_VBUS_INT_EN_HI_CLR 0xE
2163 #define PALMAS_USB_ID_INT_SRC 0xF
2164 #define PALMAS_USB_ID_INT_LATCH_SET 0x10
2165 #define PALMAS_USB_ID_INT_LATCH_CLR 0x11
2166 #define PALMAS_USB_ID_INT_EN_LO_SET 0x12
2167 #define PALMAS_USB_ID_INT_EN_LO_CLR 0x13
2168 #define PALMAS_USB_ID_INT_EN_HI_SET 0x14
2169 #define PALMAS_USB_ID_INT_EN_HI_CLR 0x15
2170 #define PALMAS_USB_OTG_ADP_CTRL 0x16
2171 #define PALMAS_USB_OTG_ADP_HIGH 0x17
2172 #define PALMAS_USB_OTG_ADP_LOW 0x18
2173 #define PALMAS_USB_OTG_ADP_RISE 0x19
2174 #define PALMAS_USB_OTG_REVISION 0x1A
2176 /* Bit definitions for USB_WAKEUP */
2177 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01
2178 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0
2180 /* Bit definitions for USB_VBUS_CTRL_SET */
2181 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80
2182 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 7
2183 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20
2184 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 5
2185 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10
2186 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 4
2187 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08
2188 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 3
2189 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04
2190 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 2
2192 /* Bit definitions for USB_VBUS_CTRL_CLR */
2193 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80
2194 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 7
2195 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20
2196 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 5
2197 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10
2198 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 4
2199 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08
2200 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 3
2201 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04
2202 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 2
2204 /* Bit definitions for USB_ID_CTRL_SET */
2205 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80
2206 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 7
2207 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40
2208 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 6
2209 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20
2210 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 5
2211 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10
2212 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 4
2213 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08
2214 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 3
2215 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04
2216 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 2
2218 /* Bit definitions for USB_ID_CTRL_CLEAR */
2219 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80
2220 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 7
2221 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40
2222 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 6
2223 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20
2224 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 5
2225 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10
2226 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 4
2227 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08
2228 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 3
2229 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04
2230 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 2
2232 /* Bit definitions for USB_VBUS_INT_SRC */
2233 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80
2234 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 7
2235 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40
2236 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 6
2237 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20
2238 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 5
2239 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08
2240 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 3
2241 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04
2242 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 2
2243 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02
2244 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 1
2245 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01
2246 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0
2248 /* Bit definitions for USB_VBUS_INT_LATCH_SET */
2249 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80
2250 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 7
2251 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40
2252 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 6
2253 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20
2254 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 5
2255 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10
2256 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 4
2257 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08
2258 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 3
2259 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04
2260 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 2
2261 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02
2262 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 1
2263 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01
2264 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0
2266 /* Bit definitions for USB_VBUS_INT_LATCH_CLR */
2267 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80
2268 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 7
2269 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40
2270 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 6
2271 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20
2272 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 5
2273 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10
2274 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 4
2275 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08
2276 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 3
2277 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04
2278 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 2
2279 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02
2280 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 1
2281 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01
2282 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0
2284 /* Bit definitions for USB_VBUS_INT_EN_LO_SET */
2285 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80
2286 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 7
2287 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40
2288 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 6
2289 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20
2290 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 5
2291 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08
2292 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 3
2293 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04
2294 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 2
2295 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02
2296 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 1
2297 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01
2298 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0
2300 /* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
2301 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80
2302 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 7
2303 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40
2304 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 6
2305 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20
2306 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 5
2307 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08
2308 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 3
2309 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04
2310 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 2
2311 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02
2312 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 1
2313 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01
2314 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0
2316 /* Bit definitions for USB_VBUS_INT_EN_HI_SET */
2317 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80
2318 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 7
2319 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40
2320 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 6
2321 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20
2322 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 5
2323 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10
2324 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 4
2325 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08
2326 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 3
2327 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04
2328 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 2
2329 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02
2330 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 1
2331 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01
2332 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0
2334 /* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
2335 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80
2336 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 7
2337 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40
2338 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 6
2339 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20
2340 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 5
2341 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10
2342 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 4
2343 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08
2344 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 3
2345 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04
2346 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 2
2347 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02
2348 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 1
2349 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01
2350 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0
2352 /* Bit definitions for USB_ID_INT_SRC */
2353 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10
2354 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 4
2355 #define PALMAS_USB_ID_INT_SRC_ID_A 0x08
2356 #define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 3
2357 #define PALMAS_USB_ID_INT_SRC_ID_B 0x04
2358 #define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 2
2359 #define PALMAS_USB_ID_INT_SRC_ID_C 0x02
2360 #define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 1
2361 #define PALMAS_USB_ID_INT_SRC_ID_GND 0x01
2362 #define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0
2364 /* Bit definitions for USB_ID_INT_LATCH_SET */
2365 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10
2366 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 4
2367 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08
2368 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 3
2369 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04
2370 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 2
2371 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02
2372 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 1
2373 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01
2374 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0
2376 /* Bit definitions for USB_ID_INT_LATCH_CLR */
2377 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10
2378 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 4
2379 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08
2380 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 3
2381 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04
2382 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 2
2383 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02
2384 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 1
2385 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01
2386 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0
2388 /* Bit definitions for USB_ID_INT_EN_LO_SET */
2389 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10
2390 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 4
2391 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08
2392 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 3
2393 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04
2394 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 2
2395 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02
2396 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 1
2397 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01
2398 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0
2400 /* Bit definitions for USB_ID_INT_EN_LO_CLR */
2401 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10
2402 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 4
2403 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08
2404 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 3
2405 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04
2406 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 2
2407 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02
2408 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 1
2409 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01
2410 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0
2412 /* Bit definitions for USB_ID_INT_EN_HI_SET */
2413 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10
2414 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 4
2415 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08
2416 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 3
2417 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04
2418 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 2
2419 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02
2420 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 1
2421 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01
2422 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0
2424 /* Bit definitions for USB_ID_INT_EN_HI_CLR */
2425 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10
2426 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 4
2427 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08
2428 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 3
2429 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04
2430 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 2
2431 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02
2432 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 1
2433 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01
2434 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0
2436 /* Bit definitions for USB_OTG_ADP_CTRL */
2437 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04
2438 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 2
2439 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03
2440 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0
2442 /* Bit definitions for USB_OTG_ADP_HIGH */
2443 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xff
2444 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0
2446 /* Bit definitions for USB_OTG_ADP_LOW */
2447 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xff
2448 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0
2450 /* Bit definitions for USB_OTG_ADP_RISE */
2451 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xff
2452 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0
2454 /* Bit definitions for USB_OTG_REVISION */
2455 #define PALMAS_USB_OTG_REVISION_OTG_REV 0x01
2456 #define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0
2458 /* Registers for function VIBRATOR */
2459 #define PALMAS_VIBRA_CTRL 0x0
2461 /* Bit definitions for VIBRA_CTRL */
2462 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06
2463 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 1
2464 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01
2465 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0
2467 /* Registers for function GPIO */
2468 #define PALMAS_GPIO_DATA_IN 0x0
2469 #define PALMAS_GPIO_DATA_DIR 0x1
2470 #define PALMAS_GPIO_DATA_OUT 0x2
2471 #define PALMAS_GPIO_DEBOUNCE_EN 0x3
2472 #define PALMAS_GPIO_CLEAR_DATA_OUT 0x4
2473 #define PALMAS_GPIO_SET_DATA_OUT 0x5
2474 #define PALMAS_PU_PD_GPIO_CTRL1 0x6
2475 #define PALMAS_PU_PD_GPIO_CTRL2 0x7
2476 #define PALMAS_OD_OUTPUT_GPIO_CTRL 0x8
2478 /* Bit definitions for GPIO_DATA_IN */
2479 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80
2480 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 7
2481 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40
2482 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 6
2483 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20
2484 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 5
2485 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10
2486 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 4
2487 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08
2488 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 3
2489 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04
2490 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 2
2491 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02
2492 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 1
2493 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01
2494 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0
2496 /* Bit definitions for GPIO_DATA_DIR */
2497 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80
2498 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 7
2499 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40
2500 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 6
2501 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20
2502 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 5
2503 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10
2504 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 4
2505 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08
2506 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 3
2507 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04
2508 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 2
2509 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02
2510 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 1
2511 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01
2512 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0
2514 /* Bit definitions for GPIO_DATA_OUT */
2515 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80
2516 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 7
2517 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40
2518 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 6
2519 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20
2520 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 5
2521 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10
2522 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 4
2523 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08
2524 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 3
2525 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04
2526 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 2
2527 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02
2528 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 1
2529 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01
2530 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0
2532 /* Bit definitions for GPIO_DEBOUNCE_EN */
2533 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80
2534 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 7
2535 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40
2536 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 6
2537 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20
2538 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 5
2539 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10
2540 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 4
2541 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08
2542 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 3
2543 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04
2544 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 2
2545 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02
2546 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 1
2547 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01
2548 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0
2550 /* Bit definitions for GPIO_CLEAR_DATA_OUT */
2551 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80
2552 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 7
2553 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40
2554 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 6
2555 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20
2556 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 5
2557 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10
2558 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 4
2559 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08
2560 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 3
2561 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04
2562 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 2
2563 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02
2564 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 1
2565 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01
2566 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0
2568 /* Bit definitions for GPIO_SET_DATA_OUT */
2569 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80
2570 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 7
2571 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40
2572 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 6
2573 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20
2574 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 5
2575 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10
2576 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 4
2577 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08
2578 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 3
2579 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04
2580 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 2
2581 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02
2582 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 1
2583 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01
2584 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0
2586 /* Bit definitions for PU_PD_GPIO_CTRL1 */
2587 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40
2588 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 6
2589 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20
2590 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 5
2591 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10
2592 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 4
2593 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08
2594 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 3
2595 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04
2596 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 2
2597 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01
2598 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0
2600 /* Bit definitions for PU_PD_GPIO_CTRL2 */
2601 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40
2602 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 6
2603 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20
2604 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 5
2605 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10
2606 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 4
2607 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08
2608 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 3
2609 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04
2610 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 2
2611 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02
2612 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 1
2613 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01
2614 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0
2616 /* Bit definitions for OD_OUTPUT_GPIO_CTRL */
2617 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20
2618 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 5
2619 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04
2620 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 2
2621 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02
2622 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 1
2624 /* Registers for function GPADC */
2625 #define PALMAS_GPADC_CTRL1 0x0
2626 #define PALMAS_GPADC_CTRL2 0x1
2627 #define PALMAS_GPADC_RT_CTRL 0x2
2628 #define PALMAS_GPADC_AUTO_CTRL 0x3
2629 #define PALMAS_GPADC_STATUS 0x4
2630 #define PALMAS_GPADC_RT_SELECT 0x5
2631 #define PALMAS_GPADC_RT_CONV0_LSB 0x6
2632 #define PALMAS_GPADC_RT_CONV0_MSB 0x7
2633 #define PALMAS_GPADC_AUTO_SELECT 0x8
2634 #define PALMAS_GPADC_AUTO_CONV0_LSB 0x9
2635 #define PALMAS_GPADC_AUTO_CONV0_MSB 0xA
2636 #define PALMAS_GPADC_AUTO_CONV1_LSB 0xB
2637 #define PALMAS_GPADC_AUTO_CONV1_MSB 0xC
2638 #define PALMAS_GPADC_SW_SELECT 0xD
2639 #define PALMAS_GPADC_SW_CONV0_LSB 0xE
2640 #define PALMAS_GPADC_SW_CONV0_MSB 0xF
2641 #define PALMAS_GPADC_THRES_CONV0_LSB 0x10
2642 #define PALMAS_GPADC_THRES_CONV0_MSB 0x11
2643 #define PALMAS_GPADC_THRES_CONV1_LSB 0x12
2644 #define PALMAS_GPADC_THRES_CONV1_MSB 0x13
2645 #define PALMAS_GPADC_SMPS_ILMONITOR_EN 0x14
2646 #define PALMAS_GPADC_SMPS_VSEL_MONITORING 0x15
2648 /* Bit definitions for GPADC_CTRL1 */
2649 #define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0
2650 #define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 6
2651 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30
2652 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 4
2653 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c
2654 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 2
2655 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02
2656 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 1
2657 #define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01
2658 #define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0
2660 /* Bit definitions for GPADC_CTRL2 */
2661 #define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06
2662 #define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 1
2664 /* Bit definitions for GPADC_RT_CTRL */
2665 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02
2666 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 1
2667 #define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01
2668 #define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0
2670 /* Bit definitions for GPADC_AUTO_CTRL */
2671 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80
2672 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 7
2673 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40
2674 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 6
2675 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20
2676 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 5
2677 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10
2678 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 4
2679 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0f
2680 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0
2682 /* Bit definitions for GPADC_STATUS */
2683 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10
2684 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 4
2686 /* Bit definitions for GPADC_RT_SELECT */
2687 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80
2688 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 7
2689 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0f
2690 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0
2692 /* Bit definitions for GPADC_RT_CONV0_LSB */
2693 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xff
2694 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0
2696 /* Bit definitions for GPADC_RT_CONV0_MSB */
2697 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0f
2698 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0
2700 /* Bit definitions for GPADC_AUTO_SELECT */
2701 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xf0
2702 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 4
2703 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0f
2704 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0
2706 /* Bit definitions for GPADC_AUTO_CONV0_LSB */
2707 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xff
2708 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0
2710 /* Bit definitions for GPADC_AUTO_CONV0_MSB */
2711 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0f
2712 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0
2714 /* Bit definitions for GPADC_AUTO_CONV1_LSB */
2715 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xff
2716 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0
2718 /* Bit definitions for GPADC_AUTO_CONV1_MSB */
2719 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0f
2720 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0
2722 /* Bit definitions for GPADC_SW_SELECT */
2723 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80
2724 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 7
2725 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10
2726 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 4
2727 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0f
2728 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0
2730 /* Bit definitions for GPADC_SW_CONV0_LSB */
2731 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xff
2732 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0
2734 /* Bit definitions for GPADC_SW_CONV0_MSB */
2735 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0f
2736 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0
2738 /* Bit definitions for GPADC_THRES_CONV0_LSB */
2739 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xff
2740 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0
2742 /* Bit definitions for GPADC_THRES_CONV0_MSB */
2743 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80
2744 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 7
2745 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0f
2746 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0
2748 /* Bit definitions for GPADC_THRES_CONV1_LSB */
2749 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xff
2750 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0
2752 /* Bit definitions for GPADC_THRES_CONV1_MSB */
2753 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80
2754 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 7
2755 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0f
2756 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0
2758 /* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
2759 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20
2760 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 5
2761 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10
2762 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 4
2763 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0f
2764 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0
2766 /* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
2767 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80
2768 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 7
2769 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7f
2770 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0
2772 /* Registers for function GPADC */
2773 #define PALMAS_GPADC_TRIM1 0x0
2774 #define PALMAS_GPADC_TRIM2 0x1
2775 #define PALMAS_GPADC_TRIM3 0x2
2776 #define PALMAS_GPADC_TRIM4 0x3
2777 #define PALMAS_GPADC_TRIM5 0x4
2778 #define PALMAS_GPADC_TRIM6 0x5
2779 #define PALMAS_GPADC_TRIM7 0x6
2780 #define PALMAS_GPADC_TRIM8 0x7
2781 #define PALMAS_GPADC_TRIM9 0x8
2782 #define PALMAS_GPADC_TRIM10 0x9
2783 #define PALMAS_GPADC_TRIM11 0xA
2784 #define PALMAS_GPADC_TRIM12 0xB
2785 #define PALMAS_GPADC_TRIM13 0xC
2786 #define PALMAS_GPADC_TRIM14 0xD
2787 #define PALMAS_GPADC_TRIM15 0xE
2788 #define PALMAS_GPADC_TRIM16 0xF
2790 static inline int palmas_read(struct palmas *palmas, unsigned int base,
2791 unsigned int reg, unsigned int *val)
2793 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2794 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2796 return regmap_read(palmas->regmap[slave_id], addr, val);
2799 static inline int palmas_write(struct palmas *palmas, unsigned int base,
2800 unsigned int reg, unsigned int value)
2802 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2803 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2805 return regmap_write(palmas->regmap[slave_id], addr, value);
2808 static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base,
2809 unsigned int reg, const void *val, size_t val_count)
2811 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2812 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2814 return regmap_bulk_write(palmas->regmap[slave_id], addr,
2818 static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base,
2819 unsigned int reg, void *val, size_t val_count)
2821 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2822 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2824 return regmap_bulk_read(palmas->regmap[slave_id], addr,
2828 static inline int palmas_update_bits(struct palmas *palmas, unsigned int base,
2829 unsigned int reg, unsigned int mask, unsigned int val)
2831 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2832 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2834 return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val);
2837 static inline int palmas_irq_get_virq(struct palmas *palmas, int irq)
2839 return regmap_irq_get_virq(palmas->irq_data, irq);
2842 #endif /* __LINUX_MFD_PALMAS_H */