4 * Copyright 2011 Texas Instruments Inc.
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
15 #ifndef __LINUX_MFD_PALMAS_H
16 #define __LINUX_MFD_PALMAS_H
18 #include <linux/usb/otg.h>
19 #include <linux/leds.h>
20 #include <linux/regmap.h>
21 #include <linux/regulator/driver.h>
23 #define PALMAS_NUM_CLIENTS 3
27 struct palmas_resource;
33 struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
34 struct regmap *regmap[PALMAS_NUM_CLIENTS];
42 struct mutex irq_lock;
43 struct regmap_irq_chip_data *irq_data;
46 struct palmas_pmic *pmic;
47 struct palmas_gpadc *gpadc;
48 struct palmas_resource *resource;
49 struct palmas_usb *usb;
57 struct palmas_gpadc_platform_data {
58 /* Channel 3 current source is only enabled during conversion */
61 /* Channel 0 current source can be used for battery detection.
62 * If used for battery detection this will cause a permanent current
63 * consumption depending on current level set here.
67 /* default BAT_REMOVAL_DAT setting on device probe */
70 /* Sets the START_POLARITY bit in the RT_CTRL register */
74 struct palmas_reg_init {
75 /* warm_rest controls the voltage levels after a warm reset
77 * 0: reload default values from OTP on warm reset
78 * 1: maintain voltage from VSEL on warm reset
82 /* roof_floor controls whether the regulator uses the i2c style
83 * of DVS or uses the method where a GPIO or other control method is
84 * attached to the NSLEEP/ENABLE1/ENABLE2 pins
88 * 0: i2c selection of voltage
89 * 1: pin selection of voltage.
95 /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
112 /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
113 * register. Set this is the default voltage set in OTP needs
120 enum palmas_regulators {
121 /* SMPS regulators */
144 /* External regulators */
150 /* Total number of regulators */
154 struct palmas_pmic_platform_data {
155 /* An array of pointers to regulator init data indexed by regulator
158 struct regulator_init_data *reg_data[PALMAS_NUM_REGS];
160 /* An array of pointers to structures containing sleep mode and DVS
161 * configuration for regulators indexed by ID
163 struct palmas_reg_init *reg_init[PALMAS_NUM_REGS];
165 /* use LDO6 for vibrator control */
168 /* Enable tracking mode of LDO8 */
169 bool enable_ldo8_tracking;
172 struct palmas_usb_platform_data {
173 /* Set this if platform wishes its own vbus control */
176 /* Do we enable the wakeup comparator on probe */
180 struct palmas_resource_platform_data {
181 int regen1_mode_sleep;
182 int regen2_mode_sleep;
183 int sysen1_mode_sleep;
184 int sysen2_mode_sleep;
186 /* bitfield to be loaded to NSLEEP_RES_ASSIGN */
188 /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */
190 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */
192 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */
195 /* bitfield to be loaded to ENABLE1_RES_ASSIGN */
197 /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */
199 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */
201 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */
204 /* bitfield to be loaded to ENABLE2_RES_ASSIGN */
206 /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */
208 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */
210 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */
214 struct palmas_clk_platform_data {
215 int clk32kg_mode_sleep;
216 int clk32kgaudio_mode_sleep;
219 struct palmas_platform_data {
222 /* bit value to be loaded to the POWER_CTRL register */
226 * boolean to select if we want to configure muxing here
227 * then the two value to load into the registers if true
232 struct palmas_pmic_platform_data *pmic_pdata;
233 struct palmas_gpadc_platform_data *gpadc_pdata;
234 struct palmas_usb_platform_data *usb_pdata;
235 struct palmas_resource_platform_data *resource_pdata;
236 struct palmas_clk_platform_data *clk_pdata;
239 struct palmas_gpadc_calibration {
245 struct palmas_gpadc {
247 struct palmas *palmas;
256 struct mutex reading_lock;
257 struct completion irq_complete;
261 struct palmas_gpadc_calibration *palmas_cal_tbl;
268 struct palmas_gpadc_result {
274 #define PALMAS_MAX_CHANNELS 16
276 /* Define the palmas IRQ numbers */
279 PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
281 PALMAS_LONG_PRESS_KEY_IRQ,
288 PALMAS_RTC_ALARM_IRQ,
289 PALMAS_RTC_TIMER_IRQ,
291 PALMAS_BATREMOVAL_IRQ,
297 PALMAS_GPADC_AUTO_0_IRQ,
298 PALMAS_GPADC_AUTO_1_IRQ,
299 PALMAS_GPADC_EOC_SW_IRQ,
300 PALMAS_GPADC_EOC_RT_IRQ,
314 /* Total Number IRQs */
319 struct palmas *palmas;
321 struct regulator_desc desc[PALMAS_NUM_REGS];
322 struct regulator_dev *rdev[PALMAS_NUM_REGS];
328 int range[PALMAS_REG_SMPS10];
329 unsigned int ramp_delay[PALMAS_REG_SMPS10];
332 struct palmas_resource {
333 struct palmas *palmas;
338 struct palmas *palmas;
341 /* for vbus reporting with irqs disabled */
344 struct regulator *vbus_reg;
346 /* used to set vbus, in atomic path */
347 struct work_struct set_vbus_work;
359 #define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)
361 enum usb_irq_events {
362 /* Wakeup events from INT3 */
363 PALMAS_USB_ID_WAKEPUP,
364 PALMAS_USB_VBUS_WAKEUP,
376 N_PALMAS_USB_ID_FLOAT,
378 /* VBUS_OTG_EVENTS */
379 PALMAS_USB_VB_SESS_END,
380 N_PALMAS_USB_VB_SESS_END,
381 PALMAS_USB_VB_SESS_VLD,
382 N_PALMAS_USB_VB_SESS_VLD,
383 PALMAS_USB_VA_SESS_VLD,
384 N_PALMAS_USB_VA_SESS_VLD,
385 PALMAS_USB_VA_VBUS_VLD,
386 N_PALMAS_USB_VA_VBUS_VLD,
388 N_PALMAS_USB_VADP_SNS,
390 N_PALMAS_USB_VADP_PRB,
391 PALMAS_USB_VOTG_SESS_VLD,
392 N_PALMAS_USB_VOTG_SESS_VLD,
395 /* defines so we can store the mux settings */
396 #define PALMAS_GPIO_0_MUXED (1 << 0)
397 #define PALMAS_GPIO_1_MUXED (1 << 1)
398 #define PALMAS_GPIO_2_MUXED (1 << 2)
399 #define PALMAS_GPIO_3_MUXED (1 << 3)
400 #define PALMAS_GPIO_4_MUXED (1 << 4)
401 #define PALMAS_GPIO_5_MUXED (1 << 5)
402 #define PALMAS_GPIO_6_MUXED (1 << 6)
403 #define PALMAS_GPIO_7_MUXED (1 << 7)
405 #define PALMAS_LED1_MUXED (1 << 0)
406 #define PALMAS_LED2_MUXED (1 << 1)
408 #define PALMAS_PWM1_MUXED (1 << 0)
409 #define PALMAS_PWM2_MUXED (1 << 1)
411 /* helper macro to get correct slave number */
412 #define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1)
413 #define PALMAS_BASE_TO_REG(x, y) ((x & 0xff) + y)
415 /* Base addresses of IP blocks in Palmas */
416 #define PALMAS_SMPS_DVS_BASE 0x20
417 #define PALMAS_RTC_BASE 0x100
418 #define PALMAS_VALIDITY_BASE 0x118
419 #define PALMAS_SMPS_BASE 0x120
420 #define PALMAS_LDO_BASE 0x150
421 #define PALMAS_DVFS_BASE 0x180
422 #define PALMAS_PMU_CONTROL_BASE 0x1A0
423 #define PALMAS_RESOURCE_BASE 0x1D4
424 #define PALMAS_PU_PD_OD_BASE 0x1F4
425 #define PALMAS_LED_BASE 0x200
426 #define PALMAS_INTERRUPT_BASE 0x210
427 #define PALMAS_USB_OTG_BASE 0x250
428 #define PALMAS_VIBRATOR_BASE 0x270
429 #define PALMAS_GPIO_BASE 0x280
430 #define PALMAS_USB_BASE 0x290
431 #define PALMAS_GPADC_BASE 0x2C0
432 #define PALMAS_TRIM_GPADC_BASE 0x3CD
434 /* Registers for function RTC */
435 #define PALMAS_SECONDS_REG 0x0
436 #define PALMAS_MINUTES_REG 0x1
437 #define PALMAS_HOURS_REG 0x2
438 #define PALMAS_DAYS_REG 0x3
439 #define PALMAS_MONTHS_REG 0x4
440 #define PALMAS_YEARS_REG 0x5
441 #define PALMAS_WEEKS_REG 0x6
442 #define PALMAS_ALARM_SECONDS_REG 0x8
443 #define PALMAS_ALARM_MINUTES_REG 0x9
444 #define PALMAS_ALARM_HOURS_REG 0xA
445 #define PALMAS_ALARM_DAYS_REG 0xB
446 #define PALMAS_ALARM_MONTHS_REG 0xC
447 #define PALMAS_ALARM_YEARS_REG 0xD
448 #define PALMAS_RTC_CTRL_REG 0x10
449 #define PALMAS_RTC_STATUS_REG 0x11
450 #define PALMAS_RTC_INTERRUPTS_REG 0x12
451 #define PALMAS_RTC_COMP_LSB_REG 0x13
452 #define PALMAS_RTC_COMP_MSB_REG 0x14
453 #define PALMAS_RTC_RES_PROG_REG 0x15
454 #define PALMAS_RTC_RESET_STATUS_REG 0x16
456 /* Bit definitions for SECONDS_REG */
457 #define PALMAS_SECONDS_REG_SEC1_MASK 0x70
458 #define PALMAS_SECONDS_REG_SEC1_SHIFT 4
459 #define PALMAS_SECONDS_REG_SEC0_MASK 0x0f
460 #define PALMAS_SECONDS_REG_SEC0_SHIFT 0
462 /* Bit definitions for MINUTES_REG */
463 #define PALMAS_MINUTES_REG_MIN1_MASK 0x70
464 #define PALMAS_MINUTES_REG_MIN1_SHIFT 4
465 #define PALMAS_MINUTES_REG_MIN0_MASK 0x0f
466 #define PALMAS_MINUTES_REG_MIN0_SHIFT 0
468 /* Bit definitions for HOURS_REG */
469 #define PALMAS_HOURS_REG_PM_NAM 0x80
470 #define PALMAS_HOURS_REG_PM_NAM_SHIFT 7
471 #define PALMAS_HOURS_REG_HOUR1_MASK 0x30
472 #define PALMAS_HOURS_REG_HOUR1_SHIFT 4
473 #define PALMAS_HOURS_REG_HOUR0_MASK 0x0f
474 #define PALMAS_HOURS_REG_HOUR0_SHIFT 0
476 /* Bit definitions for DAYS_REG */
477 #define PALMAS_DAYS_REG_DAY1_MASK 0x30
478 #define PALMAS_DAYS_REG_DAY1_SHIFT 4
479 #define PALMAS_DAYS_REG_DAY0_MASK 0x0f
480 #define PALMAS_DAYS_REG_DAY0_SHIFT 0
482 /* Bit definitions for MONTHS_REG */
483 #define PALMAS_MONTHS_REG_MONTH1 0x10
484 #define PALMAS_MONTHS_REG_MONTH1_SHIFT 4
485 #define PALMAS_MONTHS_REG_MONTH0_MASK 0x0f
486 #define PALMAS_MONTHS_REG_MONTH0_SHIFT 0
488 /* Bit definitions for YEARS_REG */
489 #define PALMAS_YEARS_REG_YEAR1_MASK 0xf0
490 #define PALMAS_YEARS_REG_YEAR1_SHIFT 4
491 #define PALMAS_YEARS_REG_YEAR0_MASK 0x0f
492 #define PALMAS_YEARS_REG_YEAR0_SHIFT 0
494 /* Bit definitions for WEEKS_REG */
495 #define PALMAS_WEEKS_REG_WEEK_MASK 0x07
496 #define PALMAS_WEEKS_REG_WEEK_SHIFT 0
498 /* Bit definitions for ALARM_SECONDS_REG */
499 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70
500 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 4
501 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0f
502 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0
504 /* Bit definitions for ALARM_MINUTES_REG */
505 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70
506 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 4
507 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0f
508 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0
510 /* Bit definitions for ALARM_HOURS_REG */
511 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80
512 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 7
513 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30
514 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 4
515 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0f
516 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0
518 /* Bit definitions for ALARM_DAYS_REG */
519 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30
520 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 4
521 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0f
522 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0
524 /* Bit definitions for ALARM_MONTHS_REG */
525 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10
526 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 4
527 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0f
528 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0
530 /* Bit definitions for ALARM_YEARS_REG */
531 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0
532 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 4
533 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0f
534 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0
536 /* Bit definitions for RTC_CTRL_REG */
537 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80
538 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 7
539 #define PALMAS_RTC_CTRL_REG_GET_TIME 0x40
540 #define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 6
541 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20
542 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 5
543 #define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10
544 #define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 4
545 #define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08
546 #define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 3
547 #define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04
548 #define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 2
549 #define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02
550 #define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 1
551 #define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01
552 #define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0
554 /* Bit definitions for RTC_STATUS_REG */
555 #define PALMAS_RTC_STATUS_REG_POWER_UP 0x80
556 #define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 7
557 #define PALMAS_RTC_STATUS_REG_ALARM 0x40
558 #define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 6
559 #define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20
560 #define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 5
561 #define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10
562 #define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 4
563 #define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08
564 #define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 3
565 #define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04
566 #define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 2
567 #define PALMAS_RTC_STATUS_REG_RUN 0x02
568 #define PALMAS_RTC_STATUS_REG_RUN_SHIFT 1
570 /* Bit definitions for RTC_INTERRUPTS_REG */
571 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10
572 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 4
573 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08
574 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 3
575 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04
576 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 2
577 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03
578 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0
580 /* Bit definitions for RTC_COMP_LSB_REG */
581 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xff
582 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0
584 /* Bit definitions for RTC_COMP_MSB_REG */
585 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xff
586 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0
588 /* Bit definitions for RTC_RES_PROG_REG */
589 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3f
590 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0
592 /* Bit definitions for RTC_RESET_STATUS_REG */
593 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01
594 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0
596 /* Registers for function BACKUP */
597 #define PALMAS_BACKUP0 0x0
598 #define PALMAS_BACKUP1 0x1
599 #define PALMAS_BACKUP2 0x2
600 #define PALMAS_BACKUP3 0x3
601 #define PALMAS_BACKUP4 0x4
602 #define PALMAS_BACKUP5 0x5
603 #define PALMAS_BACKUP6 0x6
604 #define PALMAS_BACKUP7 0x7
606 /* Bit definitions for BACKUP0 */
607 #define PALMAS_BACKUP0_BACKUP_MASK 0xff
608 #define PALMAS_BACKUP0_BACKUP_SHIFT 0
610 /* Bit definitions for BACKUP1 */
611 #define PALMAS_BACKUP1_BACKUP_MASK 0xff
612 #define PALMAS_BACKUP1_BACKUP_SHIFT 0
614 /* Bit definitions for BACKUP2 */
615 #define PALMAS_BACKUP2_BACKUP_MASK 0xff
616 #define PALMAS_BACKUP2_BACKUP_SHIFT 0
618 /* Bit definitions for BACKUP3 */
619 #define PALMAS_BACKUP3_BACKUP_MASK 0xff
620 #define PALMAS_BACKUP3_BACKUP_SHIFT 0
622 /* Bit definitions for BACKUP4 */
623 #define PALMAS_BACKUP4_BACKUP_MASK 0xff
624 #define PALMAS_BACKUP4_BACKUP_SHIFT 0
626 /* Bit definitions for BACKUP5 */
627 #define PALMAS_BACKUP5_BACKUP_MASK 0xff
628 #define PALMAS_BACKUP5_BACKUP_SHIFT 0
630 /* Bit definitions for BACKUP6 */
631 #define PALMAS_BACKUP6_BACKUP_MASK 0xff
632 #define PALMAS_BACKUP6_BACKUP_SHIFT 0
634 /* Bit definitions for BACKUP7 */
635 #define PALMAS_BACKUP7_BACKUP_MASK 0xff
636 #define PALMAS_BACKUP7_BACKUP_SHIFT 0
638 /* Registers for function SMPS */
639 #define PALMAS_SMPS12_CTRL 0x0
640 #define PALMAS_SMPS12_TSTEP 0x1
641 #define PALMAS_SMPS12_FORCE 0x2
642 #define PALMAS_SMPS12_VOLTAGE 0x3
643 #define PALMAS_SMPS3_CTRL 0x4
644 #define PALMAS_SMPS3_VOLTAGE 0x7
645 #define PALMAS_SMPS45_CTRL 0x8
646 #define PALMAS_SMPS45_TSTEP 0x9
647 #define PALMAS_SMPS45_FORCE 0xA
648 #define PALMAS_SMPS45_VOLTAGE 0xB
649 #define PALMAS_SMPS6_CTRL 0xC
650 #define PALMAS_SMPS6_TSTEP 0xD
651 #define PALMAS_SMPS6_FORCE 0xE
652 #define PALMAS_SMPS6_VOLTAGE 0xF
653 #define PALMAS_SMPS7_CTRL 0x10
654 #define PALMAS_SMPS7_VOLTAGE 0x13
655 #define PALMAS_SMPS8_CTRL 0x14
656 #define PALMAS_SMPS8_TSTEP 0x15
657 #define PALMAS_SMPS8_FORCE 0x16
658 #define PALMAS_SMPS8_VOLTAGE 0x17
659 #define PALMAS_SMPS9_CTRL 0x18
660 #define PALMAS_SMPS9_VOLTAGE 0x1B
661 #define PALMAS_SMPS10_CTRL 0x1C
662 #define PALMAS_SMPS10_STATUS 0x1F
663 #define PALMAS_SMPS_CTRL 0x24
664 #define PALMAS_SMPS_PD_CTRL 0x25
665 #define PALMAS_SMPS_DITHER_EN 0x26
666 #define PALMAS_SMPS_THERMAL_EN 0x27
667 #define PALMAS_SMPS_THERMAL_STATUS 0x28
668 #define PALMAS_SMPS_SHORT_STATUS 0x29
669 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
670 #define PALMAS_SMPS_POWERGOOD_MASK1 0x2B
671 #define PALMAS_SMPS_POWERGOOD_MASK2 0x2C
673 /* Bit definitions for SMPS12_CTRL */
674 #define PALMAS_SMPS12_CTRL_WR_S 0x80
675 #define PALMAS_SMPS12_CTRL_WR_S_SHIFT 7
676 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40
677 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 6
678 #define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30
679 #define PALMAS_SMPS12_CTRL_STATUS_SHIFT 4
680 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c
681 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 2
682 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03
683 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0
685 /* Bit definitions for SMPS12_TSTEP */
686 #define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03
687 #define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0
689 /* Bit definitions for SMPS12_FORCE */
690 #define PALMAS_SMPS12_FORCE_CMD 0x80
691 #define PALMAS_SMPS12_FORCE_CMD_SHIFT 7
692 #define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7f
693 #define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0
695 /* Bit definitions for SMPS12_VOLTAGE */
696 #define PALMAS_SMPS12_VOLTAGE_RANGE 0x80
697 #define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 7
698 #define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7f
699 #define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0
701 /* Bit definitions for SMPS3_CTRL */
702 #define PALMAS_SMPS3_CTRL_WR_S 0x80
703 #define PALMAS_SMPS3_CTRL_WR_S_SHIFT 7
704 #define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30
705 #define PALMAS_SMPS3_CTRL_STATUS_SHIFT 4
706 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c
707 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 2
708 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
709 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0
711 /* Bit definitions for SMPS3_VOLTAGE */
712 #define PALMAS_SMPS3_VOLTAGE_RANGE 0x80
713 #define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 7
714 #define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7f
715 #define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0
717 /* Bit definitions for SMPS45_CTRL */
718 #define PALMAS_SMPS45_CTRL_WR_S 0x80
719 #define PALMAS_SMPS45_CTRL_WR_S_SHIFT 7
720 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40
721 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 6
722 #define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30
723 #define PALMAS_SMPS45_CTRL_STATUS_SHIFT 4
724 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c
725 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 2
726 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03
727 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0
729 /* Bit definitions for SMPS45_TSTEP */
730 #define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03
731 #define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0
733 /* Bit definitions for SMPS45_FORCE */
734 #define PALMAS_SMPS45_FORCE_CMD 0x80
735 #define PALMAS_SMPS45_FORCE_CMD_SHIFT 7
736 #define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7f
737 #define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0
739 /* Bit definitions for SMPS45_VOLTAGE */
740 #define PALMAS_SMPS45_VOLTAGE_RANGE 0x80
741 #define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 7
742 #define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7f
743 #define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0
745 /* Bit definitions for SMPS6_CTRL */
746 #define PALMAS_SMPS6_CTRL_WR_S 0x80
747 #define PALMAS_SMPS6_CTRL_WR_S_SHIFT 7
748 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40
749 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 6
750 #define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30
751 #define PALMAS_SMPS6_CTRL_STATUS_SHIFT 4
752 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c
753 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 2
754 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03
755 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0
757 /* Bit definitions for SMPS6_TSTEP */
758 #define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03
759 #define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0
761 /* Bit definitions for SMPS6_FORCE */
762 #define PALMAS_SMPS6_FORCE_CMD 0x80
763 #define PALMAS_SMPS6_FORCE_CMD_SHIFT 7
764 #define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7f
765 #define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0
767 /* Bit definitions for SMPS6_VOLTAGE */
768 #define PALMAS_SMPS6_VOLTAGE_RANGE 0x80
769 #define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 7
770 #define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7f
771 #define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0
773 /* Bit definitions for SMPS7_CTRL */
774 #define PALMAS_SMPS7_CTRL_WR_S 0x80
775 #define PALMAS_SMPS7_CTRL_WR_S_SHIFT 7
776 #define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30
777 #define PALMAS_SMPS7_CTRL_STATUS_SHIFT 4
778 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c
779 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 2
780 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03
781 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0
783 /* Bit definitions for SMPS7_VOLTAGE */
784 #define PALMAS_SMPS7_VOLTAGE_RANGE 0x80
785 #define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 7
786 #define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7f
787 #define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0
789 /* Bit definitions for SMPS8_CTRL */
790 #define PALMAS_SMPS8_CTRL_WR_S 0x80
791 #define PALMAS_SMPS8_CTRL_WR_S_SHIFT 7
792 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40
793 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 6
794 #define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30
795 #define PALMAS_SMPS8_CTRL_STATUS_SHIFT 4
796 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c
797 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 2
798 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03
799 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0
801 /* Bit definitions for SMPS8_TSTEP */
802 #define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03
803 #define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0
805 /* Bit definitions for SMPS8_FORCE */
806 #define PALMAS_SMPS8_FORCE_CMD 0x80
807 #define PALMAS_SMPS8_FORCE_CMD_SHIFT 7
808 #define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7f
809 #define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0
811 /* Bit definitions for SMPS8_VOLTAGE */
812 #define PALMAS_SMPS8_VOLTAGE_RANGE 0x80
813 #define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 7
814 #define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7f
815 #define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0
817 /* Bit definitions for SMPS9_CTRL */
818 #define PALMAS_SMPS9_CTRL_WR_S 0x80
819 #define PALMAS_SMPS9_CTRL_WR_S_SHIFT 7
820 #define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30
821 #define PALMAS_SMPS9_CTRL_STATUS_SHIFT 4
822 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c
823 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 2
824 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03
825 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0
827 /* Bit definitions for SMPS9_VOLTAGE */
828 #define PALMAS_SMPS9_VOLTAGE_RANGE 0x80
829 #define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 7
830 #define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7f
831 #define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0
833 /* Bit definitions for SMPS10_CTRL */
834 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0
835 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 4
836 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0f
837 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0
839 /* Bit definitions for SMPS10_STATUS */
840 #define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0f
841 #define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0
843 /* Bit definitions for SMPS_CTRL */
844 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20
845 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 5
846 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10
847 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 4
848 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c
849 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 2
850 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03
851 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0
853 /* Bit definitions for SMPS_PD_CTRL */
854 #define PALMAS_SMPS_PD_CTRL_SMPS9 0x40
855 #define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 6
856 #define PALMAS_SMPS_PD_CTRL_SMPS8 0x20
857 #define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 5
858 #define PALMAS_SMPS_PD_CTRL_SMPS7 0x10
859 #define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 4
860 #define PALMAS_SMPS_PD_CTRL_SMPS6 0x08
861 #define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 3
862 #define PALMAS_SMPS_PD_CTRL_SMPS45 0x04
863 #define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 2
864 #define PALMAS_SMPS_PD_CTRL_SMPS3 0x02
865 #define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 1
866 #define PALMAS_SMPS_PD_CTRL_SMPS12 0x01
867 #define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0
869 /* Bit definitions for SMPS_THERMAL_EN */
870 #define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40
871 #define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 6
872 #define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20
873 #define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 5
874 #define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08
875 #define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 3
876 #define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04
877 #define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 2
878 #define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01
879 #define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0
881 /* Bit definitions for SMPS_THERMAL_STATUS */
882 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40
883 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 6
884 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20
885 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 5
886 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08
887 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 3
888 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04
889 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 2
890 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01
891 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0
893 /* Bit definitions for SMPS_SHORT_STATUS */
894 #define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80
895 #define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 7
896 #define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40
897 #define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 6
898 #define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20
899 #define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 5
900 #define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10
901 #define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 4
902 #define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08
903 #define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 3
904 #define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04
905 #define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 2
906 #define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02
907 #define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 1
908 #define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01
909 #define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0
911 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
912 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40
913 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 6
914 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20
915 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 5
916 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10
917 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 4
918 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08
919 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 3
920 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04
921 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 2
922 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02
923 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 1
924 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01
925 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0
927 /* Bit definitions for SMPS_POWERGOOD_MASK1 */
928 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80
929 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 7
930 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40
931 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 6
932 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20
933 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 5
934 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10
935 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 4
936 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08
937 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 3
938 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04
939 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 2
940 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02
941 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 1
942 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01
943 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0
945 /* Bit definitions for SMPS_POWERGOOD_MASK2 */
946 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
947 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7
948 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04
949 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 2
950 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02
951 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 1
952 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01
953 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0
955 /* Registers for function LDO */
956 #define PALMAS_LDO1_CTRL 0x0
957 #define PALMAS_LDO1_VOLTAGE 0x1
958 #define PALMAS_LDO2_CTRL 0x2
959 #define PALMAS_LDO2_VOLTAGE 0x3
960 #define PALMAS_LDO3_CTRL 0x4
961 #define PALMAS_LDO3_VOLTAGE 0x5
962 #define PALMAS_LDO4_CTRL 0x6
963 #define PALMAS_LDO4_VOLTAGE 0x7
964 #define PALMAS_LDO5_CTRL 0x8
965 #define PALMAS_LDO5_VOLTAGE 0x9
966 #define PALMAS_LDO6_CTRL 0xA
967 #define PALMAS_LDO6_VOLTAGE 0xB
968 #define PALMAS_LDO7_CTRL 0xC
969 #define PALMAS_LDO7_VOLTAGE 0xD
970 #define PALMAS_LDO8_CTRL 0xE
971 #define PALMAS_LDO8_VOLTAGE 0xF
972 #define PALMAS_LDO9_CTRL 0x10
973 #define PALMAS_LDO9_VOLTAGE 0x11
974 #define PALMAS_LDOLN_CTRL 0x12
975 #define PALMAS_LDOLN_VOLTAGE 0x13
976 #define PALMAS_LDOUSB_CTRL 0x14
977 #define PALMAS_LDOUSB_VOLTAGE 0x15
978 #define PALMAS_LDO_CTRL 0x1A
979 #define PALMAS_LDO_PD_CTRL1 0x1B
980 #define PALMAS_LDO_PD_CTRL2 0x1C
981 #define PALMAS_LDO_SHORT_STATUS1 0x1D
982 #define PALMAS_LDO_SHORT_STATUS2 0x1E
984 /* Bit definitions for LDO1_CTRL */
985 #define PALMAS_LDO1_CTRL_WR_S 0x80
986 #define PALMAS_LDO1_CTRL_WR_S_SHIFT 7
987 #define PALMAS_LDO1_CTRL_STATUS 0x10
988 #define PALMAS_LDO1_CTRL_STATUS_SHIFT 4
989 #define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04
990 #define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 2
991 #define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01
992 #define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0
994 /* Bit definitions for LDO1_VOLTAGE */
995 #define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3f
996 #define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0
998 /* Bit definitions for LDO2_CTRL */
999 #define PALMAS_LDO2_CTRL_WR_S 0x80
1000 #define PALMAS_LDO2_CTRL_WR_S_SHIFT 7
1001 #define PALMAS_LDO2_CTRL_STATUS 0x10
1002 #define PALMAS_LDO2_CTRL_STATUS_SHIFT 4
1003 #define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04
1004 #define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 2
1005 #define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01
1006 #define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0
1008 /* Bit definitions for LDO2_VOLTAGE */
1009 #define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3f
1010 #define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0
1012 /* Bit definitions for LDO3_CTRL */
1013 #define PALMAS_LDO3_CTRL_WR_S 0x80
1014 #define PALMAS_LDO3_CTRL_WR_S_SHIFT 7
1015 #define PALMAS_LDO3_CTRL_STATUS 0x10
1016 #define PALMAS_LDO3_CTRL_STATUS_SHIFT 4
1017 #define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04
1018 #define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 2
1019 #define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01
1020 #define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0
1022 /* Bit definitions for LDO3_VOLTAGE */
1023 #define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3f
1024 #define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0
1026 /* Bit definitions for LDO4_CTRL */
1027 #define PALMAS_LDO4_CTRL_WR_S 0x80
1028 #define PALMAS_LDO4_CTRL_WR_S_SHIFT 7
1029 #define PALMAS_LDO4_CTRL_STATUS 0x10
1030 #define PALMAS_LDO4_CTRL_STATUS_SHIFT 4
1031 #define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04
1032 #define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 2
1033 #define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01
1034 #define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0
1036 /* Bit definitions for LDO4_VOLTAGE */
1037 #define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3f
1038 #define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0
1040 /* Bit definitions for LDO5_CTRL */
1041 #define PALMAS_LDO5_CTRL_WR_S 0x80
1042 #define PALMAS_LDO5_CTRL_WR_S_SHIFT 7
1043 #define PALMAS_LDO5_CTRL_STATUS 0x10
1044 #define PALMAS_LDO5_CTRL_STATUS_SHIFT 4
1045 #define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04
1046 #define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 2
1047 #define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01
1048 #define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0
1050 /* Bit definitions for LDO5_VOLTAGE */
1051 #define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3f
1052 #define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0
1054 /* Bit definitions for LDO6_CTRL */
1055 #define PALMAS_LDO6_CTRL_WR_S 0x80
1056 #define PALMAS_LDO6_CTRL_WR_S_SHIFT 7
1057 #define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40
1058 #define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 6
1059 #define PALMAS_LDO6_CTRL_STATUS 0x10
1060 #define PALMAS_LDO6_CTRL_STATUS_SHIFT 4
1061 #define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04
1062 #define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 2
1063 #define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01
1064 #define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0
1066 /* Bit definitions for LDO6_VOLTAGE */
1067 #define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3f
1068 #define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0
1070 /* Bit definitions for LDO7_CTRL */
1071 #define PALMAS_LDO7_CTRL_WR_S 0x80
1072 #define PALMAS_LDO7_CTRL_WR_S_SHIFT 7
1073 #define PALMAS_LDO7_CTRL_STATUS 0x10
1074 #define PALMAS_LDO7_CTRL_STATUS_SHIFT 4
1075 #define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04
1076 #define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 2
1077 #define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01
1078 #define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0
1080 /* Bit definitions for LDO7_VOLTAGE */
1081 #define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3f
1082 #define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0
1084 /* Bit definitions for LDO8_CTRL */
1085 #define PALMAS_LDO8_CTRL_WR_S 0x80
1086 #define PALMAS_LDO8_CTRL_WR_S_SHIFT 7
1087 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40
1088 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 6
1089 #define PALMAS_LDO8_CTRL_STATUS 0x10
1090 #define PALMAS_LDO8_CTRL_STATUS_SHIFT 4
1091 #define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04
1092 #define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 2
1093 #define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01
1094 #define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0
1096 /* Bit definitions for LDO8_VOLTAGE */
1097 #define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3f
1098 #define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0
1100 /* Bit definitions for LDO9_CTRL */
1101 #define PALMAS_LDO9_CTRL_WR_S 0x80
1102 #define PALMAS_LDO9_CTRL_WR_S_SHIFT 7
1103 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40
1104 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 6
1105 #define PALMAS_LDO9_CTRL_STATUS 0x10
1106 #define PALMAS_LDO9_CTRL_STATUS_SHIFT 4
1107 #define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04
1108 #define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 2
1109 #define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01
1110 #define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0
1112 /* Bit definitions for LDO9_VOLTAGE */
1113 #define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3f
1114 #define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0
1116 /* Bit definitions for LDOLN_CTRL */
1117 #define PALMAS_LDOLN_CTRL_WR_S 0x80
1118 #define PALMAS_LDOLN_CTRL_WR_S_SHIFT 7
1119 #define PALMAS_LDOLN_CTRL_STATUS 0x10
1120 #define PALMAS_LDOLN_CTRL_STATUS_SHIFT 4
1121 #define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04
1122 #define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 2
1123 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01
1124 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0
1126 /* Bit definitions for LDOLN_VOLTAGE */
1127 #define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3f
1128 #define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0
1130 /* Bit definitions for LDOUSB_CTRL */
1131 #define PALMAS_LDOUSB_CTRL_WR_S 0x80
1132 #define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 7
1133 #define PALMAS_LDOUSB_CTRL_STATUS 0x10
1134 #define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 4
1135 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04
1136 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 2
1137 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01
1138 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0
1140 /* Bit definitions for LDOUSB_VOLTAGE */
1141 #define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3f
1142 #define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0
1144 /* Bit definitions for LDO_CTRL */
1145 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01
1146 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0
1148 /* Bit definitions for LDO_PD_CTRL1 */
1149 #define PALMAS_LDO_PD_CTRL1_LDO8 0x80
1150 #define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 7
1151 #define PALMAS_LDO_PD_CTRL1_LDO7 0x40
1152 #define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 6
1153 #define PALMAS_LDO_PD_CTRL1_LDO6 0x20
1154 #define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 5
1155 #define PALMAS_LDO_PD_CTRL1_LDO5 0x10
1156 #define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 4
1157 #define PALMAS_LDO_PD_CTRL1_LDO4 0x08
1158 #define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 3
1159 #define PALMAS_LDO_PD_CTRL1_LDO3 0x04
1160 #define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 2
1161 #define PALMAS_LDO_PD_CTRL1_LDO2 0x02
1162 #define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 1
1163 #define PALMAS_LDO_PD_CTRL1_LDO1 0x01
1164 #define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0
1166 /* Bit definitions for LDO_PD_CTRL2 */
1167 #define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04
1168 #define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 2
1169 #define PALMAS_LDO_PD_CTRL2_LDOLN 0x02
1170 #define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 1
1171 #define PALMAS_LDO_PD_CTRL2_LDO9 0x01
1172 #define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0
1174 /* Bit definitions for LDO_SHORT_STATUS1 */
1175 #define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80
1176 #define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 7
1177 #define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40
1178 #define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 6
1179 #define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20
1180 #define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 5
1181 #define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10
1182 #define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 4
1183 #define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08
1184 #define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 3
1185 #define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04
1186 #define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 2
1187 #define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02
1188 #define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 1
1189 #define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01
1190 #define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0
1192 /* Bit definitions for LDO_SHORT_STATUS2 */
1193 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08
1194 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 3
1195 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04
1196 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 2
1197 #define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02
1198 #define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 1
1199 #define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01
1200 #define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0
1202 /* Registers for function PMU_CONTROL */
1203 #define PALMAS_DEV_CTRL 0x0
1204 #define PALMAS_POWER_CTRL 0x1
1205 #define PALMAS_VSYS_LO 0x2
1206 #define PALMAS_VSYS_MON 0x3
1207 #define PALMAS_VBAT_MON 0x4
1208 #define PALMAS_WATCHDOG 0x5
1209 #define PALMAS_BOOT_STATUS 0x6
1210 #define PALMAS_BATTERY_BOUNCE 0x7
1211 #define PALMAS_BACKUP_BATTERY_CTRL 0x8
1212 #define PALMAS_LONG_PRESS_KEY 0x9
1213 #define PALMAS_OSC_THERM_CTRL 0xA
1214 #define PALMAS_BATDEBOUNCING 0xB
1215 #define PALMAS_SWOFF_HWRST 0xF
1216 #define PALMAS_SWOFF_COLDRST 0x10
1217 #define PALMAS_SWOFF_STATUS 0x11
1218 #define PALMAS_PMU_CONFIG 0x12
1219 #define PALMAS_SPARE 0x14
1220 #define PALMAS_PMU_SECONDARY_INT 0x15
1221 #define PALMAS_SW_REVISION 0x17
1222 #define PALMAS_EXT_CHRG_CTRL 0x18
1223 #define PALMAS_PMU_SECONDARY_INT2 0x19
1225 /* Bit definitions for DEV_CTRL */
1226 #define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c
1227 #define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 2
1228 #define PALMAS_DEV_CTRL_SW_RST 0x02
1229 #define PALMAS_DEV_CTRL_SW_RST_SHIFT 1
1230 #define PALMAS_DEV_CTRL_DEV_ON 0x01
1231 #define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0
1233 /* Bit definitions for POWER_CTRL */
1234 #define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04
1235 #define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 2
1236 #define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02
1237 #define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 1
1238 #define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01
1239 #define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0
1241 /* Bit definitions for VSYS_LO */
1242 #define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1f
1243 #define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0
1245 /* Bit definitions for VSYS_MON */
1246 #define PALMAS_VSYS_MON_ENABLE 0x80
1247 #define PALMAS_VSYS_MON_ENABLE_SHIFT 7
1248 #define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3f
1249 #define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0
1251 /* Bit definitions for VBAT_MON */
1252 #define PALMAS_VBAT_MON_ENABLE 0x80
1253 #define PALMAS_VBAT_MON_ENABLE_SHIFT 7
1254 #define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3f
1255 #define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0
1257 /* Bit definitions for WATCHDOG */
1258 #define PALMAS_WATCHDOG_LOCK 0x20
1259 #define PALMAS_WATCHDOG_LOCK_SHIFT 5
1260 #define PALMAS_WATCHDOG_ENABLE 0x10
1261 #define PALMAS_WATCHDOG_ENABLE_SHIFT 4
1262 #define PALMAS_WATCHDOG_MODE 0x08
1263 #define PALMAS_WATCHDOG_MODE_SHIFT 3
1264 #define PALMAS_WATCHDOG_TIMER_MASK 0x07
1265 #define PALMAS_WATCHDOG_TIMER_SHIFT 0
1267 /* Bit definitions for BOOT_STATUS */
1268 #define PALMAS_BOOT_STATUS_BOOT1 0x02
1269 #define PALMAS_BOOT_STATUS_BOOT1_SHIFT 1
1270 #define PALMAS_BOOT_STATUS_BOOT0 0x01
1271 #define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0
1273 /* Bit definitions for BATTERY_BOUNCE */
1274 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3f
1275 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0
1277 /* Bit definitions for BACKUP_BATTERY_CTRL */
1278 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80
1279 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 7
1280 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40
1281 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 6
1282 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20
1283 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 5
1284 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10
1285 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 4
1286 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08
1287 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 3
1288 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06
1289 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 1
1290 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01
1291 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0
1293 /* Bit definitions for LONG_PRESS_KEY */
1294 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80
1295 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 7
1296 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10
1297 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 4
1298 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c
1299 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 2
1300 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03
1301 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0
1303 /* Bit definitions for OSC_THERM_CTRL */
1304 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80
1305 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 7
1306 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40
1307 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 6
1308 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20
1309 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 5
1310 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10
1311 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 4
1312 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c
1313 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 2
1314 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02
1315 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 1
1316 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01
1317 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0
1319 /* Bit definitions for BATDEBOUNCING */
1320 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80
1321 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 7
1322 #define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78
1323 #define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 3
1324 #define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07
1325 #define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0
1327 /* Bit definitions for SWOFF_HWRST */
1328 #define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80
1329 #define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 7
1330 #define PALMAS_SWOFF_HWRST_PWRDOWN 0x40
1331 #define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 6
1332 #define PALMAS_SWOFF_HWRST_WTD 0x20
1333 #define PALMAS_SWOFF_HWRST_WTD_SHIFT 5
1334 #define PALMAS_SWOFF_HWRST_TSHUT 0x10
1335 #define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 4
1336 #define PALMAS_SWOFF_HWRST_RESET_IN 0x08
1337 #define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 3
1338 #define PALMAS_SWOFF_HWRST_SW_RST 0x04
1339 #define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 2
1340 #define PALMAS_SWOFF_HWRST_VSYS_LO 0x02
1341 #define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 1
1342 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01
1343 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0
1345 /* Bit definitions for SWOFF_COLDRST */
1346 #define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80
1347 #define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 7
1348 #define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40
1349 #define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 6
1350 #define PALMAS_SWOFF_COLDRST_WTD 0x20
1351 #define PALMAS_SWOFF_COLDRST_WTD_SHIFT 5
1352 #define PALMAS_SWOFF_COLDRST_TSHUT 0x10
1353 #define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 4
1354 #define PALMAS_SWOFF_COLDRST_RESET_IN 0x08
1355 #define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 3
1356 #define PALMAS_SWOFF_COLDRST_SW_RST 0x04
1357 #define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 2
1358 #define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02
1359 #define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 1
1360 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01
1361 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0
1363 /* Bit definitions for SWOFF_STATUS */
1364 #define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80
1365 #define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 7
1366 #define PALMAS_SWOFF_STATUS_PWRDOWN 0x40
1367 #define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 6
1368 #define PALMAS_SWOFF_STATUS_WTD 0x20
1369 #define PALMAS_SWOFF_STATUS_WTD_SHIFT 5
1370 #define PALMAS_SWOFF_STATUS_TSHUT 0x10
1371 #define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 4
1372 #define PALMAS_SWOFF_STATUS_RESET_IN 0x08
1373 #define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 3
1374 #define PALMAS_SWOFF_STATUS_SW_RST 0x04
1375 #define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 2
1376 #define PALMAS_SWOFF_STATUS_VSYS_LO 0x02
1377 #define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 1
1378 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01
1379 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0
1381 /* Bit definitions for PMU_CONFIG */
1382 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40
1383 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 6
1384 #define PALMAS_PMU_CONFIG_SPARE_MASK 0x30
1385 #define PALMAS_PMU_CONFIG_SPARE_SHIFT 4
1386 #define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c
1387 #define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 2
1388 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02
1389 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 1
1390 #define PALMAS_PMU_CONFIG_AUTODEVON 0x01
1391 #define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0
1393 /* Bit definitions for SPARE */
1394 #define PALMAS_SPARE_SPARE_MASK 0xf8
1395 #define PALMAS_SPARE_SPARE_SHIFT 3
1396 #define PALMAS_SPARE_REGEN3_OD 0x04
1397 #define PALMAS_SPARE_REGEN3_OD_SHIFT 2
1398 #define PALMAS_SPARE_REGEN2_OD 0x02
1399 #define PALMAS_SPARE_REGEN2_OD_SHIFT 1
1400 #define PALMAS_SPARE_REGEN1_OD 0x01
1401 #define PALMAS_SPARE_REGEN1_OD_SHIFT 0
1403 /* Bit definitions for PMU_SECONDARY_INT */
1404 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80
1405 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 7
1406 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40
1407 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 6
1408 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20
1409 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 5
1410 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10
1411 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 4
1412 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08
1413 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 3
1414 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04
1415 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 2
1416 #define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02
1417 #define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 1
1418 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01
1419 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0
1421 /* Bit definitions for SW_REVISION */
1422 #define PALMAS_SW_REVISION_SW_REVISION_MASK 0xff
1423 #define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0
1425 /* Bit definitions for EXT_CHRG_CTRL */
1426 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80
1427 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 7
1428 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40
1429 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 6
1430 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08
1431 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 3
1432 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04
1433 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 2
1434 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02
1435 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 1
1436 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01
1437 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0
1439 /* Bit definitions for PMU_SECONDARY_INT2 */
1440 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20
1441 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 5
1442 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10
1443 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 4
1444 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02
1445 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 1
1446 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01
1447 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0
1449 /* Registers for function RESOURCE */
1450 #define PALMAS_CLK32KG_CTRL 0x0
1451 #define PALMAS_CLK32KGAUDIO_CTRL 0x1
1452 #define PALMAS_REGEN1_CTRL 0x2
1453 #define PALMAS_REGEN2_CTRL 0x3
1454 #define PALMAS_SYSEN1_CTRL 0x4
1455 #define PALMAS_SYSEN2_CTRL 0x5
1456 #define PALMAS_NSLEEP_RES_ASSIGN 0x6
1457 #define PALMAS_NSLEEP_SMPS_ASSIGN 0x7
1458 #define PALMAS_NSLEEP_LDO_ASSIGN1 0x8
1459 #define PALMAS_NSLEEP_LDO_ASSIGN2 0x9
1460 #define PALMAS_ENABLE1_RES_ASSIGN 0xA
1461 #define PALMAS_ENABLE1_SMPS_ASSIGN 0xB
1462 #define PALMAS_ENABLE1_LDO_ASSIGN1 0xC
1463 #define PALMAS_ENABLE1_LDO_ASSIGN2 0xD
1464 #define PALMAS_ENABLE2_RES_ASSIGN 0xE
1465 #define PALMAS_ENABLE2_SMPS_ASSIGN 0xF
1466 #define PALMAS_ENABLE2_LDO_ASSIGN1 0x10
1467 #define PALMAS_ENABLE2_LDO_ASSIGN2 0x11
1468 #define PALMAS_REGEN3_CTRL 0x12
1470 /* Bit definitions for CLK32KG_CTRL */
1471 #define PALMAS_CLK32KG_CTRL_STATUS 0x10
1472 #define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 4
1473 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04
1474 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 2
1475 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01
1476 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0
1478 /* Bit definitions for CLK32KGAUDIO_CTRL */
1479 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10
1480 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 4
1481 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08
1482 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 3
1483 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04
1484 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 2
1485 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01
1486 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0
1488 /* Bit definitions for REGEN1_CTRL */
1489 #define PALMAS_REGEN1_CTRL_STATUS 0x10
1490 #define PALMAS_REGEN1_CTRL_STATUS_SHIFT 4
1491 #define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04
1492 #define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 2
1493 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01
1494 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0
1496 /* Bit definitions for REGEN2_CTRL */
1497 #define PALMAS_REGEN2_CTRL_STATUS 0x10
1498 #define PALMAS_REGEN2_CTRL_STATUS_SHIFT 4
1499 #define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04
1500 #define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 2
1501 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01
1502 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0
1504 /* Bit definitions for SYSEN1_CTRL */
1505 #define PALMAS_SYSEN1_CTRL_STATUS 0x10
1506 #define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 4
1507 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04
1508 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 2
1509 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01
1510 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0
1512 /* Bit definitions for SYSEN2_CTRL */
1513 #define PALMAS_SYSEN2_CTRL_STATUS 0x10
1514 #define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 4
1515 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04
1516 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 2
1517 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01
1518 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0
1520 /* Bit definitions for NSLEEP_RES_ASSIGN */
1521 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40
1522 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 6
1523 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20
1524 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5
1525 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10
1526 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 4
1527 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08
1528 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 3
1529 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04
1530 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 2
1531 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02
1532 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 1
1533 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01
1534 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0
1536 /* Bit definitions for NSLEEP_SMPS_ASSIGN */
1537 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80
1538 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 7
1539 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40
1540 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 6
1541 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20
1542 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 5
1543 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10
1544 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 4
1545 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08
1546 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 3
1547 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04
1548 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 2
1549 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02
1550 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 1
1551 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01
1552 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0
1554 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */
1555 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80
1556 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 7
1557 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40
1558 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 6
1559 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20
1560 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 5
1561 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10
1562 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 4
1563 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08
1564 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 3
1565 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04
1566 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 2
1567 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02
1568 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 1
1569 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01
1570 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0
1572 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */
1573 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04
1574 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 2
1575 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02
1576 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 1
1577 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01
1578 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0
1580 /* Bit definitions for ENABLE1_RES_ASSIGN */
1581 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40
1582 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 6
1583 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20
1584 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5
1585 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10
1586 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 4
1587 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08
1588 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 3
1589 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04
1590 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 2
1591 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02
1592 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 1
1593 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01
1594 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0
1596 /* Bit definitions for ENABLE1_SMPS_ASSIGN */
1597 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80
1598 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 7
1599 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40
1600 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 6
1601 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20
1602 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 5
1603 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10
1604 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 4
1605 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08
1606 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 3
1607 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04
1608 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 2
1609 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02
1610 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 1
1611 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01
1612 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0
1614 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */
1615 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80
1616 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 7
1617 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40
1618 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 6
1619 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20
1620 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 5
1621 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10
1622 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 4
1623 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08
1624 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 3
1625 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04
1626 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 2
1627 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02
1628 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 1
1629 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01
1630 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0
1632 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */
1633 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04
1634 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 2
1635 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02
1636 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 1
1637 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01
1638 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0
1640 /* Bit definitions for ENABLE2_RES_ASSIGN */
1641 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40
1642 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 6
1643 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20
1644 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5
1645 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10
1646 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 4
1647 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08
1648 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 3
1649 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04
1650 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 2
1651 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02
1652 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 1
1653 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01
1654 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0
1656 /* Bit definitions for ENABLE2_SMPS_ASSIGN */
1657 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80
1658 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 7
1659 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40
1660 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 6
1661 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20
1662 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 5
1663 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10
1664 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 4
1665 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08
1666 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 3
1667 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04
1668 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 2
1669 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02
1670 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 1
1671 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01
1672 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0
1674 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */
1675 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80
1676 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 7
1677 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40
1678 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 6
1679 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20
1680 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 5
1681 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10
1682 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 4
1683 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08
1684 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 3
1685 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04
1686 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 2
1687 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02
1688 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 1
1689 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01
1690 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0
1692 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */
1693 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04
1694 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 2
1695 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02
1696 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 1
1697 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01
1698 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0
1700 /* Bit definitions for REGEN3_CTRL */
1701 #define PALMAS_REGEN3_CTRL_STATUS 0x10
1702 #define PALMAS_REGEN3_CTRL_STATUS_SHIFT 4
1703 #define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04
1704 #define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 2
1705 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01
1706 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0
1708 /* Registers for function PAD_CONTROL */
1709 #define PALMAS_PU_PD_INPUT_CTRL1 0x0
1710 #define PALMAS_PU_PD_INPUT_CTRL2 0x1
1711 #define PALMAS_PU_PD_INPUT_CTRL3 0x2
1712 #define PALMAS_OD_OUTPUT_CTRL 0x4
1713 #define PALMAS_POLARITY_CTRL 0x5
1714 #define PALMAS_PRIMARY_SECONDARY_PAD1 0x6
1715 #define PALMAS_PRIMARY_SECONDARY_PAD2 0x7
1716 #define PALMAS_I2C_SPI 0x8
1717 #define PALMAS_PU_PD_INPUT_CTRL4 0x9
1718 #define PALMAS_PRIMARY_SECONDARY_PAD3 0xA
1720 /* Bit definitions for PU_PD_INPUT_CTRL1 */
1721 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40
1722 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 6
1723 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20
1724 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 5
1725 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10
1726 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 4
1727 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04
1728 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 2
1729 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02
1730 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 1
1732 /* Bit definitions for PU_PD_INPUT_CTRL2 */
1733 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20
1734 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 5
1735 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10
1736 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 4
1737 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08
1738 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 3
1739 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04
1740 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 2
1741 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02
1742 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 1
1743 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01
1744 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0
1746 /* Bit definitions for PU_PD_INPUT_CTRL3 */
1747 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40
1748 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 6
1749 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10
1750 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 4
1751 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04
1752 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 2
1753 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01
1754 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0
1756 /* Bit definitions for OD_OUTPUT_CTRL */
1757 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80
1758 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 7
1759 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40
1760 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 6
1761 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20
1762 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 5
1763 #define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08
1764 #define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 3
1766 /* Bit definitions for POLARITY_CTRL */
1767 #define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80
1768 #define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 7
1769 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40
1770 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 6
1771 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20
1772 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 5
1773 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10
1774 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 4
1775 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08
1776 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 3
1777 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04
1778 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 2
1779 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02
1780 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 1
1781 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01
1782 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0
1784 /* Bit definitions for PRIMARY_SECONDARY_PAD1 */
1785 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80
1786 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 7
1787 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60
1788 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 5
1789 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18
1790 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 3
1791 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04
1792 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 2
1793 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02
1794 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 1
1795 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01
1796 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0
1798 /* Bit definitions for PRIMARY_SECONDARY_PAD2 */
1799 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30
1800 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 4
1801 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08
1802 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 3
1803 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06
1804 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 1
1805 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01
1806 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0
1808 /* Bit definitions for I2C_SPI */
1809 #define PALMAS_I2C_SPI_I2C2OTP_EN 0x80
1810 #define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 7
1811 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40
1812 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 6
1813 #define PALMAS_I2C_SPI_ID_I2C2 0x20
1814 #define PALMAS_I2C_SPI_ID_I2C2_SHIFT 5
1815 #define PALMAS_I2C_SPI_I2C_SPI 0x10
1816 #define PALMAS_I2C_SPI_I2C_SPI_SHIFT 4
1817 #define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0f
1818 #define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0
1820 /* Bit definitions for PU_PD_INPUT_CTRL4 */
1821 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40
1822 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 6
1823 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10
1824 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 4
1825 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04
1826 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 2
1827 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01
1828 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0
1830 /* Bit definitions for PRIMARY_SECONDARY_PAD3 */
1831 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02
1832 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 1
1833 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01
1834 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0
1836 /* Registers for function LED_PWM */
1837 #define PALMAS_LED_PERIOD_CTRL 0x0
1838 #define PALMAS_LED_CTRL 0x1
1839 #define PALMAS_PWM_CTRL1 0x2
1840 #define PALMAS_PWM_CTRL2 0x3
1842 /* Bit definitions for LED_PERIOD_CTRL */
1843 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38
1844 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 3
1845 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07
1846 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0
1848 /* Bit definitions for LED_CTRL */
1849 #define PALMAS_LED_CTRL_LED_2_SEQ 0x20
1850 #define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 5
1851 #define PALMAS_LED_CTRL_LED_1_SEQ 0x10
1852 #define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 4
1853 #define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c
1854 #define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 2
1855 #define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03
1856 #define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0
1858 /* Bit definitions for PWM_CTRL1 */
1859 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02
1860 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 1
1861 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01
1862 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0
1864 /* Bit definitions for PWM_CTRL2 */
1865 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xff
1866 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0
1868 /* Registers for function INTERRUPT */
1869 #define PALMAS_INT1_STATUS 0x0
1870 #define PALMAS_INT1_MASK 0x1
1871 #define PALMAS_INT1_LINE_STATE 0x2
1872 #define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x3
1873 #define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x4
1874 #define PALMAS_INT2_STATUS 0x5
1875 #define PALMAS_INT2_MASK 0x6
1876 #define PALMAS_INT2_LINE_STATE 0x7
1877 #define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x8
1878 #define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x9
1879 #define PALMAS_INT3_STATUS 0xA
1880 #define PALMAS_INT3_MASK 0xB
1881 #define PALMAS_INT3_LINE_STATE 0xC
1882 #define PALMAS_INT3_EDGE_DETECT1_RESERVED 0xD
1883 #define PALMAS_INT3_EDGE_DETECT2_RESERVED 0xE
1884 #define PALMAS_INT4_STATUS 0xF
1885 #define PALMAS_INT4_MASK 0x10
1886 #define PALMAS_INT4_LINE_STATE 0x11
1887 #define PALMAS_INT4_EDGE_DETECT1 0x12
1888 #define PALMAS_INT4_EDGE_DETECT2 0x13
1889 #define PALMAS_INT_CTRL 0x14
1891 /* Bit definitions for INT1_STATUS */
1892 #define PALMAS_INT1_STATUS_VBAT_MON 0x80
1893 #define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 7
1894 #define PALMAS_INT1_STATUS_VSYS_MON 0x40
1895 #define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 6
1896 #define PALMAS_INT1_STATUS_HOTDIE 0x20
1897 #define PALMAS_INT1_STATUS_HOTDIE_SHIFT 5
1898 #define PALMAS_INT1_STATUS_PWRDOWN 0x10
1899 #define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 4
1900 #define PALMAS_INT1_STATUS_RPWRON 0x08
1901 #define PALMAS_INT1_STATUS_RPWRON_SHIFT 3
1902 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04
1903 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 2
1904 #define PALMAS_INT1_STATUS_PWRON 0x02
1905 #define PALMAS_INT1_STATUS_PWRON_SHIFT 1
1906 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01
1907 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0
1909 /* Bit definitions for INT1_MASK */
1910 #define PALMAS_INT1_MASK_VBAT_MON 0x80
1911 #define PALMAS_INT1_MASK_VBAT_MON_SHIFT 7
1912 #define PALMAS_INT1_MASK_VSYS_MON 0x40
1913 #define PALMAS_INT1_MASK_VSYS_MON_SHIFT 6
1914 #define PALMAS_INT1_MASK_HOTDIE 0x20
1915 #define PALMAS_INT1_MASK_HOTDIE_SHIFT 5
1916 #define PALMAS_INT1_MASK_PWRDOWN 0x10
1917 #define PALMAS_INT1_MASK_PWRDOWN_SHIFT 4
1918 #define PALMAS_INT1_MASK_RPWRON 0x08
1919 #define PALMAS_INT1_MASK_RPWRON_SHIFT 3
1920 #define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04
1921 #define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 2
1922 #define PALMAS_INT1_MASK_PWRON 0x02
1923 #define PALMAS_INT1_MASK_PWRON_SHIFT 1
1924 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01
1925 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0
1927 /* Bit definitions for INT1_LINE_STATE */
1928 #define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80
1929 #define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 7
1930 #define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40
1931 #define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 6
1932 #define PALMAS_INT1_LINE_STATE_HOTDIE 0x20
1933 #define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 5
1934 #define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10
1935 #define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 4
1936 #define PALMAS_INT1_LINE_STATE_RPWRON 0x08
1937 #define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 3
1938 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
1939 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 2
1940 #define PALMAS_INT1_LINE_STATE_PWRON 0x02
1941 #define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 1
1942 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01
1943 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0
1945 /* Bit definitions for INT2_STATUS */
1946 #define PALMAS_INT2_STATUS_VAC_ACOK 0x80
1947 #define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 7
1948 #define PALMAS_INT2_STATUS_SHORT 0x40
1949 #define PALMAS_INT2_STATUS_SHORT_SHIFT 6
1950 #define PALMAS_INT2_STATUS_FBI_BB 0x20
1951 #define PALMAS_INT2_STATUS_FBI_BB_SHIFT 5
1952 #define PALMAS_INT2_STATUS_RESET_IN 0x10
1953 #define PALMAS_INT2_STATUS_RESET_IN_SHIFT 4
1954 #define PALMAS_INT2_STATUS_BATREMOVAL 0x08
1955 #define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 3
1956 #define PALMAS_INT2_STATUS_WDT 0x04
1957 #define PALMAS_INT2_STATUS_WDT_SHIFT 2
1958 #define PALMAS_INT2_STATUS_RTC_TIMER 0x02
1959 #define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 1
1960 #define PALMAS_INT2_STATUS_RTC_ALARM 0x01
1961 #define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0
1963 /* Bit definitions for INT2_MASK */
1964 #define PALMAS_INT2_MASK_VAC_ACOK 0x80
1965 #define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 7
1966 #define PALMAS_INT2_MASK_SHORT 0x40
1967 #define PALMAS_INT2_MASK_SHORT_SHIFT 6
1968 #define PALMAS_INT2_MASK_FBI_BB 0x20
1969 #define PALMAS_INT2_MASK_FBI_BB_SHIFT 5
1970 #define PALMAS_INT2_MASK_RESET_IN 0x10
1971 #define PALMAS_INT2_MASK_RESET_IN_SHIFT 4
1972 #define PALMAS_INT2_MASK_BATREMOVAL 0x08
1973 #define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 3
1974 #define PALMAS_INT2_MASK_WDT 0x04
1975 #define PALMAS_INT2_MASK_WDT_SHIFT 2
1976 #define PALMAS_INT2_MASK_RTC_TIMER 0x02
1977 #define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 1
1978 #define PALMAS_INT2_MASK_RTC_ALARM 0x01
1979 #define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0
1981 /* Bit definitions for INT2_LINE_STATE */
1982 #define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80
1983 #define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 7
1984 #define PALMAS_INT2_LINE_STATE_SHORT 0x40
1985 #define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 6
1986 #define PALMAS_INT2_LINE_STATE_FBI_BB 0x20
1987 #define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 5
1988 #define PALMAS_INT2_LINE_STATE_RESET_IN 0x10
1989 #define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 4
1990 #define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08
1991 #define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 3
1992 #define PALMAS_INT2_LINE_STATE_WDT 0x04
1993 #define PALMAS_INT2_LINE_STATE_WDT_SHIFT 2
1994 #define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02
1995 #define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 1
1996 #define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01
1997 #define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0
1999 /* Bit definitions for INT3_STATUS */
2000 #define PALMAS_INT3_STATUS_VBUS 0x80
2001 #define PALMAS_INT3_STATUS_VBUS_SHIFT 7
2002 #define PALMAS_INT3_STATUS_VBUS_OTG 0x40
2003 #define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 6
2004 #define PALMAS_INT3_STATUS_ID 0x20
2005 #define PALMAS_INT3_STATUS_ID_SHIFT 5
2006 #define PALMAS_INT3_STATUS_ID_OTG 0x10
2007 #define PALMAS_INT3_STATUS_ID_OTG_SHIFT 4
2008 #define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08
2009 #define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 3
2010 #define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04
2011 #define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 2
2012 #define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02
2013 #define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 1
2014 #define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01
2015 #define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0
2017 /* Bit definitions for INT3_MASK */
2018 #define PALMAS_INT3_MASK_VBUS 0x80
2019 #define PALMAS_INT3_MASK_VBUS_SHIFT 7
2020 #define PALMAS_INT3_MASK_VBUS_OTG 0x40
2021 #define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 6
2022 #define PALMAS_INT3_MASK_ID 0x20
2023 #define PALMAS_INT3_MASK_ID_SHIFT 5
2024 #define PALMAS_INT3_MASK_ID_OTG 0x10
2025 #define PALMAS_INT3_MASK_ID_OTG_SHIFT 4
2026 #define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08
2027 #define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 3
2028 #define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04
2029 #define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 2
2030 #define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02
2031 #define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 1
2032 #define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01
2033 #define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0
2035 /* Bit definitions for INT3_LINE_STATE */
2036 #define PALMAS_INT3_LINE_STATE_VBUS 0x80
2037 #define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 7
2038 #define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40
2039 #define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 6
2040 #define PALMAS_INT3_LINE_STATE_ID 0x20
2041 #define PALMAS_INT3_LINE_STATE_ID_SHIFT 5
2042 #define PALMAS_INT3_LINE_STATE_ID_OTG 0x10
2043 #define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 4
2044 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08
2045 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 3
2046 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04
2047 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 2
2048 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02
2049 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 1
2050 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01
2051 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0
2053 /* Bit definitions for INT4_STATUS */
2054 #define PALMAS_INT4_STATUS_GPIO_7 0x80
2055 #define PALMAS_INT4_STATUS_GPIO_7_SHIFT 7
2056 #define PALMAS_INT4_STATUS_GPIO_6 0x40
2057 #define PALMAS_INT4_STATUS_GPIO_6_SHIFT 6
2058 #define PALMAS_INT4_STATUS_GPIO_5 0x20
2059 #define PALMAS_INT4_STATUS_GPIO_5_SHIFT 5
2060 #define PALMAS_INT4_STATUS_GPIO_4 0x10
2061 #define PALMAS_INT4_STATUS_GPIO_4_SHIFT 4
2062 #define PALMAS_INT4_STATUS_GPIO_3 0x08
2063 #define PALMAS_INT4_STATUS_GPIO_3_SHIFT 3
2064 #define PALMAS_INT4_STATUS_GPIO_2 0x04
2065 #define PALMAS_INT4_STATUS_GPIO_2_SHIFT 2
2066 #define PALMAS_INT4_STATUS_GPIO_1 0x02
2067 #define PALMAS_INT4_STATUS_GPIO_1_SHIFT 1
2068 #define PALMAS_INT4_STATUS_GPIO_0 0x01
2069 #define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0
2071 /* Bit definitions for INT4_MASK */
2072 #define PALMAS_INT4_MASK_GPIO_7 0x80
2073 #define PALMAS_INT4_MASK_GPIO_7_SHIFT 7
2074 #define PALMAS_INT4_MASK_GPIO_6 0x40
2075 #define PALMAS_INT4_MASK_GPIO_6_SHIFT 6
2076 #define PALMAS_INT4_MASK_GPIO_5 0x20
2077 #define PALMAS_INT4_MASK_GPIO_5_SHIFT 5
2078 #define PALMAS_INT4_MASK_GPIO_4 0x10
2079 #define PALMAS_INT4_MASK_GPIO_4_SHIFT 4
2080 #define PALMAS_INT4_MASK_GPIO_3 0x08
2081 #define PALMAS_INT4_MASK_GPIO_3_SHIFT 3
2082 #define PALMAS_INT4_MASK_GPIO_2 0x04
2083 #define PALMAS_INT4_MASK_GPIO_2_SHIFT 2
2084 #define PALMAS_INT4_MASK_GPIO_1 0x02
2085 #define PALMAS_INT4_MASK_GPIO_1_SHIFT 1
2086 #define PALMAS_INT4_MASK_GPIO_0 0x01
2087 #define PALMAS_INT4_MASK_GPIO_0_SHIFT 0
2089 /* Bit definitions for INT4_LINE_STATE */
2090 #define PALMAS_INT4_LINE_STATE_GPIO_7 0x80
2091 #define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 7
2092 #define PALMAS_INT4_LINE_STATE_GPIO_6 0x40
2093 #define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 6
2094 #define PALMAS_INT4_LINE_STATE_GPIO_5 0x20
2095 #define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 5
2096 #define PALMAS_INT4_LINE_STATE_GPIO_4 0x10
2097 #define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 4
2098 #define PALMAS_INT4_LINE_STATE_GPIO_3 0x08
2099 #define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 3
2100 #define PALMAS_INT4_LINE_STATE_GPIO_2 0x04
2101 #define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 2
2102 #define PALMAS_INT4_LINE_STATE_GPIO_1 0x02
2103 #define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 1
2104 #define PALMAS_INT4_LINE_STATE_GPIO_0 0x01
2105 #define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0
2107 /* Bit definitions for INT4_EDGE_DETECT1 */
2108 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
2109 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 7
2110 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
2111 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 6
2112 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
2113 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 5
2114 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
2115 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 4
2116 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
2117 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 3
2118 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
2119 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 2
2120 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
2121 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 1
2122 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
2123 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0
2125 /* Bit definitions for INT4_EDGE_DETECT2 */
2126 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80
2127 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 7
2128 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40
2129 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 6
2130 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
2131 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 5
2132 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
2133 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 4
2134 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
2135 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 3
2136 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
2137 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 2
2138 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
2139 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 1
2140 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
2141 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0
2143 /* Bit definitions for INT_CTRL */
2144 #define PALMAS_INT_CTRL_INT_PENDING 0x04
2145 #define PALMAS_INT_CTRL_INT_PENDING_SHIFT 2
2146 #define PALMAS_INT_CTRL_INT_CLEAR 0x01
2147 #define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0
2149 /* Registers for function USB_OTG */
2150 #define PALMAS_USB_WAKEUP 0x3
2151 #define PALMAS_USB_VBUS_CTRL_SET 0x4
2152 #define PALMAS_USB_VBUS_CTRL_CLR 0x5
2153 #define PALMAS_USB_ID_CTRL_SET 0x6
2154 #define PALMAS_USB_ID_CTRL_CLEAR 0x7
2155 #define PALMAS_USB_VBUS_INT_SRC 0x8
2156 #define PALMAS_USB_VBUS_INT_LATCH_SET 0x9
2157 #define PALMAS_USB_VBUS_INT_LATCH_CLR 0xA
2158 #define PALMAS_USB_VBUS_INT_EN_LO_SET 0xB
2159 #define PALMAS_USB_VBUS_INT_EN_LO_CLR 0xC
2160 #define PALMAS_USB_VBUS_INT_EN_HI_SET 0xD
2161 #define PALMAS_USB_VBUS_INT_EN_HI_CLR 0xE
2162 #define PALMAS_USB_ID_INT_SRC 0xF
2163 #define PALMAS_USB_ID_INT_LATCH_SET 0x10
2164 #define PALMAS_USB_ID_INT_LATCH_CLR 0x11
2165 #define PALMAS_USB_ID_INT_EN_LO_SET 0x12
2166 #define PALMAS_USB_ID_INT_EN_LO_CLR 0x13
2167 #define PALMAS_USB_ID_INT_EN_HI_SET 0x14
2168 #define PALMAS_USB_ID_INT_EN_HI_CLR 0x15
2169 #define PALMAS_USB_OTG_ADP_CTRL 0x16
2170 #define PALMAS_USB_OTG_ADP_HIGH 0x17
2171 #define PALMAS_USB_OTG_ADP_LOW 0x18
2172 #define PALMAS_USB_OTG_ADP_RISE 0x19
2173 #define PALMAS_USB_OTG_REVISION 0x1A
2175 /* Bit definitions for USB_WAKEUP */
2176 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01
2177 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0
2179 /* Bit definitions for USB_VBUS_CTRL_SET */
2180 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80
2181 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 7
2182 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20
2183 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 5
2184 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10
2185 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 4
2186 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08
2187 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 3
2188 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04
2189 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 2
2191 /* Bit definitions for USB_VBUS_CTRL_CLR */
2192 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80
2193 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 7
2194 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20
2195 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 5
2196 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10
2197 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 4
2198 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08
2199 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 3
2200 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04
2201 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 2
2203 /* Bit definitions for USB_ID_CTRL_SET */
2204 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80
2205 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 7
2206 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40
2207 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 6
2208 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20
2209 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 5
2210 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10
2211 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 4
2212 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08
2213 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 3
2214 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04
2215 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 2
2217 /* Bit definitions for USB_ID_CTRL_CLEAR */
2218 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80
2219 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 7
2220 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40
2221 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 6
2222 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20
2223 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 5
2224 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10
2225 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 4
2226 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08
2227 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 3
2228 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04
2229 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 2
2231 /* Bit definitions for USB_VBUS_INT_SRC */
2232 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80
2233 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 7
2234 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40
2235 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 6
2236 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20
2237 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 5
2238 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08
2239 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 3
2240 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04
2241 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 2
2242 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02
2243 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 1
2244 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01
2245 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0
2247 /* Bit definitions for USB_VBUS_INT_LATCH_SET */
2248 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80
2249 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 7
2250 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40
2251 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 6
2252 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20
2253 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 5
2254 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10
2255 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 4
2256 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08
2257 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 3
2258 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04
2259 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 2
2260 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02
2261 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 1
2262 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01
2263 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0
2265 /* Bit definitions for USB_VBUS_INT_LATCH_CLR */
2266 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80
2267 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 7
2268 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40
2269 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 6
2270 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20
2271 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 5
2272 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10
2273 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 4
2274 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08
2275 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 3
2276 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04
2277 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 2
2278 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02
2279 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 1
2280 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01
2281 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0
2283 /* Bit definitions for USB_VBUS_INT_EN_LO_SET */
2284 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80
2285 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 7
2286 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40
2287 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 6
2288 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20
2289 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 5
2290 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08
2291 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 3
2292 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04
2293 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 2
2294 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02
2295 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 1
2296 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01
2297 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0
2299 /* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
2300 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80
2301 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 7
2302 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40
2303 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 6
2304 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20
2305 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 5
2306 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08
2307 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 3
2308 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04
2309 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 2
2310 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02
2311 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 1
2312 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01
2313 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0
2315 /* Bit definitions for USB_VBUS_INT_EN_HI_SET */
2316 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80
2317 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 7
2318 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40
2319 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 6
2320 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20
2321 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 5
2322 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10
2323 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 4
2324 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08
2325 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 3
2326 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04
2327 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 2
2328 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02
2329 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 1
2330 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01
2331 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0
2333 /* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
2334 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80
2335 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 7
2336 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40
2337 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 6
2338 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20
2339 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 5
2340 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10
2341 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 4
2342 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08
2343 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 3
2344 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04
2345 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 2
2346 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02
2347 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 1
2348 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01
2349 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0
2351 /* Bit definitions for USB_ID_INT_SRC */
2352 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10
2353 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 4
2354 #define PALMAS_USB_ID_INT_SRC_ID_A 0x08
2355 #define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 3
2356 #define PALMAS_USB_ID_INT_SRC_ID_B 0x04
2357 #define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 2
2358 #define PALMAS_USB_ID_INT_SRC_ID_C 0x02
2359 #define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 1
2360 #define PALMAS_USB_ID_INT_SRC_ID_GND 0x01
2361 #define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0
2363 /* Bit definitions for USB_ID_INT_LATCH_SET */
2364 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10
2365 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 4
2366 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08
2367 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 3
2368 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04
2369 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 2
2370 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02
2371 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 1
2372 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01
2373 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0
2375 /* Bit definitions for USB_ID_INT_LATCH_CLR */
2376 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10
2377 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 4
2378 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08
2379 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 3
2380 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04
2381 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 2
2382 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02
2383 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 1
2384 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01
2385 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0
2387 /* Bit definitions for USB_ID_INT_EN_LO_SET */
2388 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10
2389 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 4
2390 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08
2391 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 3
2392 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04
2393 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 2
2394 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02
2395 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 1
2396 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01
2397 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0
2399 /* Bit definitions for USB_ID_INT_EN_LO_CLR */
2400 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10
2401 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 4
2402 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08
2403 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 3
2404 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04
2405 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 2
2406 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02
2407 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 1
2408 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01
2409 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0
2411 /* Bit definitions for USB_ID_INT_EN_HI_SET */
2412 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10
2413 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 4
2414 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08
2415 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 3
2416 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04
2417 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 2
2418 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02
2419 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 1
2420 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01
2421 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0
2423 /* Bit definitions for USB_ID_INT_EN_HI_CLR */
2424 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10
2425 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 4
2426 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08
2427 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 3
2428 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04
2429 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 2
2430 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02
2431 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 1
2432 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01
2433 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0
2435 /* Bit definitions for USB_OTG_ADP_CTRL */
2436 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04
2437 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 2
2438 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03
2439 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0
2441 /* Bit definitions for USB_OTG_ADP_HIGH */
2442 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xff
2443 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0
2445 /* Bit definitions for USB_OTG_ADP_LOW */
2446 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xff
2447 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0
2449 /* Bit definitions for USB_OTG_ADP_RISE */
2450 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xff
2451 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0
2453 /* Bit definitions for USB_OTG_REVISION */
2454 #define PALMAS_USB_OTG_REVISION_OTG_REV 0x01
2455 #define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0
2457 /* Registers for function VIBRATOR */
2458 #define PALMAS_VIBRA_CTRL 0x0
2460 /* Bit definitions for VIBRA_CTRL */
2461 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06
2462 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 1
2463 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01
2464 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0
2466 /* Registers for function GPIO */
2467 #define PALMAS_GPIO_DATA_IN 0x0
2468 #define PALMAS_GPIO_DATA_DIR 0x1
2469 #define PALMAS_GPIO_DATA_OUT 0x2
2470 #define PALMAS_GPIO_DEBOUNCE_EN 0x3
2471 #define PALMAS_GPIO_CLEAR_DATA_OUT 0x4
2472 #define PALMAS_GPIO_SET_DATA_OUT 0x5
2473 #define PALMAS_PU_PD_GPIO_CTRL1 0x6
2474 #define PALMAS_PU_PD_GPIO_CTRL2 0x7
2475 #define PALMAS_OD_OUTPUT_GPIO_CTRL 0x8
2477 /* Bit definitions for GPIO_DATA_IN */
2478 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80
2479 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 7
2480 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40
2481 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 6
2482 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20
2483 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 5
2484 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10
2485 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 4
2486 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08
2487 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 3
2488 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04
2489 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 2
2490 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02
2491 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 1
2492 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01
2493 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0
2495 /* Bit definitions for GPIO_DATA_DIR */
2496 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80
2497 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 7
2498 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40
2499 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 6
2500 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20
2501 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 5
2502 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10
2503 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 4
2504 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08
2505 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 3
2506 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04
2507 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 2
2508 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02
2509 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 1
2510 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01
2511 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0
2513 /* Bit definitions for GPIO_DATA_OUT */
2514 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80
2515 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 7
2516 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40
2517 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 6
2518 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20
2519 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 5
2520 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10
2521 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 4
2522 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08
2523 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 3
2524 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04
2525 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 2
2526 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02
2527 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 1
2528 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01
2529 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0
2531 /* Bit definitions for GPIO_DEBOUNCE_EN */
2532 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80
2533 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 7
2534 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40
2535 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 6
2536 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20
2537 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 5
2538 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10
2539 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 4
2540 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08
2541 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 3
2542 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04
2543 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 2
2544 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02
2545 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 1
2546 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01
2547 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0
2549 /* Bit definitions for GPIO_CLEAR_DATA_OUT */
2550 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80
2551 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 7
2552 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40
2553 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 6
2554 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20
2555 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 5
2556 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10
2557 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 4
2558 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08
2559 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 3
2560 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04
2561 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 2
2562 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02
2563 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 1
2564 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01
2565 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0
2567 /* Bit definitions for GPIO_SET_DATA_OUT */
2568 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80
2569 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 7
2570 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40
2571 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 6
2572 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20
2573 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 5
2574 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10
2575 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 4
2576 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08
2577 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 3
2578 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04
2579 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 2
2580 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02
2581 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 1
2582 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01
2583 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0
2585 /* Bit definitions for PU_PD_GPIO_CTRL1 */
2586 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40
2587 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 6
2588 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20
2589 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 5
2590 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10
2591 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 4
2592 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08
2593 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 3
2594 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04
2595 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 2
2596 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01
2597 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0
2599 /* Bit definitions for PU_PD_GPIO_CTRL2 */
2600 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40
2601 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 6
2602 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20
2603 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 5
2604 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10
2605 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 4
2606 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08
2607 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 3
2608 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04
2609 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 2
2610 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02
2611 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 1
2612 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01
2613 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0
2615 /* Bit definitions for OD_OUTPUT_GPIO_CTRL */
2616 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20
2617 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 5
2618 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04
2619 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 2
2620 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02
2621 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 1
2623 /* Registers for function GPADC */
2624 #define PALMAS_GPADC_CTRL1 0x0
2625 #define PALMAS_GPADC_CTRL2 0x1
2626 #define PALMAS_GPADC_RT_CTRL 0x2
2627 #define PALMAS_GPADC_AUTO_CTRL 0x3
2628 #define PALMAS_GPADC_STATUS 0x4
2629 #define PALMAS_GPADC_RT_SELECT 0x5
2630 #define PALMAS_GPADC_RT_CONV0_LSB 0x6
2631 #define PALMAS_GPADC_RT_CONV0_MSB 0x7
2632 #define PALMAS_GPADC_AUTO_SELECT 0x8
2633 #define PALMAS_GPADC_AUTO_CONV0_LSB 0x9
2634 #define PALMAS_GPADC_AUTO_CONV0_MSB 0xA
2635 #define PALMAS_GPADC_AUTO_CONV1_LSB 0xB
2636 #define PALMAS_GPADC_AUTO_CONV1_MSB 0xC
2637 #define PALMAS_GPADC_SW_SELECT 0xD
2638 #define PALMAS_GPADC_SW_CONV0_LSB 0xE
2639 #define PALMAS_GPADC_SW_CONV0_MSB 0xF
2640 #define PALMAS_GPADC_THRES_CONV0_LSB 0x10
2641 #define PALMAS_GPADC_THRES_CONV0_MSB 0x11
2642 #define PALMAS_GPADC_THRES_CONV1_LSB 0x12
2643 #define PALMAS_GPADC_THRES_CONV1_MSB 0x13
2644 #define PALMAS_GPADC_SMPS_ILMONITOR_EN 0x14
2645 #define PALMAS_GPADC_SMPS_VSEL_MONITORING 0x15
2647 /* Bit definitions for GPADC_CTRL1 */
2648 #define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0
2649 #define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 6
2650 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30
2651 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 4
2652 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c
2653 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 2
2654 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02
2655 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 1
2656 #define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01
2657 #define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0
2659 /* Bit definitions for GPADC_CTRL2 */
2660 #define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06
2661 #define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 1
2663 /* Bit definitions for GPADC_RT_CTRL */
2664 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02
2665 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 1
2666 #define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01
2667 #define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0
2669 /* Bit definitions for GPADC_AUTO_CTRL */
2670 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80
2671 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 7
2672 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40
2673 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 6
2674 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20
2675 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 5
2676 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10
2677 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 4
2678 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0f
2679 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0
2681 /* Bit definitions for GPADC_STATUS */
2682 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10
2683 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 4
2685 /* Bit definitions for GPADC_RT_SELECT */
2686 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80
2687 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 7
2688 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0f
2689 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0
2691 /* Bit definitions for GPADC_RT_CONV0_LSB */
2692 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xff
2693 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0
2695 /* Bit definitions for GPADC_RT_CONV0_MSB */
2696 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0f
2697 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0
2699 /* Bit definitions for GPADC_AUTO_SELECT */
2700 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xf0
2701 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 4
2702 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0f
2703 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0
2705 /* Bit definitions for GPADC_AUTO_CONV0_LSB */
2706 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xff
2707 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0
2709 /* Bit definitions for GPADC_AUTO_CONV0_MSB */
2710 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0f
2711 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0
2713 /* Bit definitions for GPADC_AUTO_CONV1_LSB */
2714 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xff
2715 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0
2717 /* Bit definitions for GPADC_AUTO_CONV1_MSB */
2718 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0f
2719 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0
2721 /* Bit definitions for GPADC_SW_SELECT */
2722 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80
2723 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 7
2724 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10
2725 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 4
2726 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0f
2727 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0
2729 /* Bit definitions for GPADC_SW_CONV0_LSB */
2730 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xff
2731 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0
2733 /* Bit definitions for GPADC_SW_CONV0_MSB */
2734 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0f
2735 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0
2737 /* Bit definitions for GPADC_THRES_CONV0_LSB */
2738 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xff
2739 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0
2741 /* Bit definitions for GPADC_THRES_CONV0_MSB */
2742 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80
2743 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 7
2744 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0f
2745 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0
2747 /* Bit definitions for GPADC_THRES_CONV1_LSB */
2748 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xff
2749 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0
2751 /* Bit definitions for GPADC_THRES_CONV1_MSB */
2752 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80
2753 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 7
2754 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0f
2755 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0
2757 /* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
2758 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20
2759 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 5
2760 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10
2761 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 4
2762 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0f
2763 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0
2765 /* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
2766 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80
2767 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 7
2768 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7f
2769 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0
2771 /* Registers for function GPADC */
2772 #define PALMAS_GPADC_TRIM1 0x0
2773 #define PALMAS_GPADC_TRIM2 0x1
2774 #define PALMAS_GPADC_TRIM3 0x2
2775 #define PALMAS_GPADC_TRIM4 0x3
2776 #define PALMAS_GPADC_TRIM5 0x4
2777 #define PALMAS_GPADC_TRIM6 0x5
2778 #define PALMAS_GPADC_TRIM7 0x6
2779 #define PALMAS_GPADC_TRIM8 0x7
2780 #define PALMAS_GPADC_TRIM9 0x8
2781 #define PALMAS_GPADC_TRIM10 0x9
2782 #define PALMAS_GPADC_TRIM11 0xA
2783 #define PALMAS_GPADC_TRIM12 0xB
2784 #define PALMAS_GPADC_TRIM13 0xC
2785 #define PALMAS_GPADC_TRIM14 0xD
2786 #define PALMAS_GPADC_TRIM15 0xE
2787 #define PALMAS_GPADC_TRIM16 0xF
2789 static inline int palmas_read(struct palmas *palmas, unsigned int base,
2790 unsigned int reg, unsigned int *val)
2792 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2793 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2795 return regmap_read(palmas->regmap[slave_id], addr, val);
2798 static inline int palmas_write(struct palmas *palmas, unsigned int base,
2799 unsigned int reg, unsigned int value)
2801 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2802 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2804 return regmap_write(palmas->regmap[slave_id], addr, value);
2807 static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base,
2808 unsigned int reg, const void *val, size_t val_count)
2810 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2811 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2813 return regmap_bulk_write(palmas->regmap[slave_id], addr,
2817 static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base,
2818 unsigned int reg, void *val, size_t val_count)
2820 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2821 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2823 return regmap_bulk_read(palmas->regmap[slave_id], addr,
2827 static inline int palmas_update_bits(struct palmas *palmas, unsigned int base,
2828 unsigned int reg, unsigned int mask, unsigned int val)
2830 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2831 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2833 return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val);
2836 static inline int palmas_irq_get_virq(struct palmas *palmas, int irq)
2838 return regmap_irq_get_virq(palmas->irq_data, irq);
2841 #endif /* __LINUX_MFD_PALMAS_H */