2 * Common variables for the Maxim MAX77843 driver
4 * Copyright (C) 2015 Samsung Electronics
5 * Author: Jaewon Kim <jaewon02.kim@samsung.com>
6 * Author: Beomho Seo <beomho.seo@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #ifndef __MAX77843_PRIVATE_H_
15 #define __MAX77843_PRIVATE_H_
17 #include <linux/i2c.h>
18 #include <linux/regmap.h>
20 #define I2C_ADDR_TOPSYS (0xCC >> 1)
21 #define I2C_ADDR_CHG (0xD2 >> 1)
22 #define I2C_ADDR_FG (0x6C >> 1)
23 #define I2C_ADDR_MUIC (0x4A >> 1)
25 /* Topsys, Haptic and LED registers */
26 enum max77843_sys_reg {
27 MAX77843_SYS_REG_PMICID = 0x00,
28 MAX77843_SYS_REG_PMICREV = 0x01,
29 MAX77843_SYS_REG_MAINCTRL1 = 0x02,
30 MAX77843_SYS_REG_INTSRC = 0x22,
31 MAX77843_SYS_REG_INTSRCMASK = 0x23,
32 MAX77843_SYS_REG_SYSINTSRC = 0x24,
33 MAX77843_SYS_REG_SYSINTMASK = 0x26,
34 MAX77843_SYS_REG_TOPSYS_STAT = 0x28,
35 MAX77843_SYS_REG_SAFEOUTCTRL = 0xC6,
40 enum max77843_haptic_reg {
41 MAX77843_HAP_REG_MCONFIG = 0x10,
46 enum max77843_led_reg {
47 MAX77843_LED_REG_LEDEN = 0x30,
48 MAX77843_LED_REG_LED0BRT = 0x31,
49 MAX77843_LED_REG_LED1BRT = 0x32,
50 MAX77843_LED_REG_LED2BRT = 0x33,
51 MAX77843_LED_REG_LED3BRT = 0x34,
52 MAX77843_LED_REG_LEDBLNK = 0x38,
53 MAX77843_LED_REG_LEDRAMP = 0x36,
58 /* Charger registers */
59 enum max77843_charger_reg {
60 MAX77843_CHG_REG_CHG_INT = 0xB0,
61 MAX77843_CHG_REG_CHG_INT_MASK = 0xB1,
62 MAX77843_CHG_REG_CHG_INT_OK = 0xB2,
63 MAX77843_CHG_REG_CHG_DTLS_00 = 0xB3,
64 MAX77843_CHG_REG_CHG_DTLS_01 = 0xB4,
65 MAX77843_CHG_REG_CHG_DTLS_02 = 0xB5,
66 MAX77843_CHG_REG_CHG_CNFG_00 = 0xB7,
67 MAX77843_CHG_REG_CHG_CNFG_01 = 0xB8,
68 MAX77843_CHG_REG_CHG_CNFG_02 = 0xB9,
69 MAX77843_CHG_REG_CHG_CNFG_03 = 0xBA,
70 MAX77843_CHG_REG_CHG_CNFG_04 = 0xBB,
71 MAX77843_CHG_REG_CHG_CNFG_06 = 0xBD,
72 MAX77843_CHG_REG_CHG_CNFG_07 = 0xBE,
73 MAX77843_CHG_REG_CHG_CNFG_09 = 0xC0,
74 MAX77843_CHG_REG_CHG_CNFG_10 = 0xC1,
75 MAX77843_CHG_REG_CHG_CNFG_11 = 0xC2,
76 MAX77843_CHG_REG_CHG_CNFG_12 = 0xC3,
81 /* Fuel gauge registers */
82 enum max77843_fuelgauge {
83 MAX77843_FG_REG_STATUS = 0x00,
84 MAX77843_FG_REG_VALRT_TH = 0x01,
85 MAX77843_FG_REG_TALRT_TH = 0x02,
86 MAX77843_FG_REG_SALRT_TH = 0x03,
87 MAX77843_FG_RATE_AT_RATE = 0x04,
88 MAX77843_FG_REG_REMCAP_REP = 0x05,
89 MAX77843_FG_REG_SOCREP = 0x06,
90 MAX77843_FG_REG_AGE = 0x07,
91 MAX77843_FG_REG_TEMP = 0x08,
92 MAX77843_FG_REG_VCELL = 0x09,
93 MAX77843_FG_REG_CURRENT = 0x0A,
94 MAX77843_FG_REG_AVG_CURRENT = 0x0B,
95 MAX77843_FG_REG_SOCMIX = 0x0D,
96 MAX77843_FG_REG_SOCAV = 0x0E,
97 MAX77843_FG_REG_REMCAP_MIX = 0x0F,
98 MAX77843_FG_REG_FULLCAP = 0x10,
99 MAX77843_FG_REG_AVG_TEMP = 0x16,
100 MAX77843_FG_REG_CYCLES = 0x17,
101 MAX77843_FG_REG_AVG_VCELL = 0x19,
102 MAX77843_FG_REG_CONFIG = 0x1D,
103 MAX77843_FG_REG_REMCAP_AV = 0x1F,
104 MAX77843_FG_REG_FULLCAP_NOM = 0x23,
105 MAX77843_FG_REG_MISCCFG = 0x2B,
106 MAX77843_FG_REG_RCOMP = 0x38,
107 MAX77843_FG_REG_FSTAT = 0x3D,
108 MAX77843_FG_REG_DQACC = 0x45,
109 MAX77843_FG_REG_DPACC = 0x46,
110 MAX77843_FG_REG_OCV = 0xEE,
111 MAX77843_FG_REG_VFOCV = 0xFB,
112 MAX77843_FG_SOCVF = 0xFF,
118 enum max77843_muic_reg {
119 MAX77843_MUIC_REG_ID = 0x00,
120 MAX77843_MUIC_REG_INT1 = 0x01,
121 MAX77843_MUIC_REG_INT2 = 0x02,
122 MAX77843_MUIC_REG_INT3 = 0x03,
123 MAX77843_MUIC_REG_STATUS1 = 0x04,
124 MAX77843_MUIC_REG_STATUS2 = 0x05,
125 MAX77843_MUIC_REG_STATUS3 = 0x06,
126 MAX77843_MUIC_REG_INTMASK1 = 0x07,
127 MAX77843_MUIC_REG_INTMASK2 = 0x08,
128 MAX77843_MUIC_REG_INTMASK3 = 0x09,
129 MAX77843_MUIC_REG_CDETCTRL1 = 0x0A,
130 MAX77843_MUIC_REG_CDETCTRL2 = 0x0B,
131 MAX77843_MUIC_REG_CONTROL1 = 0x0C,
132 MAX77843_MUIC_REG_CONTROL2 = 0x0D,
133 MAX77843_MUIC_REG_CONTROL3 = 0x0E,
134 MAX77843_MUIC_REG_CONTROL4 = 0x16,
135 MAX77843_MUIC_REG_HVCONTROL1 = 0x17,
136 MAX77843_MUIC_REG_HVCONTROL2 = 0x18,
138 MAX77843_MUIC_REG_END,
143 MAX77843_SYS_IRQ_SYSINTSRC_SYSUVLO_INT,
144 MAX77843_SYS_IRQ_SYSINTSRC_SYSOVLO_INT,
145 MAX77843_SYS_IRQ_SYSINTSRC_TSHDN_INT,
146 MAX77843_SYS_IRQ_SYSINTSRC_TM_INT,
148 /* Charger: CHG_INT */
149 MAX77843_CHG_IRQ_CHG_INT_BYP_I,
150 MAX77843_CHG_IRQ_CHG_INT_BATP_I,
151 MAX77843_CHG_IRQ_CHG_INT_BAT_I,
152 MAX77843_CHG_IRQ_CHG_INT_CHG_I,
153 MAX77843_CHG_IRQ_CHG_INT_WCIN_I,
154 MAX77843_CHG_IRQ_CHG_INT_CHGIN_I,
155 MAX77843_CHG_IRQ_CHG_INT_AICL_I,
160 enum max77843_irq_muic {
162 MAX77843_MUIC_IRQ_INT1_ADC,
163 MAX77843_MUIC_IRQ_INT1_ADCERROR,
164 MAX77843_MUIC_IRQ_INT1_ADC1K,
167 MAX77843_MUIC_IRQ_INT2_CHGTYP,
168 MAX77843_MUIC_IRQ_INT2_CHGDETRUN,
169 MAX77843_MUIC_IRQ_INT2_DCDTMR,
170 MAX77843_MUIC_IRQ_INT2_DXOVP,
171 MAX77843_MUIC_IRQ_INT2_VBVOLT,
174 MAX77843_MUIC_IRQ_INT3_VBADC,
175 MAX77843_MUIC_IRQ_INT3_VDNMON,
176 MAX77843_MUIC_IRQ_INT3_DNRES,
177 MAX77843_MUIC_IRQ_INT3_MPNACK,
178 MAX77843_MUIC_IRQ_INT3_MRXBUFOW,
179 MAX77843_MUIC_IRQ_INT3_MRXTRF,
180 MAX77843_MUIC_IRQ_INT3_MRXPERR,
181 MAX77843_MUIC_IRQ_INT3_MRXRDY,
183 MAX77843_MUIC_IRQ_NUM,
186 /* MAX77843 interrupts */
187 #define MAX77843_SYS_IRQ_SYSUVLO_INT BIT(0)
188 #define MAX77843_SYS_IRQ_SYSOVLO_INT BIT(1)
189 #define MAX77843_SYS_IRQ_TSHDN_INT BIT(2)
190 #define MAX77843_SYS_IRQ_TM_INT BIT(3)
192 /* MAX77843 MAINCTRL1 register */
193 #define MAINCTRL1_BIASEN_SHIFT 7
194 #define MAX77843_MAINCTRL1_BIASEN_MASK BIT(MAINCTRL1_BIASEN_SHIFT)
196 /* MAX77843 MCONFIG register */
197 #define MCONFIG_MODE_SHIFT 7
198 #define MCONFIG_MEN_SHIFT 6
199 #define MCONFIG_PDIV_SHIFT 0
201 #define MAX77843_MCONFIG_MODE_MASK BIT(MCONFIG_MODE_SHIFT)
202 #define MAX77843_MCONFIG_MEN_MASK BIT(MCONFIG_MEN_SHIFT)
203 #define MAX77843_MCONFIG_PDIV_MASK (0x3 << MCONFIG_PDIV_SHIFT)
205 #define LED0EN_SHIFT 0
206 #define LED1EN_SHIFT 2
207 #define LED2EN_SHIFT 4
208 #define LED3EN_SHIFT 6
210 #define MAX77843_LED_LED0EN_MASK (0x3 << LED0EN_SHIFT)
211 #define MAX77843_LED_LED1EN_MASK (0x3 << LED1EN_SHIFT)
212 #define MAX77843_LED_LED2EN_MASK (0x3 << LED2EN_SHIFT)
213 #define MAX77843_LED_LED3EN_MASK (0x3 << LED3EN_SHIFT)
219 #define MAX77843_LED_LED0EN_CONSTANT (CONSTANT << LED0EN_SHIFT)
220 #define MAX77843_LED_LED1EN_CONSTANT (CONSTANT << LED1EN_SHIFT)
221 #define MAX77843_LED_LED2EN_CONSTANT (CONSTANT << LED2EN_SHIFT)
222 #define MAX77843_LED_LED3EN_CONSTANT (CONSTANT << LED3EN_SHIFT)
224 /* MAX77843 LEDBLNK register */
225 #define LEDTON1_SHIFT 4
226 #define LEDTOFF1_SHIFT 0
228 #define MAX77843_LEDBLNK_LEDTON1_MASK (0xF << LEDTON1_SHIFT)
229 #define MAX77843_LEDBLNK_LEDTOFF1_MASK (0xF << LEDTOFF1_SHIFT)
231 /* MAX77843 LEDRAMP register */
232 #define RMPUP1_SHIFT 4
233 #define RMPDN1_SHIFT 0
235 #define MAX77843_LEDRAMP_RAMPUP1_MASK (0xF << RMPUP1_SHIFT)
236 #define MAX77843_LEDRAMP_RAMPDN1_MASK (0xF << RMPDN1_SHIFT)
238 /* Max77843 charger insterrupts */
239 #define MAX77843_CHG_BYP_I BIT(0)
240 #define MAX77843_CHG_BATP_I BIT(2)
241 #define MAX77843_CHG_BAT_I BIT(3)
242 #define MAX77843_CHG_CHG_I BIT(4)
243 #define MAX77843_CHG_WCIN_I BIT(5)
244 #define MAX77843_CHG_CHGIN_I BIT(6)
245 #define MAX77843_CHG_AICL_I BIT(7)
247 /* MAX77843 CHG_INT_OK register */
248 #define MAX77843_CHG_BYP_OK BIT(0)
249 #define MAX77843_CHG_BATP_OK BIT(2)
250 #define MAX77843_CHG_BAT_OK BIT(3)
251 #define MAX77843_CHG_CHG_OK BIT(4)
252 #define MAX77843_CHG_WCIN_OK BIT(5)
253 #define MAX77843_CHG_CHGIN_OK BIT(6)
254 #define MAX77843_CHG_AICL_OK BIT(7)
256 /* MAX77843 CHG_DETAILS_00 register */
257 #define MAX77843_CHG_BAT_DTLS BIT(0)
259 /* MAX77843 CHG_DETAILS_01 register */
260 #define MAX77843_CHG_DTLS_MASK 0x0f
261 #define MAX77843_CHG_PQ_MODE 0x00
262 #define MAX77843_CHG_CC_MODE 0x01
263 #define MAX77843_CHG_CV_MODE 0x02
264 #define MAX77843_CHG_TO_MODE 0x03
265 #define MAX77843_CHG_DO_MODE 0x04
266 #define MAX77843_CHG_HT_MODE 0x05
267 #define MAX77843_CHG_TF_MODE 0x06
268 #define MAX77843_CHG_TS_MODE 0x07
269 #define MAX77843_CHG_OFF_MODE 0x08
271 #define MAX77843_CHG_BAT_DTLS_MASK 0xf0
272 #define MAX77843_CHG_NO_BAT (0x00 << 4)
273 #define MAX77843_CHG_LOW_VOLT_BAT (0x01 << 4)
274 #define MAX77843_CHG_LONG_BAT_TIME (0x02 << 4)
275 #define MAX77843_CHG_OK_BAT (0x03 << 4)
276 #define MAX77843_CHG_OK_LOW_VOLT_BAT (0x04 << 4)
277 #define MAX77843_CHG_OVER_VOLT_BAT (0x05 << 4)
278 #define MAX77843_CHG_OVER_CURRENT_BAT (0x06 << 4)
280 /* MAX77843 CHG_CNFG_00 register */
281 #define MAX77843_CHG_MODE_MASK 0x0f
282 #define MAX77843_CHG_DISABLE 0x00
283 #define MAX77843_CHG_ENABLE 0x05
284 #define MAX77843_CHG_MASK 0x01
285 #define MAX77843_CHG_OTG_MASK 0x02
286 #define MAX77843_CHG_BUCK_MASK 0x04
287 #define MAX77843_CHG_BOOST_MASK 0x08
289 /* MAX77843 CHG_CNFG_01 register */
290 #define MAX77843_CHG_RESTART_THRESHOLD_100 0x00
291 #define MAX77843_CHG_RESTART_THRESHOLD_150 0x10
292 #define MAX77843_CHG_RESTART_THRESHOLD_200 0x20
293 #define MAX77843_CHG_RESTART_THRESHOLD_DISABLE 0x30
295 /* MAX77843 CHG_CNFG_02 register */
296 #define MAX77843_CHG_FAST_CHG_CURRENT_MIN 100000
297 #define MAX77843_CHG_FAST_CHG_CURRENT_MAX 3150000
298 #define MAX77843_CHG_FAST_CHG_CURRENT_STEP 50000
299 #define MAX77843_CHG_FAST_CHG_CURRENT_MASK 0x3f
300 #define MAX77843_CHG_OTG_ILIMIT_500 (0x00 << 6)
301 #define MAX77843_CHG_OTG_ILIMIT_900 (0x01 << 6)
302 #define MAX77843_CHG_OTG_ILIMIT_1200 (0x02 << 6)
303 #define MAX77843_CHG_OTG_ILIMIT_1500 (0x03 << 6)
304 #define MAX77843_CHG_OTG_ILIMIT_MASK 0xc0
306 /* MAX77843 CHG_CNFG_03 register */
307 #define MAX77843_CHG_TOP_OFF_CURRENT_MIN 125000
308 #define MAX77843_CHG_TOP_OFF_CURRENT_MAX 650000
309 #define MAX77843_CHG_TOP_OFF_CURRENT_STEP 75000
310 #define MAX77843_CHG_TOP_OFF_CURRENT_MASK 0x07
312 /* MAX77843 CHG_CNFG_06 register */
313 #define MAX77843_CHG_WRITE_CAP_BLOCK 0x10
314 #define MAX77843_CHG_WRITE_CAP_UNBLOCK 0x0C
316 /* MAX77843_CHG_CNFG_09_register */
317 #define MAX77843_CHG_INPUT_CURRENT_LIMIT_MIN 100000
318 #define MAX77843_CHG_INPUT_CURRENT_LIMIT_MAX 4000000
319 #define MAX77843_CHG_INPUT_CURRENT_LIMIT_REF 3367000
320 #define MAX77843_CHG_INPUT_CURRENT_LIMIT_STEP 33000
322 #define MAX77843_MUIC_ADC BIT(0)
323 #define MAX77843_MUIC_ADCERROR BIT(2)
324 #define MAX77843_MUIC_ADC1K BIT(3)
326 #define MAX77843_MUIC_CHGTYP BIT(0)
327 #define MAX77843_MUIC_CHGDETRUN BIT(1)
328 #define MAX77843_MUIC_DCDTMR BIT(2)
329 #define MAX77843_MUIC_DXOVP BIT(3)
330 #define MAX77843_MUIC_VBVOLT BIT(4)
332 #define MAX77843_MUIC_VBADC BIT(0)
333 #define MAX77843_MUIC_VDNMON BIT(1)
334 #define MAX77843_MUIC_DNRES BIT(2)
335 #define MAX77843_MUIC_MPNACK BIT(3)
336 #define MAX77843_MUIC_MRXBUFOW BIT(4)
337 #define MAX77843_MUIC_MRXTRF BIT(5)
338 #define MAX77843_MUIC_MRXPERR BIT(6)
339 #define MAX77843_MUIC_MRXRDY BIT(7)
341 /* MAX77843 INTSRCMASK register */
342 #define MAX77843_INTSRCMASK_CHGR 0
343 #define MAX77843_INTSRCMASK_SYS 1
344 #define MAX77843_INTSRCMASK_FG 2
345 #define MAX77843_INTSRCMASK_MUIC 3
347 #define MAX77843_INTSRCMASK_CHGR_MASK BIT(MAX77843_INTSRCMASK_CHGR)
348 #define MAX77843_INTSRCMASK_SYS_MASK BIT(MAX77843_INTSRCMASK_SYS)
349 #define MAX77843_INTSRCMASK_FG_MASK BIT(MAX77843_INTSRCMASK_FG)
350 #define MAX77843_INTSRCMASK_MUIC_MASK BIT(MAX77843_INTSRCMASK_MUIC)
352 #define MAX77843_INTSRC_MASK_MASK \
353 (MAX77843_INTSRCMASK_MUIC_MASK | MAX77843_INTSRCMASK_FG_MASK | \
354 MAX77843_INTSRCMASK_SYS_MASK | MAX77843_INTSRCMASK_CHGR_MASK)
356 /* MAX77843 STATUS register*/
357 #define MAX77843_MUIC_STATUS1_ADC_SHIFT 0
358 #define MAX77843_MUIC_STATUS1_ADCERROR_SHIFT 6
359 #define MAX77843_MUIC_STATUS1_ADC1K_SHIFT 7
360 #define MAX77843_MUIC_STATUS2_CHGTYP_SHIFT 0
361 #define MAX77843_MUIC_STATUS2_CHGDETRUN_SHIFT 3
362 #define MAX77843_MUIC_STATUS2_DCDTMR_SHIFT 4
363 #define MAX77843_MUIC_STATUS2_DXOVP_SHIFT 5
364 #define MAX77843_MUIC_STATUS2_VBVOLT_SHIFT 6
365 #define MAX77843_MUIC_STATUS3_VBADC_SHIFT 0
366 #define MAX77843_MUIC_STATUS3_VDNMON_SHIFT 4
367 #define MAX77843_MUIC_STATUS3_DNRES_SHIFT 5
368 #define MAX77843_MUIC_STATUS3_MPNACK_SHIFT 6
370 #define MAX77843_MUIC_STATUS1_ADC_MASK (0x1f << MAX77843_MUIC_STATUS1_ADC_SHIFT)
371 #define MAX77843_MUIC_STATUS1_ADCERROR_MASK BIT(MAX77843_MUIC_STATUS1_ADCERROR_SHIFT)
372 #define MAX77843_MUIC_STATUS1_ADC1K_MASK BIT(MAX77843_MUIC_STATUS1_ADC1K_SHIFT)
373 #define MAX77843_MUIC_STATUS2_CHGTYP_MASK (0x7 << MAX77843_MUIC_STATUS2_CHGTYP_SHIFT)
374 #define MAX77843_MUIC_STATUS2_CHGDETRUN_MASK BIT(MAX77843_MUIC_STATUS2_CHGDETRUN_SHIFT)
375 #define MAX77843_MUIC_STATUS2_DCDTMR_MASK BIT(MAX77843_MUIC_STATUS2_DCDTMR_SHIFT)
376 #define MAX77843_MUIC_STATUS2_DXOVP_MASK BIT(MAX77843_MUIC_STATUS2_DXOVP_SHIFT)
377 #define MAX77843_MUIC_STATUS2_VBVOLT_MASK BIT(MAX77843_MUIC_STATUS2_VBVOLT_SHIFT)
378 #define MAX77843_MUIC_STATUS3_VBADC_MASK (0xf << MAX77843_MUIC_STATUS3_VBADC_SHIFT)
379 #define MAX77843_MUIC_STATUS3_VDNMON_MASK BIT(MAX77843_MUIC_STATUS3_VDNMON_SHIFT)
380 #define MAX77843_MUIC_STATUS3_DNRES_MASK BIT(MAX77843_MUIC_STATUS3_DNRES_SHIFT)
381 #define MAX77843_MUIC_STATUS3_MPNACK_MASK BIT(MAX77843_MUIC_STATUS3_MPNACK_SHIFT)
383 /* MAX77843 CONTROL register */
384 #define MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT 0
385 #define MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT 3
386 #define MAX77843_MUIC_CONTROL1_NOBCCOMP_SHIFT 6
387 #define MAX77843_MUIC_CONTROL1_IDBEN_SHIFT 7
388 #define MAX77843_MUIC_CONTROL2_LOWPWR_SHIFT 0
389 #define MAX77843_MUIC_CONTROL2_ADCEN_SHIFT 1
390 #define MAX77843_MUIC_CONTROL2_CPEN_SHIFT 2
391 #define MAX77843_MUIC_CONTROL2_ACC_DET_SHIFT 5
392 #define MAX77843_MUIC_CONTROL2_USBCPINT_SHIFT 6
393 #define MAX77843_MUIC_CONTROL2_RCPS_SHIFT 7
394 #define MAX77843_MUIC_CONTROL3_JIGSET_SHIFT 0
395 #define MAX77843_MUIC_CONTROL4_ADCDBSET_SHIFT 0
396 #define MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT 4
397 #define MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT 5
398 #define MAX77843_MUIC_CONTROL4_ADCMODE_SHIFT 6
400 #define MAX77843_MUIC_CONTROL1_COMP1SW_MASK (0x7 << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT)
401 #define MAX77843_MUIC_CONTROL1_COMP2SW_MASK (0x7 << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT)
402 #define MAX77843_MUIC_CONTROL1_IDBEN_MASK BIT(MAX77843_MUIC_CONTROL1_IDBEN_SHIFT)
403 #define MAX77843_MUIC_CONTROL1_NOBCCOMP_MASK BIT(MAX77843_MUIC_CONTROL1_NOBCCOMP_SHIFT)
404 #define MAX77843_MUIC_CONTROL2_LOWPWR_MASK BIT(MAX77843_MUIC_CONTROL2_LOWPWR_SHIFT)
405 #define MAX77843_MUIC_CONTROL2_ADCEN_MASK BIT(MAX77843_MUIC_CONTROL2_ADCEN_SHIFT)
406 #define MAX77843_MUIC_CONTROL2_CPEN_MASK BIT(MAX77843_MUIC_CONTROL2_CPEN_SHIFT)
407 #define MAX77843_MUIC_CONTROL2_ACC_DET_MASK BIT(MAX77843_MUIC_CONTROL2_ACC_DET_SHIFT)
408 #define MAX77843_MUIC_CONTROL2_USBCPINT_MASK BIT(MAX77843_MUIC_CONTROL2_USBCPINT_SHIFT)
409 #define MAX77843_MUIC_CONTROL2_RCPS_MASK BIT(MAX77843_MUIC_CONTROL2_RCPS_SHIFT)
410 #define MAX77843_MUIC_CONTROL3_JIGSET_MASK (0x3 << MAX77843_MUIC_CONTROL3_JIGSET_SHIFT)
411 #define MAX77843_MUIC_CONTROL4_ADCDBSET_MASK (0x3 << MAX77843_MUIC_CONTROL4_ADCDBSET_SHIFT)
412 #define MAX77843_MUIC_CONTROL4_USBAUTO_MASK BIT(MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT)
413 #define MAX77843_MUIC_CONTROL4_FCTAUTO_MASK BIT(MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT)
414 #define MAX77843_MUIC_CONTROL4_ADCMODE_MASK (0x3 << MAX77843_MUIC_CONTROL4_ADCMODE_SHIFT)
416 /* MAX77843 switch port */
421 #define COM_AUX_USB 4
422 #define COM_AUX_UART 5
424 #define MAX77843_MUIC_CONTROL1_COM_SW \
425 ((MAX77843_MUIC_CONTROL1_COMP1SW_MASK | \
426 MAX77843_MUIC_CONTROL1_COMP2SW_MASK))
428 #define MAX77843_MUIC_CONTROL1_SW_OPEN \
429 ((COM_OPEN << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \
430 COM_OPEN << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
431 #define MAX77843_MUIC_CONTROL1_SW_USB \
432 ((COM_USB << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \
433 COM_USB << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
434 #define MAX77843_MUIC_CONTROL1_SW_AUDIO \
435 ((COM_AUDIO << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \
436 COM_AUDIO << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
437 #define MAX77843_MUIC_CONTROL1_SW_UART \
438 ((COM_UART << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \
439 COM_UART << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
440 #define MAX77843_MUIC_CONTROL1_SW_AUX_USB \
441 ((COM_AUX_USB << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \
442 COM_AUX_USB << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
443 #define MAX77843_MUIC_CONTROL1_SW_AUX_UART \
444 ((COM_AUX_UART << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \
445 COM_AUX_UART << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
447 #define MAX77843_DISABLE 0
448 #define MAX77843_ENABLE 1
450 #define CONTROL4_AUTO_DISABLE \
451 ((MAX77843_DISABLE << MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT) | \
452 (MAX77843_DISABLE << MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT))
453 #define CONTROL4_AUTO_ENABLE \
454 ((MAX77843_ENABLE << MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT) | \
455 (MAX77843_ENABLE << MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT))
457 /* MAX77843 SAFEOUT LDO Control register */
458 #define SAFEOUTCTRL_SAFEOUT1_SHIFT 0
459 #define SAFEOUTCTRL_SAFEOUT2_SHIFT 2
460 #define SAFEOUTCTRL_ENSAFEOUT1_SHIFT 6
461 #define SAFEOUTCTRL_ENSAFEOUT2_SHIFT 7
463 #define MAX77843_REG_SAFEOUTCTRL_ENSAFEOUT1 \
464 BIT(SAFEOUTCTRL_ENSAFEOUT1_SHIFT)
465 #define MAX77843_REG_SAFEOUTCTRL_ENSAFEOUT2 \
466 BIT(SAFEOUTCTRL_ENSAFEOUT2_SHIFT)
467 #define MAX77843_REG_SAFEOUTCTRL_SAFEOUT1_MASK \
468 (0x3 << SAFEOUTCTRL_SAFEOUT1_SHIFT)
469 #define MAX77843_REG_SAFEOUTCTRL_SAFEOUT2_MASK \
470 (0x3 << SAFEOUTCTRL_SAFEOUT2_SHIFT)
472 #endif /* __MAX77843_H__ */