2 * Marvell MBUS common definitions.
4 * Copyright (C) 2008 Marvell Semiconductor
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #ifndef __LINUX_MBUS_H
12 #define __LINUX_MBUS_H
16 struct mbus_dram_target_info {
18 * The 4-bit MBUS target ID of the DRAM controller.
20 u8 mbus_dram_target_id;
23 * The base address, size, and MBUS attribute ID for each
24 * of the possible DRAM chip selects. Peripherals are
25 * required to support at least 4 decode windows.
28 struct mbus_dram_window {
36 struct mvebu_mbus_state {
37 void __iomem *mbuswins_base;
38 void __iomem *sdramwins_base;
39 struct dentry *debugfs_root;
40 struct dentry *debugfs_sdram;
41 struct dentry *debugfs_devs;
42 const struct mvebu_mbus_soc_data *soc;
46 /* Flags for PCI/PCIe address decoding regions */
47 #define MVEBU_MBUS_PCI_IO 0x1
48 #define MVEBU_MBUS_PCI_MEM 0x2
49 #define MVEBU_MBUS_PCI_WA 0x3
52 * Magic value that explicits that we don't need a remapping-capable
53 * address decoding window.
55 #define MVEBU_MBUS_NO_REMAP (0xffffffff)
57 /* Maximum size of a mbus window name */
58 #define MVEBU_MBUS_MAX_WINNAME_SZ 32
60 const struct mbus_dram_target_info *mvebu_mbus_dram_info(void);
61 void mvebu_mbus_get_pcie_mem_aperture(struct resource *res);
62 void mvebu_mbus_get_pcie_io_aperture(struct resource *res);
63 int mvebu_mbus_add_window_remap_by_id(unsigned int target,
64 unsigned int attribute,
65 phys_addr_t base, size_t size,
67 int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
68 phys_addr_t base, size_t size);
69 int mvebu_mbus_del_window(phys_addr_t base, size_t size);
70 int mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
71 u32 base, u32 size, u8 target, u8 attr);
73 #endif /* __LINUX_MBUS_H */