include/linux/firmware/xlnx-zynqmp.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Xilinx Zynq MPSoC Firmware layer
   4  *
   5  *  Copyright (C) 2014-2021 Xilinx
   6  *
   7  *  Michal Simek <michal.simek@xilinx.com>
   8  *  Davorin Mista <davorin.mista@aggios.com>
   9  *  Jolly Shah <jollys@xilinx.com>
  10  *  Rajan Vaja <rajanv@xilinx.com>
  11  */
  12
  13 #ifndef __FIRMWARE_ZYNQMP_H__
  14 #define __FIRMWARE_ZYNQMP_H__
  15
  16 #include <linux/err.h>
  17
  18 #define ZYNQMP_PM_VERSION_MAJOR 1
  19 #define ZYNQMP_PM_VERSION_MINOR 0
  20
  21 #define ZYNQMP_PM_VERSION       ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
  22                                         ZYNQMP_PM_VERSION_MINOR)
  23
  24 #define ZYNQMP_TZ_VERSION_MAJOR 1
  25 #define ZYNQMP_TZ_VERSION_MINOR 0
  26
  27 #define ZYNQMP_TZ_VERSION       ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
  28                                         ZYNQMP_TZ_VERSION_MINOR)
  29
  30 /* SMC SIP service Call Function Identifier Prefix */
  31 #define PM_SIP_SVC                      0xC2000000
  32
  33 /* PM API versions */
  34 #define PM_API_VERSION_2        2
  35
  36 /* ATF only commands */
  37 #define TF_A_PM_REGISTER_SGI            0xa04
  38 #define PM_GET_TRUSTZONE_VERSION        0xa03
  39 #define PM_SET_SUSPEND_MODE             0xa02
  40 #define GET_CALLBACK_DATA               0xa01
  41
  42 /* Number of 32bits values in payload */
  43 #define PAYLOAD_ARG_CNT 4U
  44
  45 /* Number of arguments for a callback */
  46 #define CB_ARG_CNT     4
  47
  48 /* Payload size (consists of callback API ID + arguments) */
  49 #define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
  50
  51 #define ZYNQMP_PM_MAX_QOS               100U
  52
  53 #define GSS_NUM_REGS    (4)
  54
  55 /* Node capabilities */
  56 #define ZYNQMP_PM_CAPABILITY_ACCESS     0x1U
  57 #define ZYNQMP_PM_CAPABILITY_CONTEXT    0x2U
  58 #define ZYNQMP_PM_CAPABILITY_WAKEUP     0x4U
  59 #define ZYNQMP_PM_CAPABILITY_UNUSABLE   0x8U
  60
  61 /* Loader commands */
  62 #define PM_LOAD_PDI     0x701
  63 #define PDI_SRC_DDR     0xF
  64
  65 /*
  66  * Firmware FPGA Manager flags
  67  * XILINX_ZYNQMP_PM_FPGA_FULL:  FPGA full reconfiguration
  68  * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
  69  */
  70 #define XILINX_ZYNQMP_PM_FPGA_FULL      0x0U
  71 #define XILINX_ZYNQMP_PM_FPGA_PARTIAL   BIT(0)
  72
  73 /*
  74  * Node IDs for the Error Events.
  75  */
  76 #define EVENT_ERROR_PMC_ERR1    (0x28100000U)
  77 #define EVENT_ERROR_PMC_ERR2    (0x28104000U)
  78 #define EVENT_ERROR_PSM_ERR1    (0x28108000U)
  79 #define EVENT_ERROR_PSM_ERR2    (0x2810C000U)
  80
  81 enum pm_api_cb_id {
  82         PM_INIT_SUSPEND_CB = 30,
  83         PM_ACKNOWLEDGE_CB = 31,
  84         PM_NOTIFY_CB = 32,
  85 };
  86
  87 enum pm_api_id {
  88         PM_GET_API_VERSION = 1,
  89         PM_REGISTER_NOTIFIER = 5,
  90         PM_SYSTEM_SHUTDOWN = 12,
  91         PM_REQUEST_NODE = 13,
  92         PM_RELEASE_NODE = 14,
  93         PM_SET_REQUIREMENT = 15,
  94         PM_RESET_ASSERT = 17,
  95         PM_RESET_GET_STATUS = 18,
  96         PM_MMIO_WRITE = 19,
  97         PM_MMIO_READ = 20,
  98         PM_PM_INIT_FINALIZE = 21,
  99         PM_FPGA_LOAD = 22,
 100         PM_FPGA_GET_STATUS = 23,
 101         PM_GET_CHIPID = 24,
 102         PM_SECURE_SHA = 26,
 103         PM_PINCTRL_REQUEST = 28,
 104         PM_PINCTRL_RELEASE = 29,
 105         PM_PINCTRL_GET_FUNCTION = 30,
 106         PM_PINCTRL_SET_FUNCTION = 31,
 107         PM_PINCTRL_CONFIG_PARAM_GET = 32,
 108         PM_PINCTRL_CONFIG_PARAM_SET = 33,
 109         PM_IOCTL = 34,
 110         PM_QUERY_DATA = 35,
 111         PM_CLOCK_ENABLE = 36,
 112         PM_CLOCK_DISABLE = 37,
 113         PM_CLOCK_GETSTATE = 38,
 114         PM_CLOCK_SETDIVIDER = 39,
 115         PM_CLOCK_GETDIVIDER = 40,
 116         PM_CLOCK_SETRATE = 41,
 117         PM_CLOCK_GETRATE = 42,
 118         PM_CLOCK_SETPARENT = 43,
 119         PM_CLOCK_GETPARENT = 44,
 120         PM_SECURE_AES = 47,
 121         PM_FEATURE_CHECK = 63,
 122 };
 123
 124 /* PMU-FW return status codes */
 125 enum pm_ret_status {
 126         XST_PM_SUCCESS = 0,
 127         XST_PM_NO_FEATURE = 19,
 128         XST_PM_INTERNAL = 2000,
 129         XST_PM_CONFLICT = 2001,
 130         XST_PM_NO_ACCESS = 2002,
 131         XST_PM_INVALID_NODE = 2003,
 132         XST_PM_DOUBLE_REQ = 2004,
 133         XST_PM_ABORT_SUSPEND = 2005,
 134         XST_PM_MULT_USER = 2008,
 135 };
 136
 137 enum pm_ioctl_id {
 138         IOCTL_SET_TAPDELAY_BYPASS = 4,
 139         IOCTL_SD_DLL_RESET = 6,
 140         IOCTL_SET_SD_TAPDELAY = 7,
 141         IOCTL_SET_PLL_FRAC_MODE = 8,
 142         IOCTL_GET_PLL_FRAC_MODE = 9,
 143         IOCTL_SET_PLL_FRAC_DATA = 10,
 144         IOCTL_GET_PLL_FRAC_DATA = 11,
 145         IOCTL_WRITE_GGS = 12,
 146         IOCTL_READ_GGS = 13,
 147         IOCTL_WRITE_PGGS = 14,
 148         IOCTL_READ_PGGS = 15,
 149         /* Set healthy bit value */
 150         IOCTL_SET_BOOT_HEALTH_STATUS = 17,
 151         IOCTL_OSPI_MUX_SELECT = 21,
 152         /* Register SGI to ATF */
 153         IOCTL_REGISTER_SGI = 25,
 154         /* Runtime feature configuration */
 155         IOCTL_SET_FEATURE_CONFIG = 26,
 156         IOCTL_GET_FEATURE_CONFIG = 27,
 157         /* Dynamic SD/GEM configuration */
 158         IOCTL_SET_SD_CONFIG = 30,
 159         IOCTL_SET_GEM_CONFIG = 31,
 160 };
 161
 162 enum pm_query_id {
 163         PM_QID_INVALID = 0,
 164         PM_QID_CLOCK_GET_NAME = 1,
 165         PM_QID_CLOCK_GET_TOPOLOGY = 2,
 166         PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
 167         PM_QID_CLOCK_GET_PARENTS = 4,
 168         PM_QID_CLOCK_GET_ATTRIBUTES = 5,
 169         PM_QID_PINCTRL_GET_NUM_PINS = 6,
 170         PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7,
 171         PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8,
 172         PM_QID_PINCTRL_GET_FUNCTION_NAME = 9,
 173         PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10,
 174         PM_QID_PINCTRL_GET_PIN_GROUPS = 11,
 175         PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
 176         PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
 177 };
 178
 179 enum zynqmp_pm_reset_action {
 180         PM_RESET_ACTION_RELEASE = 0,
 181         PM_RESET_ACTION_ASSERT = 1,
 182         PM_RESET_ACTION_PULSE = 2,
 183 };
 184
 185 enum zynqmp_pm_reset {
 186         ZYNQMP_PM_RESET_START = 1000,
 187         ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
 188         ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001,
 189         ZYNQMP_PM_RESET_PCIE_CTRL = 1002,
 190         ZYNQMP_PM_RESET_DP = 1003,
 191         ZYNQMP_PM_RESET_SWDT_CRF = 1004,
 192         ZYNQMP_PM_RESET_AFI_FM5 = 1005,
 193         ZYNQMP_PM_RESET_AFI_FM4 = 1006,
 194         ZYNQMP_PM_RESET_AFI_FM3 = 1007,
 195         ZYNQMP_PM_RESET_AFI_FM2 = 1008,
 196         ZYNQMP_PM_RESET_AFI_FM1 = 1009,
 197         ZYNQMP_PM_RESET_AFI_FM0 = 1010,
 198         ZYNQMP_PM_RESET_GDMA = 1011,
 199         ZYNQMP_PM_RESET_GPU_PP1 = 1012,
 200         ZYNQMP_PM_RESET_GPU_PP0 = 1013,
 201         ZYNQMP_PM_RESET_GPU = 1014,
 202         ZYNQMP_PM_RESET_GT = 1015,
 203         ZYNQMP_PM_RESET_SATA = 1016,
 204         ZYNQMP_PM_RESET_ACPU3_PWRON = 1017,
 205         ZYNQMP_PM_RESET_ACPU2_PWRON = 1018,
 206         ZYNQMP_PM_RESET_ACPU1_PWRON = 1019,
 207         ZYNQMP_PM_RESET_ACPU0_PWRON = 1020,
 208         ZYNQMP_PM_RESET_APU_L2 = 1021,
 209         ZYNQMP_PM_RESET_ACPU3 = 1022,
 210         ZYNQMP_PM_RESET_ACPU2 = 1023,
 211         ZYNQMP_PM_RESET_ACPU1 = 1024,
 212         ZYNQMP_PM_RESET_ACPU0 = 1025,
 213         ZYNQMP_PM_RESET_DDR = 1026,
 214         ZYNQMP_PM_RESET_APM_FPD = 1027,
 215         ZYNQMP_PM_RESET_SOFT = 1028,
 216         ZYNQMP_PM_RESET_GEM0 = 1029,
 217         ZYNQMP_PM_RESET_GEM1 = 1030,
 218         ZYNQMP_PM_RESET_GEM2 = 1031,
 219         ZYNQMP_PM_RESET_GEM3 = 1032,
 220         ZYNQMP_PM_RESET_QSPI = 1033,
 221         ZYNQMP_PM_RESET_UART0 = 1034,
 222         ZYNQMP_PM_RESET_UART1 = 1035,
 223         ZYNQMP_PM_RESET_SPI0 = 1036,
 224         ZYNQMP_PM_RESET_SPI1 = 1037,
 225         ZYNQMP_PM_RESET_SDIO0 = 1038,
 226         ZYNQMP_PM_RESET_SDIO1 = 1039,
 227         ZYNQMP_PM_RESET_CAN0 = 1040,
 228         ZYNQMP_PM_RESET_CAN1 = 1041,
 229         ZYNQMP_PM_RESET_I2C0 = 1042,
 230         ZYNQMP_PM_RESET_I2C1 = 1043,
 231         ZYNQMP_PM_RESET_TTC0 = 1044,
 232         ZYNQMP_PM_RESET_TTC1 = 1045,
 233         ZYNQMP_PM_RESET_TTC2 = 1046,
 234         ZYNQMP_PM_RESET_TTC3 = 1047,
 235         ZYNQMP_PM_RESET_SWDT_CRL = 1048,
 236         ZYNQMP_PM_RESET_NAND = 1049,
 237         ZYNQMP_PM_RESET_ADMA = 1050,
 238         ZYNQMP_PM_RESET_GPIO = 1051,
 239         ZYNQMP_PM_RESET_IOU_CC = 1052,
 240         ZYNQMP_PM_RESET_TIMESTAMP = 1053,
 241         ZYNQMP_PM_RESET_RPU_R50 = 1054,
 242         ZYNQMP_PM_RESET_RPU_R51 = 1055,
 243         ZYNQMP_PM_RESET_RPU_AMBA = 1056,
 244         ZYNQMP_PM_RESET_OCM = 1057,
 245         ZYNQMP_PM_RESET_RPU_PGE = 1058,
 246         ZYNQMP_PM_RESET_USB0_CORERESET = 1059,
 247         ZYNQMP_PM_RESET_USB1_CORERESET = 1060,
 248         ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061,
 249         ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062,
 250         ZYNQMP_PM_RESET_USB0_APB = 1063,
 251         ZYNQMP_PM_RESET_USB1_APB = 1064,
 252         ZYNQMP_PM_RESET_IPI = 1065,
 253         ZYNQMP_PM_RESET_APM_LPD = 1066,
 254         ZYNQMP_PM_RESET_RTC = 1067,
 255         ZYNQMP_PM_RESET_SYSMON = 1068,
 256         ZYNQMP_PM_RESET_AFI_FM6 = 1069,
 257         ZYNQMP_PM_RESET_LPD_SWDT = 1070,
 258         ZYNQMP_PM_RESET_FPD = 1071,
 259         ZYNQMP_PM_RESET_RPU_DBG1 = 1072,
 260         ZYNQMP_PM_RESET_RPU_DBG0 = 1073,
 261         ZYNQMP_PM_RESET_DBG_LPD = 1074,
 262         ZYNQMP_PM_RESET_DBG_FPD = 1075,
 263         ZYNQMP_PM_RESET_APLL = 1076,
 264         ZYNQMP_PM_RESET_DPLL = 1077,
 265         ZYNQMP_PM_RESET_VPLL = 1078,
 266         ZYNQMP_PM_RESET_IOPLL = 1079,
 267         ZYNQMP_PM_RESET_RPLL = 1080,
 268         ZYNQMP_PM_RESET_GPO3_PL_0 = 1081,
 269         ZYNQMP_PM_RESET_GPO3_PL_1 = 1082,
 270         ZYNQMP_PM_RESET_GPO3_PL_2 = 1083,
 271         ZYNQMP_PM_RESET_GPO3_PL_3 = 1084,
 272         ZYNQMP_PM_RESET_GPO3_PL_4 = 1085,
 273         ZYNQMP_PM_RESET_GPO3_PL_5 = 1086,
 274         ZYNQMP_PM_RESET_GPO3_PL_6 = 1087,
 275         ZYNQMP_PM_RESET_GPO3_PL_7 = 1088,
 276         ZYNQMP_PM_RESET_GPO3_PL_8 = 1089,
 277         ZYNQMP_PM_RESET_GPO3_PL_9 = 1090,
 278         ZYNQMP_PM_RESET_GPO3_PL_10 = 1091,
 279         ZYNQMP_PM_RESET_GPO3_PL_11 = 1092,
 280         ZYNQMP_PM_RESET_GPO3_PL_12 = 1093,
 281         ZYNQMP_PM_RESET_GPO3_PL_13 = 1094,
 282         ZYNQMP_PM_RESET_GPO3_PL_14 = 1095,
 283         ZYNQMP_PM_RESET_GPO3_PL_15 = 1096,
 284         ZYNQMP_PM_RESET_GPO3_PL_16 = 1097,
 285         ZYNQMP_PM_RESET_GPO3_PL_17 = 1098,
 286         ZYNQMP_PM_RESET_GPO3_PL_18 = 1099,
 287         ZYNQMP_PM_RESET_GPO3_PL_19 = 1100,
 288         ZYNQMP_PM_RESET_GPO3_PL_20 = 1101,
 289         ZYNQMP_PM_RESET_GPO3_PL_21 = 1102,
 290         ZYNQMP_PM_RESET_GPO3_PL_22 = 1103,
 291         ZYNQMP_PM_RESET_GPO3_PL_23 = 1104,
 292         ZYNQMP_PM_RESET_GPO3_PL_24 = 1105,
 293         ZYNQMP_PM_RESET_GPO3_PL_25 = 1106,
 294         ZYNQMP_PM_RESET_GPO3_PL_26 = 1107,
 295         ZYNQMP_PM_RESET_GPO3_PL_27 = 1108,
 296         ZYNQMP_PM_RESET_GPO3_PL_28 = 1109,
 297         ZYNQMP_PM_RESET_GPO3_PL_29 = 1110,
 298         ZYNQMP_PM_RESET_GPO3_PL_30 = 1111,
 299         ZYNQMP_PM_RESET_GPO3_PL_31 = 1112,
 300         ZYNQMP_PM_RESET_RPU_LS = 1113,
 301         ZYNQMP_PM_RESET_PS_ONLY = 1114,
 302         ZYNQMP_PM_RESET_PL = 1115,
 303         ZYNQMP_PM_RESET_PS_PL0 = 1116,
 304         ZYNQMP_PM_RESET_PS_PL1 = 1117,
 305         ZYNQMP_PM_RESET_PS_PL2 = 1118,
 306         ZYNQMP_PM_RESET_PS_PL3 = 1119,
 307         ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
 308 };
 309
 310 enum zynqmp_pm_suspend_reason {
 311         SUSPEND_POWER_REQUEST = 201,
 312         SUSPEND_ALERT = 202,
 313         SUSPEND_SYSTEM_SHUTDOWN = 203,
 314 };
 315
 316 enum zynqmp_pm_request_ack {
 317         ZYNQMP_PM_REQUEST_ACK_NO = 1,
 318         ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2,
 319         ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3,
 320 };
 321
 322 enum pm_node_id {
 323         NODE_SD_0 = 39,
 324         NODE_SD_1 = 40,
 325 };
 326
 327 enum tap_delay_type {
 328         PM_TAPDELAY_INPUT = 0,
 329         PM_TAPDELAY_OUTPUT = 1,
 330 };
 331
 332 enum dll_reset_type {
 333         PM_DLL_RESET_ASSERT = 0,
 334         PM_DLL_RESET_RELEASE = 1,
 335         PM_DLL_RESET_PULSE = 2,
 336 };
 337
 338 enum pm_pinctrl_config_param {
 339         PM_PINCTRL_CONFIG_SLEW_RATE = 0,
 340         PM_PINCTRL_CONFIG_BIAS_STATUS = 1,
 341         PM_PINCTRL_CONFIG_PULL_CTRL = 2,
 342         PM_PINCTRL_CONFIG_SCHMITT_CMOS = 3,
 343         PM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4,
 344         PM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5,
 345         PM_PINCTRL_CONFIG_TRI_STATE = 6,
 346         PM_PINCTRL_CONFIG_MAX = 7,
 347 };
 348
 349 enum pm_pinctrl_slew_rate {
 350         PM_PINCTRL_SLEW_RATE_FAST = 0,
 351         PM_PINCTRL_SLEW_RATE_SLOW = 1,
 352 };
 353
 354 enum pm_pinctrl_bias_status {
 355         PM_PINCTRL_BIAS_DISABLE = 0,
 356         PM_PINCTRL_BIAS_ENABLE = 1,
 357 };
 358
 359 enum pm_pinctrl_pull_ctrl {
 360         PM_PINCTRL_BIAS_PULL_DOWN = 0,
 361         PM_PINCTRL_BIAS_PULL_UP = 1,
 362 };
 363
 364 enum pm_pinctrl_schmitt_cmos {
 365         PM_PINCTRL_INPUT_TYPE_CMOS = 0,
 366         PM_PINCTRL_INPUT_TYPE_SCHMITT = 1,
 367 };
 368
 369 enum pm_pinctrl_drive_strength {
 370         PM_PINCTRL_DRIVE_STRENGTH_2MA = 0,
 371         PM_PINCTRL_DRIVE_STRENGTH_4MA = 1,
 372         PM_PINCTRL_DRIVE_STRENGTH_8MA = 2,
 373         PM_PINCTRL_DRIVE_STRENGTH_12MA = 3,
 374 };
 375
 376 enum pm_pinctrl_tri_state {
 377         PM_PINCTRL_TRI_STATE_DISABLE = 0,
 378         PM_PINCTRL_TRI_STATE_ENABLE = 1,
 379 };
 380
 381 enum zynqmp_pm_shutdown_type {
 382         ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0,
 383         ZYNQMP_PM_SHUTDOWN_TYPE_RESET = 1,
 384         ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY = 2,
 385 };
 386
 387 enum zynqmp_pm_shutdown_subtype {
 388         ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM = 0,
 389         ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY = 1,
 390         ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2,
 391 };
 392
 393 enum tap_delay_signal_type {
 394         PM_TAPDELAY_NAND_DQS_IN = 0,
 395         PM_TAPDELAY_NAND_DQS_OUT = 1,
 396         PM_TAPDELAY_QSPI = 2,
 397         PM_TAPDELAY_MAX = 3,
 398 };
 399
 400 enum tap_delay_bypass_ctrl {
 401         PM_TAPDELAY_BYPASS_DISABLE = 0,
 402         PM_TAPDELAY_BYPASS_ENABLE = 1,
 403 };
 404
 405 enum ospi_mux_select_type {
 406         PM_OSPI_MUX_SEL_DMA = 0,
 407         PM_OSPI_MUX_SEL_LINEAR = 1,
 408 };
 409
 410 enum pm_feature_config_id {
 411         PM_FEATURE_INVALID = 0,
 412         PM_FEATURE_OVERTEMP_STATUS = 1,
 413         PM_FEATURE_OVERTEMP_VALUE = 2,
 414         PM_FEATURE_EXTWDT_STATUS = 3,
 415         PM_FEATURE_EXTWDT_VALUE = 4,
 416 };
 417
 418 /**
 419  * enum pm_sd_config_type - PM SD configuration.
 420  * @SD_CONFIG_EMMC_SEL: To set SD_EMMC_SEL in CTRL_REG_SD and SD_SLOTTYPE
 421  * @SD_CONFIG_BASECLK: To set SD_BASECLK in SD_CONFIG_REG1
 422  * @SD_CONFIG_8BIT: To set SD_8BIT in SD_CONFIG_REG2
 423  * @SD_CONFIG_FIXED: To set fixed config registers
 424  */
 425 enum pm_sd_config_type {
 426         SD_CONFIG_EMMC_SEL = 1,
 427         SD_CONFIG_BASECLK = 2,
 428         SD_CONFIG_8BIT = 3,
 429         SD_CONFIG_FIXED = 4,
 430 };
 431
 432 /**
 433  * enum pm_gem_config_type - PM GEM configuration.
 434  * @GEM_CONFIG_SGMII_MODE: To set GEM_SGMII_MODE in GEM_CLK_CTRL register
 435  * @GEM_CONFIG_FIXED: To set fixed config registers
 436  */
 437 enum pm_gem_config_type {
 438         GEM_CONFIG_SGMII_MODE = 1,
 439         GEM_CONFIG_FIXED = 2,
 440 };
 441
 442 /**
 443  * struct zynqmp_pm_query_data - PM query data
 444  * @qid:        query ID
 445  * @arg1:       Argument 1 of query data
 446  * @arg2:       Argument 2 of query data
 447  * @arg3:       Argument 3 of query data
 448  */
 449 struct zynqmp_pm_query_data {
 450         u32 qid;
 451         u32 arg1;
 452         u32 arg2;
 453         u32 arg3;
 454 };
 455
 456 int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
 457                         u32 arg2, u32 arg3, u32 *ret_payload);
 458
 459 #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
 460 int zynqmp_pm_get_api_version(u32 *version);
 461 int zynqmp_pm_get_chipid(u32 *idcode, u32 *version);
 462 int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out);
 463 int zynqmp_pm_clock_enable(u32 clock_id);
 464 int zynqmp_pm_clock_disable(u32 clock_id);
 465 int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state);
 466 int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider);
 467 int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider);
 468 int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate);
 469 int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate);
 470 int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id);
 471 int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id);
 472 int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode);
 473 int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode);
 474 int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data);
 475 int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data);
 476 int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value);
 477 int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type);
 478 int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select);
 479 int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
 480                            const enum zynqmp_pm_reset_action assert_flag);
 481 int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status);
 482 unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode);
 483 int zynqmp_pm_bootmode_write(u32 ps_mode);
 484 int zynqmp_pm_init_finalize(void);
 485 int zynqmp_pm_set_suspend_mode(u32 mode);
 486 int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
 487                            const u32 qos, const enum zynqmp_pm_request_ack ack);
 488 int zynqmp_pm_release_node(const u32 node);
 489 int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
 490                               const u32 qos,
 491                               const enum zynqmp_pm_request_ack ack);
 492 int zynqmp_pm_aes_engine(const u64 address, u32 *out);
 493 int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags);
 494 int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
 495 int zynqmp_pm_fpga_get_status(u32 *value);
 496 int zynqmp_pm_write_ggs(u32 index, u32 value);
 497 int zynqmp_pm_read_ggs(u32 index, u32 *value);
 498 int zynqmp_pm_write_pggs(u32 index, u32 value);
 499 int zynqmp_pm_read_pggs(u32 index, u32 *value);
 500 int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value);
 501 int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
 502 int zynqmp_pm_set_boot_health_status(u32 value);
 503 int zynqmp_pm_pinctrl_request(const u32 pin);
 504 int zynqmp_pm_pinctrl_release(const u32 pin);
 505 int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id);
 506 int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id);
 507 int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
 508                                  u32 *value);
 509 int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
 510                                  u32 value);
 511 int zynqmp_pm_load_pdi(const u32 src, const u64 address);
 512 int zynqmp_pm_register_notifier(const u32 node, const u32 event,
 513                                 const u32 wake, const u32 enable);
 514 int zynqmp_pm_feature(const u32 api_id);
 515 int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
 516 int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value);
 517 int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload);
 518 int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset);
 519 int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value);
 520 int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config,
 521                              u32 value);
 522 #else
 523 static inline int zynqmp_pm_get_api_version(u32 *version)
 524 {
 525         return -ENODEV;
 526 }
 527
 528 static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
 529 {
 530         return -ENODEV;
 531 }
 532
 533 static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,
 534                                        u32 *out)
 535 {
 536         return -ENODEV;
 537 }
 538
 539 static inline int zynqmp_pm_clock_enable(u32 clock_id)
 540 {
 541         return -ENODEV;
 542 }
 543
 544 static inline int zynqmp_pm_clock_disable(u32 clock_id)
 545 {
 546         return -ENODEV;
 547 }
 548
 549 static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
 550 {
 551         return -ENODEV;
 552 }
 553
 554 static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
 555 {
 556         return -ENODEV;
 557 }
 558
 559 static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
 560 {
 561         return -ENODEV;
 562 }
 563
 564 static inline int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate)
 565 {
 566         return -ENODEV;
 567 }
 568
 569 static inline int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate)
 570 {
 571         return -ENODEV;
 572 }
 573
 574 static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id)
 575 {
 576         return -ENODEV;
 577 }
 578
 579 static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
 580 {
 581         return -ENODEV;
 582 }
 583
 584 static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode)
 585 {
 586         return -ENODEV;
 587 }
 588
 589 static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode)
 590 {
 591         return -ENODEV;
 592 }
 593
 594 static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data)
 595 {
 596         return -ENODEV;
 597 }
 598
 599 static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data)
 600 {
 601         return -ENODEV;
 602 }
 603
 604 static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value)
 605 {
 606         return -ENODEV;
 607 }
 608
 609 static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
 610 {
 611         return -ENODEV;
 612 }
 613
 614 static inline int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select)
 615 {
 616         return -ENODEV;
 617 }
 618
 619 static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
 620                                          const enum zynqmp_pm_reset_action assert_flag)
 621 {
 622         return -ENODEV;
 623 }
 624
 625 static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,
 626                                              u32 *status)
 627 {
 628         return -ENODEV;
 629 }
 630
 631 static inline unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode)
 632 {
 633         return -ENODEV;
 634 }
 635
 636 static inline int zynqmp_pm_bootmode_write(u32 ps_mode)
 637 {
 638         return -ENODEV;
 639 }
 640
 641 static inline int zynqmp_pm_init_finalize(void)
 642 {
 643         return -ENODEV;
 644 }
 645
 646 static inline int zynqmp_pm_set_suspend_mode(u32 mode)
 647 {
 648         return -ENODEV;
 649 }
 650
 651 static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
 652                                          const u32 qos,
 653                                          const enum zynqmp_pm_request_ack ack)
 654 {
 655         return -ENODEV;
 656 }
 657
 658 static inline int zynqmp_pm_release_node(const u32 node)
 659 {
 660         return -ENODEV;
 661 }
 662
 663 static inline int zynqmp_pm_set_requirement(const u32 node,
 664                                             const u32 capabilities,
 665                                             const u32 qos,
 666                                             const enum zynqmp_pm_request_ack ack)
 667 {
 668         return -ENODEV;
 669 }
 670
 671 static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
 672 {
 673         return -ENODEV;
 674 }
 675
 676 static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size,
 677                                      const u32 flags)
 678 {
 679         return -ENODEV;
 680 }
 681
 682 static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
 683                                       const u32 flags)
 684 {
 685         return -ENODEV;
 686 }
 687
 688 static inline int zynqmp_pm_fpga_get_status(u32 *value)
 689 {
 690         return -ENODEV;
 691 }
 692
 693 static inline int zynqmp_pm_write_ggs(u32 index, u32 value)
 694 {
 695         return -ENODEV;
 696 }
 697
 698 static inline int zynqmp_pm_read_ggs(u32 index, u32 *value)
 699 {
 700         return -ENODEV;
 701 }
 702
 703 static inline int zynqmp_pm_write_pggs(u32 index, u32 value)
 704 {
 705         return -ENODEV;
 706 }
 707
 708 static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
 709 {
 710         return -ENODEV;
 711 }
 712
 713 static inline int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value)
 714 {
 715         return -ENODEV;
 716 }
 717
 718 static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
 719 {
 720         return -ENODEV;
 721 }
 722
 723 static inline int zynqmp_pm_set_boot_health_status(u32 value)
 724 {
 725         return -ENODEV;
 726 }
 727
 728 static inline int zynqmp_pm_pinctrl_request(const u32 pin)
 729 {
 730         return -ENODEV;
 731 }
 732
 733 static inline int zynqmp_pm_pinctrl_release(const u32 pin)
 734 {
 735         return -ENODEV;
 736 }
 737
 738 static inline int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id)
 739 {
 740         return -ENODEV;
 741 }
 742
 743 static inline int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
 744 {
 745         return -ENODEV;
 746 }
 747
 748 static inline int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id)
 749 {
 750         return -ENODEV;
 751 }
 752
 753 static inline int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
 754                                                u32 *value)
 755 {
 756         return -ENODEV;
 757 }
 758
 759 static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
 760                                                u32 value)
 761 {
 762         return -ENODEV;
 763 }
 764
 765 static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address)
 766 {
 767         return -ENODEV;
 768 }
 769
 770 static inline int zynqmp_pm_register_notifier(const u32 node, const u32 event,
 771                                               const u32 wake, const u32 enable)
 772 {
 773         return -ENODEV;
 774 }
 775
 776 static inline int zynqmp_pm_feature(const u32 api_id)
 777 {
 778         return -ENODEV;
 779 }
 780
 781 static inline int zynqmp_pm_set_feature_config(enum pm_feature_config_id id,
 782                                                u32 value)
 783 {
 784         return -ENODEV;
 785 }
 786
 787 static inline int zynqmp_pm_get_feature_config(enum pm_feature_config_id id,
 788                                                u32 *payload)
 789 {
 790         return -ENODEV;
 791 }
 792
 793 static inline int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset)
 794 {
 795         return -ENODEV;
 796 }
 797
 798 static inline int zynqmp_pm_set_sd_config(u32 node,
 799                                           enum pm_sd_config_type config,
 800                                           u32 value)
 801 {
 802         return -ENODEV;
 803 }
 804
 805 static inline int zynqmp_pm_set_gem_config(u32 node,
 806                                            enum pm_gem_config_type config,
 807                                            u32 value)
 808 {
 809         return -ENODEV;
 810 }
 811
 812 #endif
 813
 814 #endif /* __FIRMWARE_ZYNQMP_H__ */