include/linux/firmware/xlnx-zynqmp.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Xilinx Zynq MPSoC Firmware layer
   4  *
   5  *  Copyright (C) 2014-2021 Xilinx
   6  *
   7  *  Michal Simek <michal.simek@xilinx.com>
   8  *  Davorin Mista <davorin.mista@aggios.com>
   9  *  Jolly Shah <jollys@xilinx.com>
  10  *  Rajan Vaja <rajanv@xilinx.com>
  11  */
  12
  13 #ifndef __FIRMWARE_ZYNQMP_H__
  14 #define __FIRMWARE_ZYNQMP_H__
  15 #include <linux/types.h>
  16
  17 #include <linux/err.h>
  18
  19 #define ZYNQMP_PM_VERSION_MAJOR 1
  20 #define ZYNQMP_PM_VERSION_MINOR 0
  21
  22 #define ZYNQMP_PM_VERSION       ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
  23                                         ZYNQMP_PM_VERSION_MINOR)
  24
  25 #define ZYNQMP_TZ_VERSION_MAJOR 1
  26 #define ZYNQMP_TZ_VERSION_MINOR 0
  27
  28 #define ZYNQMP_TZ_VERSION       ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
  29                                         ZYNQMP_TZ_VERSION_MINOR)
  30
  31 /* SMC SIP service Call Function Identifier Prefix */
  32 #define PM_SIP_SVC                      0xC2000000
  33
  34 /* PM API versions */
  35 #define PM_API_VERSION_2        2
  36
  37 /* ATF only commands */
  38 #define TF_A_PM_REGISTER_SGI            0xa04
  39 #define PM_GET_TRUSTZONE_VERSION        0xa03
  40 #define PM_SET_SUSPEND_MODE             0xa02
  41 #define GET_CALLBACK_DATA               0xa01
  42
  43 /* Number of 32bits values in payload */
  44 #define PAYLOAD_ARG_CNT 4U
  45
  46 /* Number of arguments for a callback */
  47 #define CB_ARG_CNT     4
  48
  49 /* Payload size (consists of callback API ID + arguments) */
  50 #define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
  51
  52 #define ZYNQMP_PM_MAX_QOS               100U
  53
  54 #define GSS_NUM_REGS    (4)
  55
  56 /* Node capabilities */
  57 #define ZYNQMP_PM_CAPABILITY_ACCESS     0x1U
  58 #define ZYNQMP_PM_CAPABILITY_CONTEXT    0x2U
  59 #define ZYNQMP_PM_CAPABILITY_WAKEUP     0x4U
  60 #define ZYNQMP_PM_CAPABILITY_UNUSABLE   0x8U
  61
  62 /* Loader commands */
  63 #define PM_LOAD_PDI     0x701
  64 #define PDI_SRC_DDR     0xF
  65
  66 /*
  67  * Firmware FPGA Manager flags
  68  * XILINX_ZYNQMP_PM_FPGA_FULL:  FPGA full reconfiguration
  69  * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
  70  */
  71 #define XILINX_ZYNQMP_PM_FPGA_FULL      0x0U
  72 #define XILINX_ZYNQMP_PM_FPGA_PARTIAL   BIT(0)
  73
  74 /*
  75  * Node IDs for the Error Events.
  76  */
  77 #define EVENT_ERROR_PMC_ERR1    (0x28100000U)
  78 #define EVENT_ERROR_PMC_ERR2    (0x28104000U)
  79 #define EVENT_ERROR_PSM_ERR1    (0x28108000U)
  80 #define EVENT_ERROR_PSM_ERR2    (0x2810C000U)
  81
  82 enum pm_api_cb_id {
  83         PM_INIT_SUSPEND_CB = 30,
  84         PM_ACKNOWLEDGE_CB = 31,
  85         PM_NOTIFY_CB = 32,
  86 };
  87
  88 enum pm_api_id {
  89         PM_GET_API_VERSION = 1,
  90         PM_REGISTER_NOTIFIER = 5,
  91         PM_FORCE_POWERDOWN = 8,
  92         PM_REQUEST_WAKEUP = 10,
  93         PM_SYSTEM_SHUTDOWN = 12,
  94         PM_REQUEST_NODE = 13,
  95         PM_RELEASE_NODE = 14,
  96         PM_SET_REQUIREMENT = 15,
  97         PM_RESET_ASSERT = 17,
  98         PM_RESET_GET_STATUS = 18,
  99         PM_MMIO_WRITE = 19,
 100         PM_MMIO_READ = 20,
 101         PM_PM_INIT_FINALIZE = 21,
 102         PM_FPGA_LOAD = 22,
 103         PM_FPGA_GET_STATUS = 23,
 104         PM_GET_CHIPID = 24,
 105         PM_SECURE_SHA = 26,
 106         PM_PINCTRL_REQUEST = 28,
 107         PM_PINCTRL_RELEASE = 29,
 108         PM_PINCTRL_GET_FUNCTION = 30,
 109         PM_PINCTRL_SET_FUNCTION = 31,
 110         PM_PINCTRL_CONFIG_PARAM_GET = 32,
 111         PM_PINCTRL_CONFIG_PARAM_SET = 33,
 112         PM_IOCTL = 34,
 113         PM_QUERY_DATA = 35,
 114         PM_CLOCK_ENABLE = 36,
 115         PM_CLOCK_DISABLE = 37,
 116         PM_CLOCK_GETSTATE = 38,
 117         PM_CLOCK_SETDIVIDER = 39,
 118         PM_CLOCK_GETDIVIDER = 40,
 119         PM_CLOCK_SETRATE = 41,
 120         PM_CLOCK_GETRATE = 42,
 121         PM_CLOCK_SETPARENT = 43,
 122         PM_CLOCK_GETPARENT = 44,
 123         PM_SECURE_AES = 47,
 124         PM_FEATURE_CHECK = 63,
 125 };
 126
 127 /* PMU-FW return status codes */
 128 enum pm_ret_status {
 129         XST_PM_SUCCESS = 0,
 130         XST_PM_NO_FEATURE = 19,
 131         XST_PM_INTERNAL = 2000,
 132         XST_PM_CONFLICT = 2001,
 133         XST_PM_NO_ACCESS = 2002,
 134         XST_PM_INVALID_NODE = 2003,
 135         XST_PM_DOUBLE_REQ = 2004,
 136         XST_PM_ABORT_SUSPEND = 2005,
 137         XST_PM_MULT_USER = 2008,
 138 };
 139
 140 enum pm_ioctl_id {
 141         IOCTL_GET_RPU_OPER_MODE = 0,
 142         IOCTL_SET_RPU_OPER_MODE = 1,
 143         IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
 144         IOCTL_TCM_COMB_CONFIG = 3,
 145         IOCTL_SD_DLL_RESET = 6,
 146         IOCTL_SET_SD_TAPDELAY = 7,
 147         IOCTL_SET_PLL_FRAC_MODE = 8,
 148         IOCTL_GET_PLL_FRAC_MODE = 9,
 149         IOCTL_SET_PLL_FRAC_DATA = 10,
 150         IOCTL_GET_PLL_FRAC_DATA = 11,
 151         IOCTL_WRITE_GGS = 12,
 152         IOCTL_READ_GGS = 13,
 153         IOCTL_WRITE_PGGS = 14,
 154         IOCTL_READ_PGGS = 15,
 155         /* Set healthy bit value */
 156         IOCTL_SET_BOOT_HEALTH_STATUS = 17,
 157         IOCTL_OSPI_MUX_SELECT = 21,
 158         /* Register SGI to ATF */
 159         IOCTL_REGISTER_SGI = 25,
 160         /* Runtime feature configuration */
 161         IOCTL_SET_FEATURE_CONFIG = 26,
 162         IOCTL_GET_FEATURE_CONFIG = 27,
 163         /* Dynamic SD/GEM configuration */
 164         IOCTL_SET_SD_CONFIG = 30,
 165         IOCTL_SET_GEM_CONFIG = 31,
 166 };
 167
 168 enum pm_query_id {
 169         PM_QID_INVALID = 0,
 170         PM_QID_CLOCK_GET_NAME = 1,
 171         PM_QID_CLOCK_GET_TOPOLOGY = 2,
 172         PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
 173         PM_QID_CLOCK_GET_PARENTS = 4,
 174         PM_QID_CLOCK_GET_ATTRIBUTES = 5,
 175         PM_QID_PINCTRL_GET_NUM_PINS = 6,
 176         PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7,
 177         PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8,
 178         PM_QID_PINCTRL_GET_FUNCTION_NAME = 9,
 179         PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10,
 180         PM_QID_PINCTRL_GET_PIN_GROUPS = 11,
 181         PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
 182         PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
 183 };
 184
 185 enum rpu_oper_mode {
 186         PM_RPU_MODE_LOCKSTEP = 0,
 187         PM_RPU_MODE_SPLIT = 1,
 188 };
 189
 190 enum rpu_boot_mem {
 191         PM_RPU_BOOTMEM_LOVEC = 0,
 192         PM_RPU_BOOTMEM_HIVEC = 1,
 193 };
 194
 195 enum rpu_tcm_comb {
 196         PM_RPU_TCM_SPLIT = 0,
 197         PM_RPU_TCM_COMB = 1,
 198 };
 199
 200 enum zynqmp_pm_reset_action {
 201         PM_RESET_ACTION_RELEASE = 0,
 202         PM_RESET_ACTION_ASSERT = 1,
 203         PM_RESET_ACTION_PULSE = 2,
 204 };
 205
 206 enum zynqmp_pm_reset {
 207         ZYNQMP_PM_RESET_START = 1000,
 208         ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
 209         ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001,
 210         ZYNQMP_PM_RESET_PCIE_CTRL = 1002,
 211         ZYNQMP_PM_RESET_DP = 1003,
 212         ZYNQMP_PM_RESET_SWDT_CRF = 1004,
 213         ZYNQMP_PM_RESET_AFI_FM5 = 1005,
 214         ZYNQMP_PM_RESET_AFI_FM4 = 1006,
 215         ZYNQMP_PM_RESET_AFI_FM3 = 1007,
 216         ZYNQMP_PM_RESET_AFI_FM2 = 1008,
 217         ZYNQMP_PM_RESET_AFI_FM1 = 1009,
 218         ZYNQMP_PM_RESET_AFI_FM0 = 1010,
 219         ZYNQMP_PM_RESET_GDMA = 1011,
 220         ZYNQMP_PM_RESET_GPU_PP1 = 1012,
 221         ZYNQMP_PM_RESET_GPU_PP0 = 1013,
 222         ZYNQMP_PM_RESET_GPU = 1014,
 223         ZYNQMP_PM_RESET_GT = 1015,
 224         ZYNQMP_PM_RESET_SATA = 1016,
 225         ZYNQMP_PM_RESET_ACPU3_PWRON = 1017,
 226         ZYNQMP_PM_RESET_ACPU2_PWRON = 1018,
 227         ZYNQMP_PM_RESET_ACPU1_PWRON = 1019,
 228         ZYNQMP_PM_RESET_ACPU0_PWRON = 1020,
 229         ZYNQMP_PM_RESET_APU_L2 = 1021,
 230         ZYNQMP_PM_RESET_ACPU3 = 1022,
 231         ZYNQMP_PM_RESET_ACPU2 = 1023,
 232         ZYNQMP_PM_RESET_ACPU1 = 1024,
 233         ZYNQMP_PM_RESET_ACPU0 = 1025,
 234         ZYNQMP_PM_RESET_DDR = 1026,
 235         ZYNQMP_PM_RESET_APM_FPD = 1027,
 236         ZYNQMP_PM_RESET_SOFT = 1028,
 237         ZYNQMP_PM_RESET_GEM0 = 1029,
 238         ZYNQMP_PM_RESET_GEM1 = 1030,
 239         ZYNQMP_PM_RESET_GEM2 = 1031,
 240         ZYNQMP_PM_RESET_GEM3 = 1032,
 241         ZYNQMP_PM_RESET_QSPI = 1033,
 242         ZYNQMP_PM_RESET_UART0 = 1034,
 243         ZYNQMP_PM_RESET_UART1 = 1035,
 244         ZYNQMP_PM_RESET_SPI0 = 1036,
 245         ZYNQMP_PM_RESET_SPI1 = 1037,
 246         ZYNQMP_PM_RESET_SDIO0 = 1038,
 247         ZYNQMP_PM_RESET_SDIO1 = 1039,
 248         ZYNQMP_PM_RESET_CAN0 = 1040,
 249         ZYNQMP_PM_RESET_CAN1 = 1041,
 250         ZYNQMP_PM_RESET_I2C0 = 1042,
 251         ZYNQMP_PM_RESET_I2C1 = 1043,
 252         ZYNQMP_PM_RESET_TTC0 = 1044,
 253         ZYNQMP_PM_RESET_TTC1 = 1045,
 254         ZYNQMP_PM_RESET_TTC2 = 1046,
 255         ZYNQMP_PM_RESET_TTC3 = 1047,
 256         ZYNQMP_PM_RESET_SWDT_CRL = 1048,
 257         ZYNQMP_PM_RESET_NAND = 1049,
 258         ZYNQMP_PM_RESET_ADMA = 1050,
 259         ZYNQMP_PM_RESET_GPIO = 1051,
 260         ZYNQMP_PM_RESET_IOU_CC = 1052,
 261         ZYNQMP_PM_RESET_TIMESTAMP = 1053,
 262         ZYNQMP_PM_RESET_RPU_R50 = 1054,
 263         ZYNQMP_PM_RESET_RPU_R51 = 1055,
 264         ZYNQMP_PM_RESET_RPU_AMBA = 1056,
 265         ZYNQMP_PM_RESET_OCM = 1057,
 266         ZYNQMP_PM_RESET_RPU_PGE = 1058,
 267         ZYNQMP_PM_RESET_USB0_CORERESET = 1059,
 268         ZYNQMP_PM_RESET_USB1_CORERESET = 1060,
 269         ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061,
 270         ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062,
 271         ZYNQMP_PM_RESET_USB0_APB = 1063,
 272         ZYNQMP_PM_RESET_USB1_APB = 1064,
 273         ZYNQMP_PM_RESET_IPI = 1065,
 274         ZYNQMP_PM_RESET_APM_LPD = 1066,
 275         ZYNQMP_PM_RESET_RTC = 1067,
 276         ZYNQMP_PM_RESET_SYSMON = 1068,
 277         ZYNQMP_PM_RESET_AFI_FM6 = 1069,
 278         ZYNQMP_PM_RESET_LPD_SWDT = 1070,
 279         ZYNQMP_PM_RESET_FPD = 1071,
 280         ZYNQMP_PM_RESET_RPU_DBG1 = 1072,
 281         ZYNQMP_PM_RESET_RPU_DBG0 = 1073,
 282         ZYNQMP_PM_RESET_DBG_LPD = 1074,
 283         ZYNQMP_PM_RESET_DBG_FPD = 1075,
 284         ZYNQMP_PM_RESET_APLL = 1076,
 285         ZYNQMP_PM_RESET_DPLL = 1077,
 286         ZYNQMP_PM_RESET_VPLL = 1078,
 287         ZYNQMP_PM_RESET_IOPLL = 1079,
 288         ZYNQMP_PM_RESET_RPLL = 1080,
 289         ZYNQMP_PM_RESET_GPO3_PL_0 = 1081,
 290         ZYNQMP_PM_RESET_GPO3_PL_1 = 1082,
 291         ZYNQMP_PM_RESET_GPO3_PL_2 = 1083,
 292         ZYNQMP_PM_RESET_GPO3_PL_3 = 1084,
 293         ZYNQMP_PM_RESET_GPO3_PL_4 = 1085,
 294         ZYNQMP_PM_RESET_GPO3_PL_5 = 1086,
 295         ZYNQMP_PM_RESET_GPO3_PL_6 = 1087,
 296         ZYNQMP_PM_RESET_GPO3_PL_7 = 1088,
 297         ZYNQMP_PM_RESET_GPO3_PL_8 = 1089,
 298         ZYNQMP_PM_RESET_GPO3_PL_9 = 1090,
 299         ZYNQMP_PM_RESET_GPO3_PL_10 = 1091,
 300         ZYNQMP_PM_RESET_GPO3_PL_11 = 1092,
 301         ZYNQMP_PM_RESET_GPO3_PL_12 = 1093,
 302         ZYNQMP_PM_RESET_GPO3_PL_13 = 1094,
 303         ZYNQMP_PM_RESET_GPO3_PL_14 = 1095,
 304         ZYNQMP_PM_RESET_GPO3_PL_15 = 1096,
 305         ZYNQMP_PM_RESET_GPO3_PL_16 = 1097,
 306         ZYNQMP_PM_RESET_GPO3_PL_17 = 1098,
 307         ZYNQMP_PM_RESET_GPO3_PL_18 = 1099,
 308         ZYNQMP_PM_RESET_GPO3_PL_19 = 1100,
 309         ZYNQMP_PM_RESET_GPO3_PL_20 = 1101,
 310         ZYNQMP_PM_RESET_GPO3_PL_21 = 1102,
 311         ZYNQMP_PM_RESET_GPO3_PL_22 = 1103,
 312         ZYNQMP_PM_RESET_GPO3_PL_23 = 1104,
 313         ZYNQMP_PM_RESET_GPO3_PL_24 = 1105,
 314         ZYNQMP_PM_RESET_GPO3_PL_25 = 1106,
 315         ZYNQMP_PM_RESET_GPO3_PL_26 = 1107,
 316         ZYNQMP_PM_RESET_GPO3_PL_27 = 1108,
 317         ZYNQMP_PM_RESET_GPO3_PL_28 = 1109,
 318         ZYNQMP_PM_RESET_GPO3_PL_29 = 1110,
 319         ZYNQMP_PM_RESET_GPO3_PL_30 = 1111,
 320         ZYNQMP_PM_RESET_GPO3_PL_31 = 1112,
 321         ZYNQMP_PM_RESET_RPU_LS = 1113,
 322         ZYNQMP_PM_RESET_PS_ONLY = 1114,
 323         ZYNQMP_PM_RESET_PL = 1115,
 324         ZYNQMP_PM_RESET_PS_PL0 = 1116,
 325         ZYNQMP_PM_RESET_PS_PL1 = 1117,
 326         ZYNQMP_PM_RESET_PS_PL2 = 1118,
 327         ZYNQMP_PM_RESET_PS_PL3 = 1119,
 328         ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
 329 };
 330
 331 enum zynqmp_pm_suspend_reason {
 332         SUSPEND_POWER_REQUEST = 201,
 333         SUSPEND_ALERT = 202,
 334         SUSPEND_SYSTEM_SHUTDOWN = 203,
 335 };
 336
 337 enum zynqmp_pm_request_ack {
 338         ZYNQMP_PM_REQUEST_ACK_NO = 1,
 339         ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2,
 340         ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3,
 341 };
 342
 343 enum pm_node_id {
 344         NODE_SD_0 = 39,
 345         NODE_SD_1 = 40,
 346 };
 347
 348 enum tap_delay_type {
 349         PM_TAPDELAY_INPUT = 0,
 350         PM_TAPDELAY_OUTPUT = 1,
 351 };
 352
 353 enum dll_reset_type {
 354         PM_DLL_RESET_ASSERT = 0,
 355         PM_DLL_RESET_RELEASE = 1,
 356         PM_DLL_RESET_PULSE = 2,
 357 };
 358
 359 enum pm_pinctrl_config_param {
 360         PM_PINCTRL_CONFIG_SLEW_RATE = 0,
 361         PM_PINCTRL_CONFIG_BIAS_STATUS = 1,
 362         PM_PINCTRL_CONFIG_PULL_CTRL = 2,
 363         PM_PINCTRL_CONFIG_SCHMITT_CMOS = 3,
 364         PM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4,
 365         PM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5,
 366         PM_PINCTRL_CONFIG_TRI_STATE = 6,
 367         PM_PINCTRL_CONFIG_MAX = 7,
 368 };
 369
 370 enum pm_pinctrl_slew_rate {
 371         PM_PINCTRL_SLEW_RATE_FAST = 0,
 372         PM_PINCTRL_SLEW_RATE_SLOW = 1,
 373 };
 374
 375 enum pm_pinctrl_bias_status {
 376         PM_PINCTRL_BIAS_DISABLE = 0,
 377         PM_PINCTRL_BIAS_ENABLE = 1,
 378 };
 379
 380 enum pm_pinctrl_pull_ctrl {
 381         PM_PINCTRL_BIAS_PULL_DOWN = 0,
 382         PM_PINCTRL_BIAS_PULL_UP = 1,
 383 };
 384
 385 enum pm_pinctrl_schmitt_cmos {
 386         PM_PINCTRL_INPUT_TYPE_CMOS = 0,
 387         PM_PINCTRL_INPUT_TYPE_SCHMITT = 1,
 388 };
 389
 390 enum pm_pinctrl_drive_strength {
 391         PM_PINCTRL_DRIVE_STRENGTH_2MA = 0,
 392         PM_PINCTRL_DRIVE_STRENGTH_4MA = 1,
 393         PM_PINCTRL_DRIVE_STRENGTH_8MA = 2,
 394         PM_PINCTRL_DRIVE_STRENGTH_12MA = 3,
 395 };
 396
 397 enum pm_pinctrl_tri_state {
 398         PM_PINCTRL_TRI_STATE_DISABLE = 0,
 399         PM_PINCTRL_TRI_STATE_ENABLE = 1,
 400 };
 401
 402 enum zynqmp_pm_shutdown_type {
 403         ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0,
 404         ZYNQMP_PM_SHUTDOWN_TYPE_RESET = 1,
 405         ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY = 2,
 406 };
 407
 408 enum zynqmp_pm_shutdown_subtype {
 409         ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM = 0,
 410         ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY = 1,
 411         ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2,
 412 };
 413
 414 enum ospi_mux_select_type {
 415         PM_OSPI_MUX_SEL_DMA = 0,
 416         PM_OSPI_MUX_SEL_LINEAR = 1,
 417 };
 418
 419 enum pm_feature_config_id {
 420         PM_FEATURE_INVALID = 0,
 421         PM_FEATURE_OVERTEMP_STATUS = 1,
 422         PM_FEATURE_OVERTEMP_VALUE = 2,
 423         PM_FEATURE_EXTWDT_STATUS = 3,
 424         PM_FEATURE_EXTWDT_VALUE = 4,
 425 };
 426
 427 /**
 428  * enum pm_sd_config_type - PM SD configuration.
 429  * @SD_CONFIG_EMMC_SEL: To set SD_EMMC_SEL in CTRL_REG_SD and SD_SLOTTYPE
 430  * @SD_CONFIG_BASECLK: To set SD_BASECLK in SD_CONFIG_REG1
 431  * @SD_CONFIG_8BIT: To set SD_8BIT in SD_CONFIG_REG2
 432  * @SD_CONFIG_FIXED: To set fixed config registers
 433  */
 434 enum pm_sd_config_type {
 435         SD_CONFIG_EMMC_SEL = 1,
 436         SD_CONFIG_BASECLK = 2,
 437         SD_CONFIG_8BIT = 3,
 438         SD_CONFIG_FIXED = 4,
 439 };
 440
 441 /**
 442  * enum pm_gem_config_type - PM GEM configuration.
 443  * @GEM_CONFIG_SGMII_MODE: To set GEM_SGMII_MODE in GEM_CLK_CTRL register
 444  * @GEM_CONFIG_FIXED: To set fixed config registers
 445  */
 446 enum pm_gem_config_type {
 447         GEM_CONFIG_SGMII_MODE = 1,
 448         GEM_CONFIG_FIXED = 2,
 449 };
 450
 451 /**
 452  * struct zynqmp_pm_query_data - PM query data
 453  * @qid:        query ID
 454  * @arg1:       Argument 1 of query data
 455  * @arg2:       Argument 2 of query data
 456  * @arg3:       Argument 3 of query data
 457  */
 458 struct zynqmp_pm_query_data {
 459         u32 qid;
 460         u32 arg1;
 461         u32 arg2;
 462         u32 arg3;
 463 };
 464
 465 int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
 466                         u32 arg2, u32 arg3, u32 *ret_payload);
 467
 468 #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
 469 int zynqmp_pm_get_api_version(u32 *version);
 470 int zynqmp_pm_get_chipid(u32 *idcode, u32 *version);
 471 int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out);
 472 int zynqmp_pm_clock_enable(u32 clock_id);
 473 int zynqmp_pm_clock_disable(u32 clock_id);
 474 int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state);
 475 int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider);
 476 int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider);
 477 int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate);
 478 int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate);
 479 int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id);
 480 int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id);
 481 int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode);
 482 int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode);
 483 int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data);
 484 int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data);
 485 int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value);
 486 int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type);
 487 int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select);
 488 int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
 489                            const enum zynqmp_pm_reset_action assert_flag);
 490 int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status);
 491 unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode);
 492 int zynqmp_pm_bootmode_write(u32 ps_mode);
 493 int zynqmp_pm_init_finalize(void);
 494 int zynqmp_pm_set_suspend_mode(u32 mode);
 495 int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
 496                            const u32 qos, const enum zynqmp_pm_request_ack ack);
 497 int zynqmp_pm_release_node(const u32 node);
 498 int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
 499                               const u32 qos,
 500                               const enum zynqmp_pm_request_ack ack);
 501 int zynqmp_pm_aes_engine(const u64 address, u32 *out);
 502 int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags);
 503 int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
 504 int zynqmp_pm_fpga_get_status(u32 *value);
 505 int zynqmp_pm_write_ggs(u32 index, u32 value);
 506 int zynqmp_pm_read_ggs(u32 index, u32 *value);
 507 int zynqmp_pm_write_pggs(u32 index, u32 value);
 508 int zynqmp_pm_read_pggs(u32 index, u32 *value);
 509 int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
 510 int zynqmp_pm_set_boot_health_status(u32 value);
 511 int zynqmp_pm_pinctrl_request(const u32 pin);
 512 int zynqmp_pm_pinctrl_release(const u32 pin);
 513 int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id);
 514 int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id);
 515 int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
 516                                  u32 *value);
 517 int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
 518                                  u32 value);
 519 int zynqmp_pm_load_pdi(const u32 src, const u64 address);
 520 int zynqmp_pm_register_notifier(const u32 node, const u32 event,
 521                                 const u32 wake, const u32 enable);
 522 int zynqmp_pm_feature(const u32 api_id);
 523 int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
 524 int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value);
 525 int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload);
 526 int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset);
 527 int zynqmp_pm_force_pwrdwn(const u32 target,
 528                            const enum zynqmp_pm_request_ack ack);
 529 int zynqmp_pm_request_wake(const u32 node,
 530                            const bool set_addr,
 531                            const u64 address,
 532                            const enum zynqmp_pm_request_ack ack);
 533 int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode);
 534 int zynqmp_pm_set_rpu_mode(u32 node_id, u32 arg1);
 535 int zynqmp_pm_set_tcm_config(u32 node_id, u32 arg1);
 536 int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value);
 537 int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config,
 538                              u32 value);
 539 #else
 540 static inline int zynqmp_pm_get_api_version(u32 *version)
 541 {
 542         return -ENODEV;
 543 }
 544
 545 static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
 546 {
 547         return -ENODEV;
 548 }
 549
 550 static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,
 551                                        u32 *out)
 552 {
 553         return -ENODEV;
 554 }
 555
 556 static inline int zynqmp_pm_clock_enable(u32 clock_id)
 557 {
 558         return -ENODEV;
 559 }
 560
 561 static inline int zynqmp_pm_clock_disable(u32 clock_id)
 562 {
 563         return -ENODEV;
 564 }
 565
 566 static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
 567 {
 568         return -ENODEV;
 569 }
 570
 571 static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
 572 {
 573         return -ENODEV;
 574 }
 575
 576 static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
 577 {
 578         return -ENODEV;
 579 }
 580
 581 static inline int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate)
 582 {
 583         return -ENODEV;
 584 }
 585
 586 static inline int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate)
 587 {
 588         return -ENODEV;
 589 }
 590
 591 static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id)
 592 {
 593         return -ENODEV;
 594 }
 595
 596 static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
 597 {
 598         return -ENODEV;
 599 }
 600
 601 static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode)
 602 {
 603         return -ENODEV;
 604 }
 605
 606 static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode)
 607 {
 608         return -ENODEV;
 609 }
 610
 611 static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data)
 612 {
 613         return -ENODEV;
 614 }
 615
 616 static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data)
 617 {
 618         return -ENODEV;
 619 }
 620
 621 static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value)
 622 {
 623         return -ENODEV;
 624 }
 625
 626 static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
 627 {
 628         return -ENODEV;
 629 }
 630
 631 static inline int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select)
 632 {
 633         return -ENODEV;
 634 }
 635
 636 static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
 637                                          const enum zynqmp_pm_reset_action assert_flag)
 638 {
 639         return -ENODEV;
 640 }
 641
 642 static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,
 643                                              u32 *status)
 644 {
 645         return -ENODEV;
 646 }
 647
 648 static inline unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode)
 649 {
 650         return -ENODEV;
 651 }
 652
 653 static inline int zynqmp_pm_bootmode_write(u32 ps_mode)
 654 {
 655         return -ENODEV;
 656 }
 657
 658 static inline int zynqmp_pm_init_finalize(void)
 659 {
 660         return -ENODEV;
 661 }
 662
 663 static inline int zynqmp_pm_set_suspend_mode(u32 mode)
 664 {
 665         return -ENODEV;
 666 }
 667
 668 static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
 669                                          const u32 qos,
 670                                          const enum zynqmp_pm_request_ack ack)
 671 {
 672         return -ENODEV;
 673 }
 674
 675 static inline int zynqmp_pm_release_node(const u32 node)
 676 {
 677         return -ENODEV;
 678 }
 679
 680 static inline int zynqmp_pm_set_requirement(const u32 node,
 681                                             const u32 capabilities,
 682                                             const u32 qos,
 683                                             const enum zynqmp_pm_request_ack ack)
 684 {
 685         return -ENODEV;
 686 }
 687
 688 static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
 689 {
 690         return -ENODEV;
 691 }
 692
 693 static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size,
 694                                      const u32 flags)
 695 {
 696         return -ENODEV;
 697 }
 698
 699 static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
 700                                       const u32 flags)
 701 {
 702         return -ENODEV;
 703 }
 704
 705 static inline int zynqmp_pm_fpga_get_status(u32 *value)
 706 {
 707         return -ENODEV;
 708 }
 709
 710 static inline int zynqmp_pm_write_ggs(u32 index, u32 value)
 711 {
 712         return -ENODEV;
 713 }
 714
 715 static inline int zynqmp_pm_read_ggs(u32 index, u32 *value)
 716 {
 717         return -ENODEV;
 718 }
 719
 720 static inline int zynqmp_pm_write_pggs(u32 index, u32 value)
 721 {
 722         return -ENODEV;
 723 }
 724
 725 static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
 726 {
 727         return -ENODEV;
 728 }
 729
 730 static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
 731 {
 732         return -ENODEV;
 733 }
 734
 735 static inline int zynqmp_pm_set_boot_health_status(u32 value)
 736 {
 737         return -ENODEV;
 738 }
 739
 740 static inline int zynqmp_pm_pinctrl_request(const u32 pin)
 741 {
 742         return -ENODEV;
 743 }
 744
 745 static inline int zynqmp_pm_pinctrl_release(const u32 pin)
 746 {
 747         return -ENODEV;
 748 }
 749
 750 static inline int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id)
 751 {
 752         return -ENODEV;
 753 }
 754
 755 static inline int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
 756 {
 757         return -ENODEV;
 758 }
 759
 760 static inline int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id)
 761 {
 762         return -ENODEV;
 763 }
 764
 765 static inline int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
 766                                                u32 *value)
 767 {
 768         return -ENODEV;
 769 }
 770
 771 static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
 772                                                u32 value)
 773 {
 774         return -ENODEV;
 775 }
 776
 777 static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address)
 778 {
 779         return -ENODEV;
 780 }
 781
 782 static inline int zynqmp_pm_register_notifier(const u32 node, const u32 event,
 783                                               const u32 wake, const u32 enable)
 784 {
 785         return -ENODEV;
 786 }
 787
 788 static inline int zynqmp_pm_feature(const u32 api_id)
 789 {
 790         return -ENODEV;
 791 }
 792
 793 static inline int zynqmp_pm_set_feature_config(enum pm_feature_config_id id,
 794                                                u32 value)
 795 {
 796         return -ENODEV;
 797 }
 798
 799 static inline int zynqmp_pm_get_feature_config(enum pm_feature_config_id id,
 800                                                u32 *payload)
 801 {
 802         return -ENODEV;
 803 }
 804
 805 static inline int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset)
 806 {
 807         return -ENODEV;
 808 }
 809
 810 static inline int zynqmp_pm_force_pwrdwn(const u32 target,
 811                                          const enum zynqmp_pm_request_ack ack)
 812 {
 813         return -ENODEV;
 814 }
 815
 816 static inline int zynqmp_pm_request_wake(const u32 node,
 817                                          const bool set_addr,
 818                                          const u64 address,
 819                                          const enum zynqmp_pm_request_ack ack)
 820 {
 821         return -ENODEV;
 822 }
 823
 824 static inline int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode)
 825 {
 826         return -ENODEV;
 827 }
 828
 829 static inline int zynqmp_pm_set_rpu_mode(u32 node_id, u32 arg1)
 830 {
 831         return -ENODEV;
 832 }
 833
 834 static inline int zynqmp_pm_set_tcm_config(u32 node_id, u32 arg1)
 835 {
 836         return -ENODEV;
 837 }
 838
 839 static inline int zynqmp_pm_set_sd_config(u32 node,
 840                                           enum pm_sd_config_type config,
 841                                           u32 value)
 842 {
 843         return -ENODEV;
 844 }
 845
 846 static inline int zynqmp_pm_set_gem_config(u32 node,
 847                                            enum pm_gem_config_type config,
 848                                            u32 value)
 849 {
 850         return -ENODEV;
 851 }
 852
 853 #endif
 854
 855 #endif /* __FIRMWARE_ZYNQMP_H__ */