include/linux/firmware/xlnx-zynqmp.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Xilinx Zynq MPSoC Firmware layer
   4  *
   5  *  Copyright (C) 2014-2021 Xilinx
   6  *
   7  *  Michal Simek <michal.simek@xilinx.com>
   8  *  Davorin Mista <davorin.mista@aggios.com>
   9  *  Jolly Shah <jollys@xilinx.com>
  10  *  Rajan Vaja <rajanv@xilinx.com>
  11  */
  12
  13 #ifndef __FIRMWARE_ZYNQMP_H__
  14 #define __FIRMWARE_ZYNQMP_H__
  15 #include <linux/types.h>
  16
  17 #include <linux/err.h>
  18
  19 #define ZYNQMP_PM_VERSION_MAJOR 1
  20 #define ZYNQMP_PM_VERSION_MINOR 0
  21
  22 #define ZYNQMP_PM_VERSION       ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
  23                                         ZYNQMP_PM_VERSION_MINOR)
  24
  25 #define ZYNQMP_TZ_VERSION_MAJOR 1
  26 #define ZYNQMP_TZ_VERSION_MINOR 0
  27
  28 #define ZYNQMP_TZ_VERSION       ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
  29                                         ZYNQMP_TZ_VERSION_MINOR)
  30
  31 /* SMC SIP service Call Function Identifier Prefix */
  32 #define PM_SIP_SVC                      0xC2000000
  33
  34 /* PM API versions */
  35 #define PM_API_VERSION_2        2
  36
  37 /* ATF only commands */
  38 #define TF_A_PM_REGISTER_SGI            0xa04
  39 #define PM_GET_TRUSTZONE_VERSION        0xa03
  40 #define PM_SET_SUSPEND_MODE             0xa02
  41 #define GET_CALLBACK_DATA               0xa01
  42
  43 /* Number of 32bits values in payload */
  44 #define PAYLOAD_ARG_CNT 4U
  45
  46 /* Number of arguments for a callback */
  47 #define CB_ARG_CNT     4
  48
  49 /* Payload size (consists of callback API ID + arguments) */
  50 #define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
  51
  52 #define ZYNQMP_PM_MAX_QOS               100U
  53
  54 #define GSS_NUM_REGS    (4)
  55
  56 /* Node capabilities */
  57 #define ZYNQMP_PM_CAPABILITY_ACCESS     0x1U
  58 #define ZYNQMP_PM_CAPABILITY_CONTEXT    0x2U
  59 #define ZYNQMP_PM_CAPABILITY_WAKEUP     0x4U
  60 #define ZYNQMP_PM_CAPABILITY_UNUSABLE   0x8U
  61
  62 /* Loader commands */
  63 #define PM_LOAD_PDI     0x701
  64 #define PDI_SRC_DDR     0xF
  65
  66 /*
  67  * Firmware FPGA Manager flags
  68  * XILINX_ZYNQMP_PM_FPGA_FULL:  FPGA full reconfiguration
  69  * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
  70  */
  71 #define XILINX_ZYNQMP_PM_FPGA_FULL      0x0U
  72 #define XILINX_ZYNQMP_PM_FPGA_PARTIAL   BIT(0)
  73
  74 /*
  75  * Node IDs for the Error Events.
  76  */
  77 #define EVENT_ERROR_PMC_ERR1    (0x28100000U)
  78 #define EVENT_ERROR_PMC_ERR2    (0x28104000U)
  79 #define EVENT_ERROR_PSM_ERR1    (0x28108000U)
  80 #define EVENT_ERROR_PSM_ERR2    (0x2810C000U)
  81
  82 enum pm_api_cb_id {
  83         PM_INIT_SUSPEND_CB = 30,
  84         PM_ACKNOWLEDGE_CB = 31,
  85         PM_NOTIFY_CB = 32,
  86 };
  87
  88 enum pm_api_id {
  89         PM_GET_API_VERSION = 1,
  90         PM_REGISTER_NOTIFIER = 5,
  91         PM_FORCE_POWERDOWN = 8,
  92         PM_REQUEST_WAKEUP = 10,
  93         PM_SYSTEM_SHUTDOWN = 12,
  94         PM_REQUEST_NODE = 13,
  95         PM_RELEASE_NODE = 14,
  96         PM_SET_REQUIREMENT = 15,
  97         PM_RESET_ASSERT = 17,
  98         PM_RESET_GET_STATUS = 18,
  99         PM_MMIO_WRITE = 19,
 100         PM_MMIO_READ = 20,
 101         PM_PM_INIT_FINALIZE = 21,
 102         PM_FPGA_LOAD = 22,
 103         PM_FPGA_GET_STATUS = 23,
 104         PM_GET_CHIPID = 24,
 105         PM_SECURE_SHA = 26,
 106         PM_PINCTRL_REQUEST = 28,
 107         PM_PINCTRL_RELEASE = 29,
 108         PM_PINCTRL_GET_FUNCTION = 30,
 109         PM_PINCTRL_SET_FUNCTION = 31,
 110         PM_PINCTRL_CONFIG_PARAM_GET = 32,
 111         PM_PINCTRL_CONFIG_PARAM_SET = 33,
 112         PM_IOCTL = 34,
 113         PM_QUERY_DATA = 35,
 114         PM_CLOCK_ENABLE = 36,
 115         PM_CLOCK_DISABLE = 37,
 116         PM_CLOCK_GETSTATE = 38,
 117         PM_CLOCK_SETDIVIDER = 39,
 118         PM_CLOCK_GETDIVIDER = 40,
 119         PM_CLOCK_SETRATE = 41,
 120         PM_CLOCK_GETRATE = 42,
 121         PM_CLOCK_SETPARENT = 43,
 122         PM_CLOCK_GETPARENT = 44,
 123         PM_SECURE_AES = 47,
 124         PM_FEATURE_CHECK = 63,
 125 };
 126
 127 /* PMU-FW return status codes */
 128 enum pm_ret_status {
 129         XST_PM_SUCCESS = 0,
 130         XST_PM_NO_FEATURE = 19,
 131         XST_PM_INTERNAL = 2000,
 132         XST_PM_CONFLICT = 2001,
 133         XST_PM_NO_ACCESS = 2002,
 134         XST_PM_INVALID_NODE = 2003,
 135         XST_PM_DOUBLE_REQ = 2004,
 136         XST_PM_ABORT_SUSPEND = 2005,
 137         XST_PM_MULT_USER = 2008,
 138 };
 139
 140 enum pm_ioctl_id {
 141         IOCTL_GET_RPU_OPER_MODE = 0,
 142         IOCTL_SET_RPU_OPER_MODE = 1,
 143         IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
 144         IOCTL_TCM_COMB_CONFIG = 3,
 145         IOCTL_SET_TAPDELAY_BYPASS = 4,
 146         IOCTL_SD_DLL_RESET = 6,
 147         IOCTL_SET_SD_TAPDELAY = 7,
 148         IOCTL_SET_PLL_FRAC_MODE = 8,
 149         IOCTL_GET_PLL_FRAC_MODE = 9,
 150         IOCTL_SET_PLL_FRAC_DATA = 10,
 151         IOCTL_GET_PLL_FRAC_DATA = 11,
 152         IOCTL_WRITE_GGS = 12,
 153         IOCTL_READ_GGS = 13,
 154         IOCTL_WRITE_PGGS = 14,
 155         IOCTL_READ_PGGS = 15,
 156         /* Set healthy bit value */
 157         IOCTL_SET_BOOT_HEALTH_STATUS = 17,
 158         IOCTL_OSPI_MUX_SELECT = 21,
 159         /* Register SGI to ATF */
 160         IOCTL_REGISTER_SGI = 25,
 161         /* Runtime feature configuration */
 162         IOCTL_SET_FEATURE_CONFIG = 26,
 163         IOCTL_GET_FEATURE_CONFIG = 27,
 164         /* Dynamic SD/GEM configuration */
 165         IOCTL_SET_SD_CONFIG = 30,
 166         IOCTL_SET_GEM_CONFIG = 31,
 167 };
 168
 169 enum pm_query_id {
 170         PM_QID_INVALID = 0,
 171         PM_QID_CLOCK_GET_NAME = 1,
 172         PM_QID_CLOCK_GET_TOPOLOGY = 2,
 173         PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
 174         PM_QID_CLOCK_GET_PARENTS = 4,
 175         PM_QID_CLOCK_GET_ATTRIBUTES = 5,
 176         PM_QID_PINCTRL_GET_NUM_PINS = 6,
 177         PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7,
 178         PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8,
 179         PM_QID_PINCTRL_GET_FUNCTION_NAME = 9,
 180         PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10,
 181         PM_QID_PINCTRL_GET_PIN_GROUPS = 11,
 182         PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
 183         PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
 184 };
 185
 186 enum rpu_oper_mode {
 187         PM_RPU_MODE_LOCKSTEP = 0,
 188         PM_RPU_MODE_SPLIT = 1,
 189 };
 190
 191 enum rpu_boot_mem {
 192         PM_RPU_BOOTMEM_LOVEC = 0,
 193         PM_RPU_BOOTMEM_HIVEC = 1,
 194 };
 195
 196 enum rpu_tcm_comb {
 197         PM_RPU_TCM_SPLIT = 0,
 198         PM_RPU_TCM_COMB = 1,
 199 };
 200
 201 enum zynqmp_pm_reset_action {
 202         PM_RESET_ACTION_RELEASE = 0,
 203         PM_RESET_ACTION_ASSERT = 1,
 204         PM_RESET_ACTION_PULSE = 2,
 205 };
 206
 207 enum zynqmp_pm_reset {
 208         ZYNQMP_PM_RESET_START = 1000,
 209         ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
 210         ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001,
 211         ZYNQMP_PM_RESET_PCIE_CTRL = 1002,
 212         ZYNQMP_PM_RESET_DP = 1003,
 213         ZYNQMP_PM_RESET_SWDT_CRF = 1004,
 214         ZYNQMP_PM_RESET_AFI_FM5 = 1005,
 215         ZYNQMP_PM_RESET_AFI_FM4 = 1006,
 216         ZYNQMP_PM_RESET_AFI_FM3 = 1007,
 217         ZYNQMP_PM_RESET_AFI_FM2 = 1008,
 218         ZYNQMP_PM_RESET_AFI_FM1 = 1009,
 219         ZYNQMP_PM_RESET_AFI_FM0 = 1010,
 220         ZYNQMP_PM_RESET_GDMA = 1011,
 221         ZYNQMP_PM_RESET_GPU_PP1 = 1012,
 222         ZYNQMP_PM_RESET_GPU_PP0 = 1013,
 223         ZYNQMP_PM_RESET_GPU = 1014,
 224         ZYNQMP_PM_RESET_GT = 1015,
 225         ZYNQMP_PM_RESET_SATA = 1016,
 226         ZYNQMP_PM_RESET_ACPU3_PWRON = 1017,
 227         ZYNQMP_PM_RESET_ACPU2_PWRON = 1018,
 228         ZYNQMP_PM_RESET_ACPU1_PWRON = 1019,
 229         ZYNQMP_PM_RESET_ACPU0_PWRON = 1020,
 230         ZYNQMP_PM_RESET_APU_L2 = 1021,
 231         ZYNQMP_PM_RESET_ACPU3 = 1022,
 232         ZYNQMP_PM_RESET_ACPU2 = 1023,
 233         ZYNQMP_PM_RESET_ACPU1 = 1024,
 234         ZYNQMP_PM_RESET_ACPU0 = 1025,
 235         ZYNQMP_PM_RESET_DDR = 1026,
 236         ZYNQMP_PM_RESET_APM_FPD = 1027,
 237         ZYNQMP_PM_RESET_SOFT = 1028,
 238         ZYNQMP_PM_RESET_GEM0 = 1029,
 239         ZYNQMP_PM_RESET_GEM1 = 1030,
 240         ZYNQMP_PM_RESET_GEM2 = 1031,
 241         ZYNQMP_PM_RESET_GEM3 = 1032,
 242         ZYNQMP_PM_RESET_QSPI = 1033,
 243         ZYNQMP_PM_RESET_UART0 = 1034,
 244         ZYNQMP_PM_RESET_UART1 = 1035,
 245         ZYNQMP_PM_RESET_SPI0 = 1036,
 246         ZYNQMP_PM_RESET_SPI1 = 1037,
 247         ZYNQMP_PM_RESET_SDIO0 = 1038,
 248         ZYNQMP_PM_RESET_SDIO1 = 1039,
 249         ZYNQMP_PM_RESET_CAN0 = 1040,
 250         ZYNQMP_PM_RESET_CAN1 = 1041,
 251         ZYNQMP_PM_RESET_I2C0 = 1042,
 252         ZYNQMP_PM_RESET_I2C1 = 1043,
 253         ZYNQMP_PM_RESET_TTC0 = 1044,
 254         ZYNQMP_PM_RESET_TTC1 = 1045,
 255         ZYNQMP_PM_RESET_TTC2 = 1046,
 256         ZYNQMP_PM_RESET_TTC3 = 1047,
 257         ZYNQMP_PM_RESET_SWDT_CRL = 1048,
 258         ZYNQMP_PM_RESET_NAND = 1049,
 259         ZYNQMP_PM_RESET_ADMA = 1050,
 260         ZYNQMP_PM_RESET_GPIO = 1051,
 261         ZYNQMP_PM_RESET_IOU_CC = 1052,
 262         ZYNQMP_PM_RESET_TIMESTAMP = 1053,
 263         ZYNQMP_PM_RESET_RPU_R50 = 1054,
 264         ZYNQMP_PM_RESET_RPU_R51 = 1055,
 265         ZYNQMP_PM_RESET_RPU_AMBA = 1056,
 266         ZYNQMP_PM_RESET_OCM = 1057,
 267         ZYNQMP_PM_RESET_RPU_PGE = 1058,
 268         ZYNQMP_PM_RESET_USB0_CORERESET = 1059,
 269         ZYNQMP_PM_RESET_USB1_CORERESET = 1060,
 270         ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061,
 271         ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062,
 272         ZYNQMP_PM_RESET_USB0_APB = 1063,
 273         ZYNQMP_PM_RESET_USB1_APB = 1064,
 274         ZYNQMP_PM_RESET_IPI = 1065,
 275         ZYNQMP_PM_RESET_APM_LPD = 1066,
 276         ZYNQMP_PM_RESET_RTC = 1067,
 277         ZYNQMP_PM_RESET_SYSMON = 1068,
 278         ZYNQMP_PM_RESET_AFI_FM6 = 1069,
 279         ZYNQMP_PM_RESET_LPD_SWDT = 1070,
 280         ZYNQMP_PM_RESET_FPD = 1071,
 281         ZYNQMP_PM_RESET_RPU_DBG1 = 1072,
 282         ZYNQMP_PM_RESET_RPU_DBG0 = 1073,
 283         ZYNQMP_PM_RESET_DBG_LPD = 1074,
 284         ZYNQMP_PM_RESET_DBG_FPD = 1075,
 285         ZYNQMP_PM_RESET_APLL = 1076,
 286         ZYNQMP_PM_RESET_DPLL = 1077,
 287         ZYNQMP_PM_RESET_VPLL = 1078,
 288         ZYNQMP_PM_RESET_IOPLL = 1079,
 289         ZYNQMP_PM_RESET_RPLL = 1080,
 290         ZYNQMP_PM_RESET_GPO3_PL_0 = 1081,
 291         ZYNQMP_PM_RESET_GPO3_PL_1 = 1082,
 292         ZYNQMP_PM_RESET_GPO3_PL_2 = 1083,
 293         ZYNQMP_PM_RESET_GPO3_PL_3 = 1084,
 294         ZYNQMP_PM_RESET_GPO3_PL_4 = 1085,
 295         ZYNQMP_PM_RESET_GPO3_PL_5 = 1086,
 296         ZYNQMP_PM_RESET_GPO3_PL_6 = 1087,
 297         ZYNQMP_PM_RESET_GPO3_PL_7 = 1088,
 298         ZYNQMP_PM_RESET_GPO3_PL_8 = 1089,
 299         ZYNQMP_PM_RESET_GPO3_PL_9 = 1090,
 300         ZYNQMP_PM_RESET_GPO3_PL_10 = 1091,
 301         ZYNQMP_PM_RESET_GPO3_PL_11 = 1092,
 302         ZYNQMP_PM_RESET_GPO3_PL_12 = 1093,
 303         ZYNQMP_PM_RESET_GPO3_PL_13 = 1094,
 304         ZYNQMP_PM_RESET_GPO3_PL_14 = 1095,
 305         ZYNQMP_PM_RESET_GPO3_PL_15 = 1096,
 306         ZYNQMP_PM_RESET_GPO3_PL_16 = 1097,
 307         ZYNQMP_PM_RESET_GPO3_PL_17 = 1098,
 308         ZYNQMP_PM_RESET_GPO3_PL_18 = 1099,
 309         ZYNQMP_PM_RESET_GPO3_PL_19 = 1100,
 310         ZYNQMP_PM_RESET_GPO3_PL_20 = 1101,
 311         ZYNQMP_PM_RESET_GPO3_PL_21 = 1102,
 312         ZYNQMP_PM_RESET_GPO3_PL_22 = 1103,
 313         ZYNQMP_PM_RESET_GPO3_PL_23 = 1104,
 314         ZYNQMP_PM_RESET_GPO3_PL_24 = 1105,
 315         ZYNQMP_PM_RESET_GPO3_PL_25 = 1106,
 316         ZYNQMP_PM_RESET_GPO3_PL_26 = 1107,
 317         ZYNQMP_PM_RESET_GPO3_PL_27 = 1108,
 318         ZYNQMP_PM_RESET_GPO3_PL_28 = 1109,
 319         ZYNQMP_PM_RESET_GPO3_PL_29 = 1110,
 320         ZYNQMP_PM_RESET_GPO3_PL_30 = 1111,
 321         ZYNQMP_PM_RESET_GPO3_PL_31 = 1112,
 322         ZYNQMP_PM_RESET_RPU_LS = 1113,
 323         ZYNQMP_PM_RESET_PS_ONLY = 1114,
 324         ZYNQMP_PM_RESET_PL = 1115,
 325         ZYNQMP_PM_RESET_PS_PL0 = 1116,
 326         ZYNQMP_PM_RESET_PS_PL1 = 1117,
 327         ZYNQMP_PM_RESET_PS_PL2 = 1118,
 328         ZYNQMP_PM_RESET_PS_PL3 = 1119,
 329         ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
 330 };
 331
 332 enum zynqmp_pm_suspend_reason {
 333         SUSPEND_POWER_REQUEST = 201,
 334         SUSPEND_ALERT = 202,
 335         SUSPEND_SYSTEM_SHUTDOWN = 203,
 336 };
 337
 338 enum zynqmp_pm_request_ack {
 339         ZYNQMP_PM_REQUEST_ACK_NO = 1,
 340         ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2,
 341         ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3,
 342 };
 343
 344 enum pm_node_id {
 345         NODE_SD_0 = 39,
 346         NODE_SD_1 = 40,
 347 };
 348
 349 enum tap_delay_type {
 350         PM_TAPDELAY_INPUT = 0,
 351         PM_TAPDELAY_OUTPUT = 1,
 352 };
 353
 354 enum dll_reset_type {
 355         PM_DLL_RESET_ASSERT = 0,
 356         PM_DLL_RESET_RELEASE = 1,
 357         PM_DLL_RESET_PULSE = 2,
 358 };
 359
 360 enum pm_pinctrl_config_param {
 361         PM_PINCTRL_CONFIG_SLEW_RATE = 0,
 362         PM_PINCTRL_CONFIG_BIAS_STATUS = 1,
 363         PM_PINCTRL_CONFIG_PULL_CTRL = 2,
 364         PM_PINCTRL_CONFIG_SCHMITT_CMOS = 3,
 365         PM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4,
 366         PM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5,
 367         PM_PINCTRL_CONFIG_TRI_STATE = 6,
 368         PM_PINCTRL_CONFIG_MAX = 7,
 369 };
 370
 371 enum pm_pinctrl_slew_rate {
 372         PM_PINCTRL_SLEW_RATE_FAST = 0,
 373         PM_PINCTRL_SLEW_RATE_SLOW = 1,
 374 };
 375
 376 enum pm_pinctrl_bias_status {
 377         PM_PINCTRL_BIAS_DISABLE = 0,
 378         PM_PINCTRL_BIAS_ENABLE = 1,
 379 };
 380
 381 enum pm_pinctrl_pull_ctrl {
 382         PM_PINCTRL_BIAS_PULL_DOWN = 0,
 383         PM_PINCTRL_BIAS_PULL_UP = 1,
 384 };
 385
 386 enum pm_pinctrl_schmitt_cmos {
 387         PM_PINCTRL_INPUT_TYPE_CMOS = 0,
 388         PM_PINCTRL_INPUT_TYPE_SCHMITT = 1,
 389 };
 390
 391 enum pm_pinctrl_drive_strength {
 392         PM_PINCTRL_DRIVE_STRENGTH_2MA = 0,
 393         PM_PINCTRL_DRIVE_STRENGTH_4MA = 1,
 394         PM_PINCTRL_DRIVE_STRENGTH_8MA = 2,
 395         PM_PINCTRL_DRIVE_STRENGTH_12MA = 3,
 396 };
 397
 398 enum pm_pinctrl_tri_state {
 399         PM_PINCTRL_TRI_STATE_DISABLE = 0,
 400         PM_PINCTRL_TRI_STATE_ENABLE = 1,
 401 };
 402
 403 enum zynqmp_pm_shutdown_type {
 404         ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0,
 405         ZYNQMP_PM_SHUTDOWN_TYPE_RESET = 1,
 406         ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY = 2,
 407 };
 408
 409 enum zynqmp_pm_shutdown_subtype {
 410         ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM = 0,
 411         ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY = 1,
 412         ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2,
 413 };
 414
 415 enum tap_delay_signal_type {
 416         PM_TAPDELAY_NAND_DQS_IN = 0,
 417         PM_TAPDELAY_NAND_DQS_OUT = 1,
 418         PM_TAPDELAY_QSPI = 2,
 419         PM_TAPDELAY_MAX = 3,
 420 };
 421
 422 enum tap_delay_bypass_ctrl {
 423         PM_TAPDELAY_BYPASS_DISABLE = 0,
 424         PM_TAPDELAY_BYPASS_ENABLE = 1,
 425 };
 426
 427 enum ospi_mux_select_type {
 428         PM_OSPI_MUX_SEL_DMA = 0,
 429         PM_OSPI_MUX_SEL_LINEAR = 1,
 430 };
 431
 432 enum pm_feature_config_id {
 433         PM_FEATURE_INVALID = 0,
 434         PM_FEATURE_OVERTEMP_STATUS = 1,
 435         PM_FEATURE_OVERTEMP_VALUE = 2,
 436         PM_FEATURE_EXTWDT_STATUS = 3,
 437         PM_FEATURE_EXTWDT_VALUE = 4,
 438 };
 439
 440 /**
 441  * enum pm_sd_config_type - PM SD configuration.
 442  * @SD_CONFIG_EMMC_SEL: To set SD_EMMC_SEL in CTRL_REG_SD and SD_SLOTTYPE
 443  * @SD_CONFIG_BASECLK: To set SD_BASECLK in SD_CONFIG_REG1
 444  * @SD_CONFIG_8BIT: To set SD_8BIT in SD_CONFIG_REG2
 445  * @SD_CONFIG_FIXED: To set fixed config registers
 446  */
 447 enum pm_sd_config_type {
 448         SD_CONFIG_EMMC_SEL = 1,
 449         SD_CONFIG_BASECLK = 2,
 450         SD_CONFIG_8BIT = 3,
 451         SD_CONFIG_FIXED = 4,
 452 };
 453
 454 /**
 455  * enum pm_gem_config_type - PM GEM configuration.
 456  * @GEM_CONFIG_SGMII_MODE: To set GEM_SGMII_MODE in GEM_CLK_CTRL register
 457  * @GEM_CONFIG_FIXED: To set fixed config registers
 458  */
 459 enum pm_gem_config_type {
 460         GEM_CONFIG_SGMII_MODE = 1,
 461         GEM_CONFIG_FIXED = 2,
 462 };
 463
 464 /**
 465  * struct zynqmp_pm_query_data - PM query data
 466  * @qid:        query ID
 467  * @arg1:       Argument 1 of query data
 468  * @arg2:       Argument 2 of query data
 469  * @arg3:       Argument 3 of query data
 470  */
 471 struct zynqmp_pm_query_data {
 472         u32 qid;
 473         u32 arg1;
 474         u32 arg2;
 475         u32 arg3;
 476 };
 477
 478 int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
 479                         u32 arg2, u32 arg3, u32 *ret_payload);
 480
 481 #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
 482 int zynqmp_pm_get_api_version(u32 *version);
 483 int zynqmp_pm_get_chipid(u32 *idcode, u32 *version);
 484 int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out);
 485 int zynqmp_pm_clock_enable(u32 clock_id);
 486 int zynqmp_pm_clock_disable(u32 clock_id);
 487 int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state);
 488 int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider);
 489 int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider);
 490 int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate);
 491 int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate);
 492 int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id);
 493 int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id);
 494 int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode);
 495 int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode);
 496 int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data);
 497 int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data);
 498 int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value);
 499 int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type);
 500 int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select);
 501 int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
 502                            const enum zynqmp_pm_reset_action assert_flag);
 503 int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status);
 504 unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode);
 505 int zynqmp_pm_bootmode_write(u32 ps_mode);
 506 int zynqmp_pm_init_finalize(void);
 507 int zynqmp_pm_set_suspend_mode(u32 mode);
 508 int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
 509                            const u32 qos, const enum zynqmp_pm_request_ack ack);
 510 int zynqmp_pm_release_node(const u32 node);
 511 int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
 512                               const u32 qos,
 513                               const enum zynqmp_pm_request_ack ack);
 514 int zynqmp_pm_aes_engine(const u64 address, u32 *out);
 515 int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags);
 516 int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
 517 int zynqmp_pm_fpga_get_status(u32 *value);
 518 int zynqmp_pm_write_ggs(u32 index, u32 value);
 519 int zynqmp_pm_read_ggs(u32 index, u32 *value);
 520 int zynqmp_pm_write_pggs(u32 index, u32 value);
 521 int zynqmp_pm_read_pggs(u32 index, u32 *value);
 522 int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value);
 523 int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
 524 int zynqmp_pm_set_boot_health_status(u32 value);
 525 int zynqmp_pm_pinctrl_request(const u32 pin);
 526 int zynqmp_pm_pinctrl_release(const u32 pin);
 527 int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id);
 528 int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id);
 529 int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
 530                                  u32 *value);
 531 int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
 532                                  u32 value);
 533 int zynqmp_pm_load_pdi(const u32 src, const u64 address);
 534 int zynqmp_pm_register_notifier(const u32 node, const u32 event,
 535                                 const u32 wake, const u32 enable);
 536 int zynqmp_pm_feature(const u32 api_id);
 537 int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
 538 int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value);
 539 int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload);
 540 int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset);
 541 int zynqmp_pm_force_pwrdwn(const u32 target,
 542                            const enum zynqmp_pm_request_ack ack);
 543 int zynqmp_pm_request_wake(const u32 node,
 544                            const bool set_addr,
 545                            const u64 address,
 546                            const enum zynqmp_pm_request_ack ack);
 547 int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode);
 548 int zynqmp_pm_set_rpu_mode(u32 node_id, u32 arg1);
 549 int zynqmp_pm_set_tcm_config(u32 node_id, u32 arg1);
 550 int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value);
 551 int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config,
 552                              u32 value);
 553 #else
 554 static inline int zynqmp_pm_get_api_version(u32 *version)
 555 {
 556         return -ENODEV;
 557 }
 558
 559 static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
 560 {
 561         return -ENODEV;
 562 }
 563
 564 static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,
 565                                        u32 *out)
 566 {
 567         return -ENODEV;
 568 }
 569
 570 static inline int zynqmp_pm_clock_enable(u32 clock_id)
 571 {
 572         return -ENODEV;
 573 }
 574
 575 static inline int zynqmp_pm_clock_disable(u32 clock_id)
 576 {
 577         return -ENODEV;
 578 }
 579
 580 static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
 581 {
 582         return -ENODEV;
 583 }
 584
 585 static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
 586 {
 587         return -ENODEV;
 588 }
 589
 590 static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
 591 {
 592         return -ENODEV;
 593 }
 594
 595 static inline int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate)
 596 {
 597         return -ENODEV;
 598 }
 599
 600 static inline int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate)
 601 {
 602         return -ENODEV;
 603 }
 604
 605 static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id)
 606 {
 607         return -ENODEV;
 608 }
 609
 610 static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
 611 {
 612         return -ENODEV;
 613 }
 614
 615 static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode)
 616 {
 617         return -ENODEV;
 618 }
 619
 620 static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode)
 621 {
 622         return -ENODEV;
 623 }
 624
 625 static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data)
 626 {
 627         return -ENODEV;
 628 }
 629
 630 static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data)
 631 {
 632         return -ENODEV;
 633 }
 634
 635 static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value)
 636 {
 637         return -ENODEV;
 638 }
 639
 640 static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
 641 {
 642         return -ENODEV;
 643 }
 644
 645 static inline int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select)
 646 {
 647         return -ENODEV;
 648 }
 649
 650 static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
 651                                          const enum zynqmp_pm_reset_action assert_flag)
 652 {
 653         return -ENODEV;
 654 }
 655
 656 static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,
 657                                              u32 *status)
 658 {
 659         return -ENODEV;
 660 }
 661
 662 static inline unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode)
 663 {
 664         return -ENODEV;
 665 }
 666
 667 static inline int zynqmp_pm_bootmode_write(u32 ps_mode)
 668 {
 669         return -ENODEV;
 670 }
 671
 672 static inline int zynqmp_pm_init_finalize(void)
 673 {
 674         return -ENODEV;
 675 }
 676
 677 static inline int zynqmp_pm_set_suspend_mode(u32 mode)
 678 {
 679         return -ENODEV;
 680 }
 681
 682 static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
 683                                          const u32 qos,
 684                                          const enum zynqmp_pm_request_ack ack)
 685 {
 686         return -ENODEV;
 687 }
 688
 689 static inline int zynqmp_pm_release_node(const u32 node)
 690 {
 691         return -ENODEV;
 692 }
 693
 694 static inline int zynqmp_pm_set_requirement(const u32 node,
 695                                             const u32 capabilities,
 696                                             const u32 qos,
 697                                             const enum zynqmp_pm_request_ack ack)
 698 {
 699         return -ENODEV;
 700 }
 701
 702 static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
 703 {
 704         return -ENODEV;
 705 }
 706
 707 static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size,
 708                                      const u32 flags)
 709 {
 710         return -ENODEV;
 711 }
 712
 713 static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
 714                                       const u32 flags)
 715 {
 716         return -ENODEV;
 717 }
 718
 719 static inline int zynqmp_pm_fpga_get_status(u32 *value)
 720 {
 721         return -ENODEV;
 722 }
 723
 724 static inline int zynqmp_pm_write_ggs(u32 index, u32 value)
 725 {
 726         return -ENODEV;
 727 }
 728
 729 static inline int zynqmp_pm_read_ggs(u32 index, u32 *value)
 730 {
 731         return -ENODEV;
 732 }
 733
 734 static inline int zynqmp_pm_write_pggs(u32 index, u32 value)
 735 {
 736         return -ENODEV;
 737 }
 738
 739 static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
 740 {
 741         return -ENODEV;
 742 }
 743
 744 static inline int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value)
 745 {
 746         return -ENODEV;
 747 }
 748
 749 static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
 750 {
 751         return -ENODEV;
 752 }
 753
 754 static inline int zynqmp_pm_set_boot_health_status(u32 value)
 755 {
 756         return -ENODEV;
 757 }
 758
 759 static inline int zynqmp_pm_pinctrl_request(const u32 pin)
 760 {
 761         return -ENODEV;
 762 }
 763
 764 static inline int zynqmp_pm_pinctrl_release(const u32 pin)
 765 {
 766         return -ENODEV;
 767 }
 768
 769 static inline int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id)
 770 {
 771         return -ENODEV;
 772 }
 773
 774 static inline int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
 775 {
 776         return -ENODEV;
 777 }
 778
 779 static inline int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id)
 780 {
 781         return -ENODEV;
 782 }
 783
 784 static inline int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
 785                                                u32 *value)
 786 {
 787         return -ENODEV;
 788 }
 789
 790 static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
 791                                                u32 value)
 792 {
 793         return -ENODEV;
 794 }
 795
 796 static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address)
 797 {
 798         return -ENODEV;
 799 }
 800
 801 static inline int zynqmp_pm_register_notifier(const u32 node, const u32 event,
 802                                               const u32 wake, const u32 enable)
 803 {
 804         return -ENODEV;
 805 }
 806
 807 static inline int zynqmp_pm_feature(const u32 api_id)
 808 {
 809         return -ENODEV;
 810 }
 811
 812 static inline int zynqmp_pm_set_feature_config(enum pm_feature_config_id id,
 813                                                u32 value)
 814 {
 815         return -ENODEV;
 816 }
 817
 818 static inline int zynqmp_pm_get_feature_config(enum pm_feature_config_id id,
 819                                                u32 *payload)
 820 {
 821         return -ENODEV;
 822 }
 823
 824 static inline int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset)
 825 {
 826         return -ENODEV;
 827 }
 828
 829 static inline int zynqmp_pm_force_pwrdwn(const u32 target,
 830                                          const enum zynqmp_pm_request_ack ack)
 831 {
 832         return -ENODEV;
 833 }
 834
 835 static inline int zynqmp_pm_request_wake(const u32 node,
 836                                          const bool set_addr,
 837                                          const u64 address,
 838                                          const enum zynqmp_pm_request_ack ack)
 839 {
 840         return -ENODEV;
 841 }
 842
 843 static inline int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode)
 844 {
 845         return -ENODEV;
 846 }
 847
 848 static inline int zynqmp_pm_set_rpu_mode(u32 node_id, u32 arg1)
 849 {
 850         return -ENODEV;
 851 }
 852
 853 static inline int zynqmp_pm_set_tcm_config(u32 node_id, u32 arg1)
 854 {
 855         return -ENODEV;
 856 }
 857
 858 static inline int zynqmp_pm_set_sd_config(u32 node,
 859                                           enum pm_sd_config_type config,
 860                                           u32 value)
 861 {
 862         return -ENODEV;
 863 }
 864
 865 static inline int zynqmp_pm_set_gem_config(u32 node,
 866                                            enum pm_gem_config_type config,
 867                                            u32 value)
 868 {
 869         return -ENODEV;
 870 }
 871
 872 #endif
 873
 874 #endif /* __FIRMWARE_ZYNQMP_H__ */