2 * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
5 * Copyright (C) 2007 Atmel Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
14 #include <linux/dmaengine.h>
17 * struct dw_dma_platform_data - Controller configuration parameters
18 * @nr_channels: Number of channels supported by hardware (max 8)
19 * @is_private: The device channels should be marked as private and not for
20 * by the general purpose DMA channel allocator.
22 struct dw_dma_platform_data {
23 unsigned int nr_channels;
25 #define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */
26 #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */
27 unsigned char chan_allocation_order;
28 #define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */
29 #define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */
30 unsigned char chan_priority;
34 * enum dw_dma_slave_width - DMA slave register access width.
35 * @DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses
36 * @DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses
37 * @DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses
39 enum dw_dma_slave_width {
40 DW_DMA_SLAVE_WIDTH_8BIT,
41 DW_DMA_SLAVE_WIDTH_16BIT,
42 DW_DMA_SLAVE_WIDTH_32BIT,
46 * struct dw_dma_slave - Controller-specific information about a slave
48 * @dma_dev: required DMA master device
49 * @tx_reg: physical address of data register used for
50 * memory-to-peripheral transfers
51 * @rx_reg: physical address of data register used for
52 * peripheral-to-memory transfers
53 * @reg_width: peripheral register width
54 * @cfg_hi: Platform-specific initializer for the CFG_HI register
55 * @cfg_lo: Platform-specific initializer for the CFG_LO register
56 * @src_master: src master for transfers on allocated channel.
57 * @dst_master: dest master for transfers on allocated channel.
60 struct device *dma_dev;
63 enum dw_dma_slave_width reg_width;
70 /* Platform-configurable bits in CFG_HI */
71 #define DWC_CFGH_FCMODE (1 << 0)
72 #define DWC_CFGH_FIFO_MODE (1 << 1)
73 #define DWC_CFGH_PROTCTL(x) ((x) << 2)
74 #define DWC_CFGH_SRC_PER(x) ((x) << 7)
75 #define DWC_CFGH_DST_PER(x) ((x) << 11)
77 /* Platform-configurable bits in CFG_LO */
78 #define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */
79 #define DWC_CFGL_LOCK_CH_BLOCK (1 << 12)
80 #define DWC_CFGL_LOCK_CH_XACT (2 << 12)
81 #define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */
82 #define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
83 #define DWC_CFGL_LOCK_BUS_XACT (2 << 14)
84 #define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */
85 #define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */
86 #define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */
87 #define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */
89 /* DMA API extensions */
90 struct dw_cyclic_desc {
91 struct dw_desc **desc;
92 unsigned long periods;
93 void (*period_callback)(void *param);
94 void *period_callback_param;
97 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
98 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
99 enum dma_data_direction direction);
100 void dw_dma_cyclic_free(struct dma_chan *chan);
101 int dw_dma_cyclic_start(struct dma_chan *chan);
102 void dw_dma_cyclic_stop(struct dma_chan *chan);
104 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan);
106 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan);
108 #endif /* DW_DMAC_H */