2 * Copyright (c) 2006, Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 * Copyright (C) Ashok Raj <ashok.raj@intel.com>
18 * Copyright (C) Shaohua Li <shaohua.li@intel.com>
24 #include <linux/acpi.h>
25 #include <linux/types.h>
26 #include <linux/msi.h>
27 #include <linux/irqreturn.h>
29 struct acpi_dmar_header;
32 #define DMAR_INTR_REMAP 0x1
33 #define DMAR_X2APIC_OPT_OUT 0x2
36 #ifdef CONFIG_DMAR_TABLE
37 extern struct acpi_table_header *dmar_tbl;
38 struct dmar_drhd_unit {
39 struct list_head list; /* list of drhd units */
40 struct acpi_dmar_header *hdr; /* ACPI header */
41 u64 reg_base_addr; /* register base address*/
42 struct pci_dev **devices; /* target device array */
43 int devices_cnt; /* target device count */
44 u16 segment; /* PCI domain */
45 u8 ignored:1; /* ignore drhd */
47 struct intel_iommu *iommu;
50 extern struct list_head dmar_drhd_units;
52 #define for_each_drhd_unit(drhd) \
53 list_for_each_entry(drhd, &dmar_drhd_units, list)
55 #define for_each_active_iommu(i, drhd) \
56 list_for_each_entry(drhd, &dmar_drhd_units, list) \
57 if (i=drhd->iommu, drhd->ignored) {} else
59 #define for_each_iommu(i, drhd) \
60 list_for_each_entry(drhd, &dmar_drhd_units, list) \
61 if (i=drhd->iommu, 0) {} else
63 extern int dmar_table_init(void);
64 extern int dmar_dev_scope_init(void);
66 /* Intel IOMMU detection */
67 extern int detect_intel_iommu(void);
68 extern int enable_drhd_fault_handling(void);
70 extern int parse_ioapics_under_ir(void);
71 extern int alloc_iommu(struct dmar_drhd_unit *);
73 static inline int detect_intel_iommu(void)
78 static inline int dmar_table_init(void)
82 static inline int enable_drhd_fault_handling(void)
86 #endif /* !CONFIG_DMAR_TABLE */
117 #ifdef CONFIG_IRQ_REMAP
118 extern int get_irte(int irq, struct irte *entry);
119 extern int modify_irte(int irq, struct irte *irte_modified);
120 extern int alloc_irte(struct intel_iommu *iommu, int irq, u16 count);
121 extern int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
123 extern int map_irq_to_irte_handle(int irq, u16 *sub_handle);
125 extern struct intel_iommu *map_dev_to_ir(struct pci_dev *dev);
126 extern struct intel_iommu *map_ioapic_to_ir(int apic);
127 extern struct intel_iommu *map_hpet_to_ir(u8 id);
128 extern int set_ioapic_sid(struct irte *irte, int apic);
129 extern int set_hpet_sid(struct irte *irte, u8 id);
130 extern int set_msi_sid(struct irte *irte, struct pci_dev *dev);
132 static inline int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
136 static inline int modify_irte(int irq, struct irte *irte_modified)
140 static inline int map_irq_to_irte_handle(int irq, u16 *sub_handle)
144 static inline int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
149 static inline struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
153 static inline struct intel_iommu *map_ioapic_to_ir(int apic)
157 static inline struct intel_iommu *map_hpet_to_ir(unsigned int hpet_id)
161 static inline int set_ioapic_sid(struct irte *irte, int apic)
165 static inline int set_hpet_sid(struct irte *irte, u8 id)
169 static inline int set_msi_sid(struct irte *irte, struct pci_dev *dev)
177 IRQ_REMAP_XAPIC_MODE,
178 IRQ_REMAP_X2APIC_MODE,
181 /* Can't use the common MSI interrupt functions
182 * since DMAR is not a pci device
185 extern void dmar_msi_unmask(struct irq_data *data);
186 extern void dmar_msi_mask(struct irq_data *data);
187 extern void dmar_msi_read(int irq, struct msi_msg *msg);
188 extern void dmar_msi_write(int irq, struct msi_msg *msg);
189 extern int dmar_set_interrupt(struct intel_iommu *iommu);
190 extern irqreturn_t dmar_fault(int irq, void *dev_id);
191 extern int arch_setup_dmar_msi(unsigned int irq);
193 #ifdef CONFIG_INTEL_IOMMU
194 extern int iommu_detected, no_iommu;
195 extern struct list_head dmar_rmrr_units;
196 struct dmar_rmrr_unit {
197 struct list_head list; /* list of rmrr units */
198 struct acpi_dmar_header *hdr; /* ACPI header */
199 u64 base_address; /* reserved base address*/
200 u64 end_address; /* reserved end address */
201 struct pci_dev **devices; /* target devices */
202 int devices_cnt; /* target device count */
205 #define for_each_rmrr_units(rmrr) \
206 list_for_each_entry(rmrr, &dmar_rmrr_units, list)
208 struct dmar_atsr_unit {
209 struct list_head list; /* list of ATSR units */
210 struct acpi_dmar_header *hdr; /* ACPI header */
211 struct pci_dev **devices; /* target devices */
212 int devices_cnt; /* target device count */
213 u8 include_all:1; /* include all ports */
216 int dmar_parse_rmrr_atsr_dev(void);
217 extern int dmar_parse_one_rmrr(struct acpi_dmar_header *header);
218 extern int dmar_parse_one_atsr(struct acpi_dmar_header *header);
219 extern int dmar_parse_dev_scope(void *start, void *end, int *cnt,
220 struct pci_dev ***devices, u16 segment);
221 extern int intel_iommu_init(void);
222 #else /* !CONFIG_INTEL_IOMMU: */
223 static inline int intel_iommu_init(void) { return -ENODEV; }
224 static inline int dmar_parse_one_rmrr(struct acpi_dmar_header *header)
228 static inline int dmar_parse_one_atsr(struct acpi_dmar_header *header)
232 static inline int dmar_parse_rmrr_atsr_dev(void)
236 #endif /* CONFIG_INTEL_IOMMU */
238 #endif /* __DMAR_H__ */