include/linux/dma/ti-cppi5.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * CPPI5 descriptors interface
   4  *
   5  * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
   6  */
   7
   8 #ifndef __TI_CPPI5_H__
   9 #define __TI_CPPI5_H__
  10
  11 #include <linux/bitops.h>
  12 #include <linux/printk.h>
  13 #include <linux/bug.h>
  14
  15 /**
  16  * struct cppi5_desc_hdr_t - Descriptor header, present in all types of
  17  *                           descriptors
  18  * @pkt_info0:          Packet info word 0 (n/a in Buffer desc)
  19  * @pkt_info0:          Packet info word 1 (n/a in Buffer desc)
  20  * @pkt_info0:          Packet info word 2 (n/a in Buffer desc)
  21  * @src_dst_tag:        Packet info word 3 (n/a in Buffer desc)
  22  */
  23 struct cppi5_desc_hdr_t {
  24         u32 pkt_info0;
  25         u32 pkt_info1;
  26         u32 pkt_info2;
  27         u32 src_dst_tag;
  28 } __packed;
  29
  30 /**
  31  * struct cppi5_host_desc_t - Host-mode packet and buffer descriptor definition
  32  * @hdr:                Descriptor header
  33  * @next_desc:          word 4/5: Linking word
  34  * @buf_ptr:            word 6/7: Buffer pointer
  35  * @buf_info1:          word 8: Buffer valid data length
  36  * @org_buf_len:        word 9: Original buffer length
  37  * @org_buf_ptr:        word 10/11: Original buffer pointer
  38  * @epib[0]:            Extended Packet Info Data (optional, 4 words), and/or
  39  *                      Protocol Specific Data (optional, 0-128 bytes in
  40  *                      multiples of 4), and/or
  41  *                      Other Software Data (0-N bytes, optional)
  42  */
  43 struct cppi5_host_desc_t {
  44         struct cppi5_desc_hdr_t hdr;
  45         u64 next_desc;
  46         u64 buf_ptr;
  47         u32 buf_info1;
  48         u32 org_buf_len;
  49         u64 org_buf_ptr;
  50         u32 epib[];
  51 } __packed;
  52
  53 #define CPPI5_DESC_MIN_ALIGN                    (16U)
  54
  55 #define CPPI5_INFO0_HDESC_EPIB_SIZE             (16U)
  56 #define CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE       (128U)
  57
  58 #define CPPI5_INFO0_HDESC_TYPE_SHIFT            (30U)
  59 #define CPPI5_INFO0_HDESC_TYPE_MASK             GENMASK(31, 30)
  60 #define   CPPI5_INFO0_DESC_TYPE_VAL_HOST        (1U)
  61 #define   CPPI5_INFO0_DESC_TYPE_VAL_MONO        (2U)
  62 #define   CPPI5_INFO0_DESC_TYPE_VAL_TR          (3U)
  63 #define CPPI5_INFO0_HDESC_EPIB_PRESENT          BIT(29)
  64 /*
  65  * Protocol Specific Words location:
  66  * 0 - located in the descriptor,
  67  * 1 = located in the SOP Buffer immediately prior to the data.
  68  */
  69 #define CPPI5_INFO0_HDESC_PSINFO_LOCATION       BIT(28)
  70 #define CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT     (22U)
  71 #define CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK      GENMASK(27, 22)
  72 #define CPPI5_INFO0_HDESC_PKTLEN_SHIFT          (0)
  73 #define CPPI5_INFO0_HDESC_PKTLEN_MASK           GENMASK(21, 0)
  74
  75 #define CPPI5_INFO1_DESC_PKTERROR_SHIFT         (28U)
  76 #define CPPI5_INFO1_DESC_PKTERROR_MASK          GENMASK(31, 28)
  77 #define CPPI5_INFO1_HDESC_PSFLGS_SHIFT          (24U)
  78 #define CPPI5_INFO1_HDESC_PSFLGS_MASK           GENMASK(27, 24)
  79 #define CPPI5_INFO1_DESC_PKTID_SHIFT            (14U)
  80 #define CPPI5_INFO1_DESC_PKTID_MASK             GENMASK(23, 14)
  81 #define CPPI5_INFO1_DESC_FLOWID_SHIFT           (0)
  82 #define CPPI5_INFO1_DESC_FLOWID_MASK            GENMASK(13, 0)
  83 #define CPPI5_INFO1_DESC_FLOWID_DEFAULT         CPPI5_INFO1_DESC_FLOWID_MASK
  84
  85 #define CPPI5_INFO2_HDESC_PKTTYPE_SHIFT         (27U)
  86 #define CPPI5_INFO2_HDESC_PKTTYPE_MASK          GENMASK(31, 27)
  87 /* Return Policy: 0 - Entire packet 1 - Each buffer */
  88 #define CPPI5_INFO2_HDESC_RETPOLICY             BIT(18)
  89 /*
  90  * Early Return:
  91  * 0 = desc pointers should be returned after all reads have been completed
  92  * 1 = desc pointers should be returned immediately upon fetching
  93  * the descriptor and beginning to transfer data.
  94  */
  95 #define CPPI5_INFO2_HDESC_EARLYRET              BIT(17)
  96 /*
  97  * Return Push Policy:
  98  * 0 = Descriptor must be returned to tail of queue
  99  * 1 = Descriptor must be returned to head of queue
 100  */
 101 #define CPPI5_INFO2_DESC_RETPUSHPOLICY          BIT(16)
 102 #define CPPI5_INFO2_DESC_RETP_MASK              GENMASK(18, 16)
 103
 104 #define CPPI5_INFO2_DESC_RETQ_SHIFT             (0)
 105 #define CPPI5_INFO2_DESC_RETQ_MASK              GENMASK(15, 0)
 106
 107 #define CPPI5_INFO3_DESC_SRCTAG_SHIFT           (16U)
 108 #define CPPI5_INFO3_DESC_SRCTAG_MASK            GENMASK(31, 16)
 109 #define CPPI5_INFO3_DESC_DSTTAG_SHIFT           (0)
 110 #define CPPI5_INFO3_DESC_DSTTAG_MASK            GENMASK(15, 0)
 111
 112 #define CPPI5_BUFINFO1_HDESC_DATA_LEN_SHIFT     (0)
 113 #define CPPI5_BUFINFO1_HDESC_DATA_LEN_MASK      GENMASK(27, 0)
 114
 115 #define CPPI5_OBUFINFO0_HDESC_BUF_LEN_SHIFT     (0)
 116 #define CPPI5_OBUFINFO0_HDESC_BUF_LEN_MASK      GENMASK(27, 0)
 117
 118 /**
 119  * struct cppi5_desc_epib_t - Host Packet Descriptor Extended Packet Info Block
 120  * @timestamp:          word 0: application specific timestamp
 121  * @sw_info0:           word 1: Software Info 0
 122  * @sw_info1:           word 1: Software Info 1
 123  * @sw_info2:           word 1: Software Info 2
 124  */
 125 struct cppi5_desc_epib_t {
 126         u32 timestamp;  /* w0: application specific timestamp */
 127         u32 sw_info0;   /* w1: Software Info 0 */
 128         u32 sw_info1;   /* w2: Software Info 1 */
 129         u32 sw_info2;   /* w3: Software Info 2 */
 130 };
 131
 132 /**
 133  * struct cppi5_monolithic_desc_t - Monolithic-mode packet descriptor
 134  * @hdr:                Descriptor header
 135  * @epib[0]:            Extended Packet Info Data (optional, 4 words), and/or
 136  *                      Protocol Specific Data (optional, 0-128 bytes in
 137  *                      multiples of 4), and/or
 138  *                      Other Software Data (0-N bytes, optional)
 139  */
 140 struct cppi5_monolithic_desc_t {
 141         struct cppi5_desc_hdr_t hdr;
 142         u32 epib[];
 143 };
 144
 145 #define CPPI5_INFO2_MDESC_DATA_OFFSET_SHIFT     (18U)
 146 #define CPPI5_INFO2_MDESC_DATA_OFFSET_MASK      GENMASK(26, 18)
 147
 148 /*
 149  * Reload Count:
 150  * 0 = Finish the packet and place the descriptor back on the return queue
 151  * 1-0x1ff = Vector to the Reload Index and resume processing
 152  * 0x1ff indicates perpetual loop, infinite reload until the channel is stopped
 153  */
 154 #define CPPI5_INFO0_TRDESC_RLDCNT_SHIFT         (20U)
 155 #define CPPI5_INFO0_TRDESC_RLDCNT_MASK          GENMASK(28, 20)
 156 #define CPPI5_INFO0_TRDESC_RLDCNT_MAX           (0x1ff)
 157 #define CPPI5_INFO0_TRDESC_RLDCNT_INFINITE      CPPI5_INFO0_TRDESC_RLDCNT_MAX
 158 #define CPPI5_INFO0_TRDESC_RLDIDX_SHIFT         (14U)
 159 #define CPPI5_INFO0_TRDESC_RLDIDX_MASK          GENMASK(19, 14)
 160 #define CPPI5_INFO0_TRDESC_RLDIDX_MAX           (0x3f)
 161 #define CPPI5_INFO0_TRDESC_LASTIDX_SHIFT        (0)
 162 #define CPPI5_INFO0_TRDESC_LASTIDX_MASK         GENMASK(13, 0)
 163
 164 #define CPPI5_INFO1_TRDESC_RECSIZE_SHIFT        (24U)
 165 #define CPPI5_INFO1_TRDESC_RECSIZE_MASK         GENMASK(26, 24)
 166 #define   CPPI5_INFO1_TRDESC_RECSIZE_VAL_16B    (0)
 167 #define   CPPI5_INFO1_TRDESC_RECSIZE_VAL_32B    (1U)
 168 #define   CPPI5_INFO1_TRDESC_RECSIZE_VAL_64B    (2U)
 169 #define   CPPI5_INFO1_TRDESC_RECSIZE_VAL_128B   (3U)
 170
 171 static inline void cppi5_desc_dump(void *desc, u32 size)
 172 {
 173         print_hex_dump(KERN_ERR, "dump udmap_desc: ", DUMP_PREFIX_NONE,
 174                        32, 4, desc, size, false);
 175 }
 176
 177 #define CPPI5_TDCM_MARKER                       (0x1)
 178 /**
 179  * cppi5_desc_is_tdcm - check if the paddr indicates Teardown Complete Message
 180  * @paddr: Physical address of the packet popped from the ring
 181  *
 182  * Returns true if the address indicates TDCM
 183  */
 184 static inline bool cppi5_desc_is_tdcm(dma_addr_t paddr)
 185 {
 186         return (paddr & CPPI5_TDCM_MARKER) ? true : false;
 187 }
 188
 189 /**
 190  * cppi5_desc_get_type - get descriptor type
 191  * @desc_hdr: packet descriptor/TR header
 192  *
 193  * Returns descriptor type:
 194  * CPPI5_INFO0_DESC_TYPE_VAL_HOST
 195  * CPPI5_INFO0_DESC_TYPE_VAL_MONO
 196  * CPPI5_INFO0_DESC_TYPE_VAL_TR
 197  */
 198 static inline u32 cppi5_desc_get_type(struct cppi5_desc_hdr_t *desc_hdr)
 199 {
 200         return (desc_hdr->pkt_info0 & CPPI5_INFO0_HDESC_TYPE_MASK) >>
 201                 CPPI5_INFO0_HDESC_TYPE_SHIFT;
 202 }
 203
 204 /**
 205  * cppi5_desc_get_errflags - get Error Flags from Desc
 206  * @desc_hdr: packet/TR descriptor header
 207  *
 208  * Returns Error Flags from Packet/TR Descriptor
 209  */
 210 static inline u32 cppi5_desc_get_errflags(struct cppi5_desc_hdr_t *desc_hdr)
 211 {
 212         return (desc_hdr->pkt_info1 & CPPI5_INFO1_DESC_PKTERROR_MASK) >>
 213                 CPPI5_INFO1_DESC_PKTERROR_SHIFT;
 214 }
 215
 216 /**
 217  * cppi5_desc_get_pktids - get Packet and Flow ids from Desc
 218  * @desc_hdr: packet/TR descriptor header
 219  * @pkt_id: Packet ID
 220  * @flow_id: Flow ID
 221  *
 222  * Returns Packet and Flow ids from packet/TR descriptor
 223  */
 224 static inline void cppi5_desc_get_pktids(struct cppi5_desc_hdr_t *desc_hdr,
 225                                          u32 *pkt_id, u32 *flow_id)
 226 {
 227         *pkt_id = (desc_hdr->pkt_info1 & CPPI5_INFO1_DESC_PKTID_MASK) >>
 228                    CPPI5_INFO1_DESC_PKTID_SHIFT;
 229         *flow_id = (desc_hdr->pkt_info1 & CPPI5_INFO1_DESC_FLOWID_MASK) >>
 230                     CPPI5_INFO1_DESC_FLOWID_SHIFT;
 231 }
 232
 233 /**
 234  * cppi5_desc_set_pktids - set Packet and Flow ids in Desc
 235  * @desc_hdr: packet/TR descriptor header
 236  * @pkt_id: Packet ID
 237  * @flow_id: Flow ID
 238  */
 239 static inline void cppi5_desc_set_pktids(struct cppi5_desc_hdr_t *desc_hdr,
 240                                          u32 pkt_id, u32 flow_id)
 241 {
 242         desc_hdr->pkt_info1 &= ~(CPPI5_INFO1_DESC_PKTID_MASK |
 243                                  CPPI5_INFO1_DESC_FLOWID_MASK);
 244         desc_hdr->pkt_info1 |= (pkt_id << CPPI5_INFO1_DESC_PKTID_SHIFT) &
 245                                 CPPI5_INFO1_DESC_PKTID_MASK;
 246         desc_hdr->pkt_info1 |= (flow_id << CPPI5_INFO1_DESC_FLOWID_SHIFT) &
 247                                 CPPI5_INFO1_DESC_FLOWID_MASK;
 248 }
 249
 250 /**
 251  * cppi5_desc_set_retpolicy - set Packet Return Policy in Desc
 252  * @desc_hdr: packet/TR descriptor header
 253  * @flags: fags, supported values
 254  *  CPPI5_INFO2_HDESC_RETPOLICY
 255  *  CPPI5_INFO2_HDESC_EARLYRET
 256  *  CPPI5_INFO2_DESC_RETPUSHPOLICY
 257  * @return_ring_id: Packet Return Queue/Ring id, value 0xFFFF reserved
 258  */
 259 static inline void cppi5_desc_set_retpolicy(struct cppi5_desc_hdr_t *desc_hdr,
 260                                             u32 flags, u32 return_ring_id)
 261 {
 262         desc_hdr->pkt_info2 &= ~(CPPI5_INFO2_DESC_RETP_MASK |
 263                                  CPPI5_INFO2_DESC_RETQ_MASK);
 264         desc_hdr->pkt_info2 |= flags & CPPI5_INFO2_DESC_RETP_MASK;
 265         desc_hdr->pkt_info2 |= return_ring_id & CPPI5_INFO2_DESC_RETQ_MASK;
 266 }
 267
 268 /**
 269  * cppi5_desc_get_tags_ids - get Packet Src/Dst Tags from Desc
 270  * @desc_hdr: packet/TR descriptor header
 271  * @src_tag_id: Source Tag
 272  * @dst_tag_id: Dest Tag
 273  *
 274  * Returns Packet Src/Dst Tags from packet/TR descriptor
 275  */
 276 static inline void cppi5_desc_get_tags_ids(struct cppi5_desc_hdr_t *desc_hdr,
 277                                            u32 *src_tag_id, u32 *dst_tag_id)
 278 {
 279         if (src_tag_id)
 280                 *src_tag_id = (desc_hdr->src_dst_tag &
 281                               CPPI5_INFO3_DESC_SRCTAG_MASK) >>
 282                               CPPI5_INFO3_DESC_SRCTAG_SHIFT;
 283         if (dst_tag_id)
 284                 *dst_tag_id = desc_hdr->src_dst_tag &
 285                               CPPI5_INFO3_DESC_DSTTAG_MASK;
 286 }
 287
 288 /**
 289  * cppi5_desc_set_tags_ids - set Packet Src/Dst Tags in HDesc
 290  * @desc_hdr: packet/TR descriptor header
 291  * @src_tag_id: Source Tag
 292  * @dst_tag_id: Dest Tag
 293  *
 294  * Returns Packet Src/Dst Tags from packet/TR descriptor
 295  */
 296 static inline void cppi5_desc_set_tags_ids(struct cppi5_desc_hdr_t *desc_hdr,
 297                                            u32 src_tag_id, u32 dst_tag_id)
 298 {
 299         desc_hdr->src_dst_tag = (src_tag_id << CPPI5_INFO3_DESC_SRCTAG_SHIFT) &
 300                                 CPPI5_INFO3_DESC_SRCTAG_MASK;
 301         desc_hdr->src_dst_tag |= dst_tag_id & CPPI5_INFO3_DESC_DSTTAG_MASK;
 302 }
 303
 304 /**
 305  * cppi5_hdesc_calc_size - Calculate Host Packet Descriptor size
 306  * @epib: is EPIB present
 307  * @psdata_size: PSDATA size
 308  * @sw_data_size: SWDATA size
 309  *
 310  * Returns required Host Packet Descriptor size
 311  * 0 - if PSDATA > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE
 312  */
 313 static inline u32 cppi5_hdesc_calc_size(bool epib, u32 psdata_size,
 314                                         u32 sw_data_size)
 315 {
 316         u32 desc_size;
 317
 318         if (psdata_size > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE)
 319                 return 0;
 320
 321         desc_size = sizeof(struct cppi5_host_desc_t) + psdata_size +
 322                     sw_data_size;
 323
 324         if (epib)
 325                 desc_size += CPPI5_INFO0_HDESC_EPIB_SIZE;
 326
 327         return ALIGN(desc_size, CPPI5_DESC_MIN_ALIGN);
 328 }
 329
 330 /**
 331  * cppi5_hdesc_init - Init Host Packet Descriptor size
 332  * @desc: Host packet descriptor
 333  * @flags: supported values
 334  *      CPPI5_INFO0_HDESC_EPIB_PRESENT
 335  *      CPPI5_INFO0_HDESC_PSINFO_LOCATION
 336  * @psdata_size: PSDATA size
 337  *
 338  * Returns required Host Packet Descriptor size
 339  * 0 - if PSDATA > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE
 340  */
 341 static inline void cppi5_hdesc_init(struct cppi5_host_desc_t *desc, u32 flags,
 342                                     u32 psdata_size)
 343 {
 344         desc->hdr.pkt_info0 = (CPPI5_INFO0_DESC_TYPE_VAL_HOST <<
 345                                CPPI5_INFO0_HDESC_TYPE_SHIFT) | (flags);
 346         desc->hdr.pkt_info0 |= ((psdata_size >> 2) <<
 347                                 CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT) &
 348                                 CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK;
 349         desc->next_desc = 0;
 350 }
 351
 352 /**
 353  * cppi5_hdesc_update_flags - Replace descriptor flags
 354  * @desc: Host packet descriptor
 355  * @flags: supported values
 356  *      CPPI5_INFO0_HDESC_EPIB_PRESENT
 357  *      CPPI5_INFO0_HDESC_PSINFO_LOCATION
 358  */
 359 static inline void cppi5_hdesc_update_flags(struct cppi5_host_desc_t *desc,
 360                                             u32 flags)
 361 {
 362         desc->hdr.pkt_info0 &= ~(CPPI5_INFO0_HDESC_EPIB_PRESENT |
 363                                  CPPI5_INFO0_HDESC_PSINFO_LOCATION);
 364         desc->hdr.pkt_info0 |= flags;
 365 }
 366
 367 /**
 368  * cppi5_hdesc_update_psdata_size - Replace PSdata size
 369  * @desc: Host packet descriptor
 370  * @psdata_size: PSDATA size
 371  */
 372 static inline void
 373 cppi5_hdesc_update_psdata_size(struct cppi5_host_desc_t *desc, u32 psdata_size)
 374 {
 375         desc->hdr.pkt_info0 &= ~CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK;
 376         desc->hdr.pkt_info0 |= ((psdata_size >> 2) <<
 377                                 CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT) &
 378                                 CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK;
 379 }
 380
 381 /**
 382  * cppi5_hdesc_get_psdata_size - get PSdata size in bytes
 383  * @desc: Host packet descriptor
 384  */
 385 static inline u32 cppi5_hdesc_get_psdata_size(struct cppi5_host_desc_t *desc)
 386 {
 387         u32 psdata_size = 0;
 388
 389         if (!(desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PSINFO_LOCATION))
 390                 psdata_size = (desc->hdr.pkt_info0 &
 391                                CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK) >>
 392                                CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT;
 393
 394         return (psdata_size << 2);
 395 }
 396
 397 /**
 398  * cppi5_hdesc_get_pktlen - get Packet Length from HDesc
 399  * @desc: Host packet descriptor
 400  *
 401  * Returns Packet Length from Host Packet Descriptor
 402  */
 403 static inline u32 cppi5_hdesc_get_pktlen(struct cppi5_host_desc_t *desc)
 404 {
 405         return (desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PKTLEN_MASK);
 406 }
 407
 408 /**
 409  * cppi5_hdesc_set_pktlen - set Packet Length in HDesc
 410  * @desc: Host packet descriptor
 411  */
 412 static inline void cppi5_hdesc_set_pktlen(struct cppi5_host_desc_t *desc,
 413                                           u32 pkt_len)
 414 {
 415         desc->hdr.pkt_info0 &= ~CPPI5_INFO0_HDESC_PKTLEN_MASK;
 416         desc->hdr.pkt_info0 |= (pkt_len & CPPI5_INFO0_HDESC_PKTLEN_MASK);
 417 }
 418
 419 /**
 420  * cppi5_hdesc_get_psflags - get Protocol Specific Flags from HDesc
 421  * @desc: Host packet descriptor
 422  *
 423  * Returns Protocol Specific Flags from Host Packet Descriptor
 424  */
 425 static inline u32 cppi5_hdesc_get_psflags(struct cppi5_host_desc_t *desc)
 426 {
 427         return (desc->hdr.pkt_info1 & CPPI5_INFO1_HDESC_PSFLGS_MASK) >>
 428                 CPPI5_INFO1_HDESC_PSFLGS_SHIFT;
 429 }
 430
 431 /**
 432  * cppi5_hdesc_set_psflags - set Protocol Specific Flags in HDesc
 433  * @desc: Host packet descriptor
 434  */
 435 static inline void cppi5_hdesc_set_psflags(struct cppi5_host_desc_t *desc,
 436                                            u32 ps_flags)
 437 {
 438         desc->hdr.pkt_info1 &= ~CPPI5_INFO1_HDESC_PSFLGS_MASK;
 439         desc->hdr.pkt_info1 |= (ps_flags <<
 440                                 CPPI5_INFO1_HDESC_PSFLGS_SHIFT) &
 441                                 CPPI5_INFO1_HDESC_PSFLGS_MASK;
 442 }
 443
 444 /**
 445  * cppi5_hdesc_get_errflags - get Packet Type from HDesc
 446  * @desc: Host packet descriptor
 447  */
 448 static inline u32 cppi5_hdesc_get_pkttype(struct cppi5_host_desc_t *desc)
 449 {
 450         return (desc->hdr.pkt_info2 & CPPI5_INFO2_HDESC_PKTTYPE_MASK) >>
 451                 CPPI5_INFO2_HDESC_PKTTYPE_SHIFT;
 452 }
 453
 454 /**
 455  * cppi5_hdesc_get_errflags - set Packet Type in HDesc
 456  * @desc: Host packet descriptor
 457  * @pkt_type: Packet Type
 458  */
 459 static inline void cppi5_hdesc_set_pkttype(struct cppi5_host_desc_t *desc,
 460                                            u32 pkt_type)
 461 {
 462         desc->hdr.pkt_info2 &= ~CPPI5_INFO2_HDESC_PKTTYPE_MASK;
 463         desc->hdr.pkt_info2 |=
 464                         (pkt_type << CPPI5_INFO2_HDESC_PKTTYPE_SHIFT) &
 465                          CPPI5_INFO2_HDESC_PKTTYPE_MASK;
 466 }
 467
 468 /**
 469  * cppi5_hdesc_attach_buf - attach buffer to HDesc
 470  * @desc: Host packet descriptor
 471  * @buf: Buffer physical address
 472  * @buf_data_len: Buffer length
 473  * @obuf: Original Buffer physical address
 474  * @obuf_len: Original Buffer length
 475  *
 476  * Attaches buffer to Host Packet Descriptor
 477  */
 478 static inline void cppi5_hdesc_attach_buf(struct cppi5_host_desc_t *desc,
 479                                           dma_addr_t buf, u32 buf_data_len,
 480                                           dma_addr_t obuf, u32 obuf_len)
 481 {
 482         desc->buf_ptr = buf;
 483         desc->buf_info1 = buf_data_len & CPPI5_BUFINFO1_HDESC_DATA_LEN_MASK;
 484         desc->org_buf_ptr = obuf;
 485         desc->org_buf_len = obuf_len & CPPI5_OBUFINFO0_HDESC_BUF_LEN_MASK;
 486 }
 487
 488 static inline void cppi5_hdesc_get_obuf(struct cppi5_host_desc_t *desc,
 489                                         dma_addr_t *obuf, u32 *obuf_len)
 490 {
 491         *obuf = desc->org_buf_ptr;
 492         *obuf_len = desc->org_buf_len & CPPI5_OBUFINFO0_HDESC_BUF_LEN_MASK;
 493 }
 494
 495 static inline void cppi5_hdesc_reset_to_original(struct cppi5_host_desc_t *desc)
 496 {
 497         desc->buf_ptr = desc->org_buf_ptr;
 498         desc->buf_info1 = desc->org_buf_len;
 499 }
 500
 501 /**
 502  * cppi5_hdesc_link_hbdesc - link Host Buffer Descriptor to HDesc
 503  * @desc: Host Packet Descriptor
 504  * @buf_desc: Host Buffer Descriptor physical address
 505  *
 506  * add and link Host Buffer Descriptor to HDesc
 507  */
 508 static inline void cppi5_hdesc_link_hbdesc(struct cppi5_host_desc_t *desc,
 509                                            dma_addr_t hbuf_desc)
 510 {
 511         desc->next_desc = hbuf_desc;
 512 }
 513
 514 static inline dma_addr_t
 515 cppi5_hdesc_get_next_hbdesc(struct cppi5_host_desc_t *desc)
 516 {
 517         return (dma_addr_t)desc->next_desc;
 518 }
 519
 520 static inline void cppi5_hdesc_reset_hbdesc(struct cppi5_host_desc_t *desc)
 521 {
 522         desc->hdr = (struct cppi5_desc_hdr_t) { 0 };
 523         desc->next_desc = 0;
 524 }
 525
 526 /**
 527  * cppi5_hdesc_epib_present -  check if EPIB present
 528  * @desc_hdr: packet descriptor/TR header
 529  *
 530  * Returns true if EPIB present in the packet
 531  */
 532 static inline bool cppi5_hdesc_epib_present(struct cppi5_desc_hdr_t *desc_hdr)
 533 {
 534         return !!(desc_hdr->pkt_info0 & CPPI5_INFO0_HDESC_EPIB_PRESENT);
 535 }
 536
 537 /**
 538  * cppi5_hdesc_get_psdata -  Get pointer on PSDATA
 539  * @desc: Host packet descriptor
 540  *
 541  * Returns pointer on PSDATA in HDesc.
 542  * NULL - if ps_data placed at the start of data buffer.
 543  */
 544 static inline void *cppi5_hdesc_get_psdata(struct cppi5_host_desc_t *desc)
 545 {
 546         u32 psdata_size;
 547         void *psdata;
 548
 549         if (desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PSINFO_LOCATION)
 550                 return NULL;
 551
 552         psdata_size = (desc->hdr.pkt_info0 &
 553                        CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK) >>
 554                        CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT;
 555
 556         if (!psdata_size)
 557                 return NULL;
 558
 559         psdata = &desc->epib;
 560
 561         if (cppi5_hdesc_epib_present(&desc->hdr))
 562                 psdata += CPPI5_INFO0_HDESC_EPIB_SIZE;
 563
 564         return psdata;
 565 }
 566
 567 /**
 568  * cppi5_hdesc_get_swdata -  Get pointer on swdata
 569  * @desc: Host packet descriptor
 570  *
 571  * Returns pointer on SWDATA in HDesc.
 572  * NOTE. It's caller responsibility to be sure hdesc actually has swdata.
 573  */
 574 static inline void *cppi5_hdesc_get_swdata(struct cppi5_host_desc_t *desc)
 575 {
 576         u32 psdata_size = 0;
 577         void *swdata;
 578
 579         if (!(desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PSINFO_LOCATION))
 580                 psdata_size = (desc->hdr.pkt_info0 &
 581                                CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK) >>
 582                                CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT;
 583
 584         swdata = &desc->epib;
 585
 586         if (cppi5_hdesc_epib_present(&desc->hdr))
 587                 swdata += CPPI5_INFO0_HDESC_EPIB_SIZE;
 588
 589         swdata += (psdata_size << 2);
 590
 591         return swdata;
 592 }
 593
 594 /* ================================== TR ================================== */
 595
 596 #define CPPI5_TR_TYPE_SHIFT                     (0U)
 597 #define CPPI5_TR_TYPE_MASK                      GENMASK(3, 0)
 598 #define CPPI5_TR_STATIC                         BIT(4)
 599 #define CPPI5_TR_WAIT                           BIT(5)
 600 #define CPPI5_TR_EVENT_SIZE_SHIFT               (6U)
 601 #define CPPI5_TR_EVENT_SIZE_MASK                GENMASK(7, 6)
 602 #define CPPI5_TR_TRIGGER0_SHIFT                 (8U)
 603 #define CPPI5_TR_TRIGGER0_MASK                  GENMASK(9, 8)
 604 #define CPPI5_TR_TRIGGER0_TYPE_SHIFT            (10U)
 605 #define CPPI5_TR_TRIGGER0_TYPE_MASK             GENMASK(11, 10)
 606 #define CPPI5_TR_TRIGGER1_SHIFT                 (12U)
 607 #define CPPI5_TR_TRIGGER1_MASK                  GENMASK(13, 12)
 608 #define CPPI5_TR_TRIGGER1_TYPE_SHIFT            (14U)
 609 #define CPPI5_TR_TRIGGER1_TYPE_MASK             GENMASK(15, 14)
 610 #define CPPI5_TR_CMD_ID_SHIFT                   (16U)
 611 #define CPPI5_TR_CMD_ID_MASK                    GENMASK(23, 16)
 612 #define CPPI5_TR_CSF_FLAGS_SHIFT                (24U)
 613 #define CPPI5_TR_CSF_FLAGS_MASK                 GENMASK(31, 24)
 614 #define   CPPI5_TR_CSF_SA_INDIRECT              BIT(0)
 615 #define   CPPI5_TR_CSF_DA_INDIRECT              BIT(1)
 616 #define   CPPI5_TR_CSF_SUPR_EVT                 BIT(2)
 617 #define   CPPI5_TR_CSF_EOL_ADV_SHIFT            (4U)
 618 #define   CPPI5_TR_CSF_EOL_ADV_MASK             GENMASK(6, 4)
 619 #define   CPPI5_TR_CSF_EOP                      BIT(7)
 620
 621 /**
 622  * enum cppi5_tr_types - TR types
 623  * @CPPI5_TR_TYPE0:     One dimensional data move
 624  * @CPPI5_TR_TYPE1:     Two dimensional data move
 625  * @CPPI5_TR_TYPE2:     Three dimensional data move
 626  * @CPPI5_TR_TYPE3:     Four dimensional data move
 627  * @CPPI5_TR_TYPE4:     Four dimensional data move with data formatting
 628  * @CPPI5_TR_TYPE5:     Four dimensional Cache Warm
 629  * @CPPI5_TR_TYPE8:     Four Dimensional Block Move
 630  * @CPPI5_TR_TYPE9:     Four Dimensional Block Move with Repacking
 631  * @CPPI5_TR_TYPE10:    Two Dimensional Block Move
 632  * @CPPI5_TR_TYPE11:    Two Dimensional Block Move with Repacking
 633  * @CPPI5_TR_TYPE15:    Four Dimensional Block Move with Repacking and
 634  *                      Indirection
 635  */
 636 enum cppi5_tr_types {
 637         CPPI5_TR_TYPE0 = 0,
 638         CPPI5_TR_TYPE1,
 639         CPPI5_TR_TYPE2,
 640         CPPI5_TR_TYPE3,
 641         CPPI5_TR_TYPE4,
 642         CPPI5_TR_TYPE5,
 643         /* type6-7: Reserved */
 644         CPPI5_TR_TYPE8 = 8,
 645         CPPI5_TR_TYPE9,
 646         CPPI5_TR_TYPE10,
 647         CPPI5_TR_TYPE11,
 648         /* type12-14: Reserved */
 649         CPPI5_TR_TYPE15 = 15,
 650         CPPI5_TR_TYPE_MAX
 651 };
 652
 653 /**
 654  * enum cppi5_tr_event_size - TR Flags EVENT_SIZE field specifies when an event
 655  *                            is generated for each TR.
 656  * @CPPI5_TR_EVENT_SIZE_COMPLETION:     When TR is complete and all status for
 657  *                                      the TR has been received
 658  * @CPPI5_TR_EVENT_SIZE_ICNT1_DEC:      Type 0: when the last data transaction
 659  *                                      is sent for the TR
 660  *                                      Type 1-11: when ICNT1 is decremented
 661  * @CPPI5_TR_EVENT_SIZE_ICNT2_DEC:      Type 0-1,10-11: when the last data
 662  *                                      transaction is sent for the TR
 663  *                                      All other types: when ICNT2 is
 664  *                                      decremented
 665  * @CPPI5_TR_EVENT_SIZE_ICNT3_DEC:      Type 0-2,10-11: when the last data
 666  *                                      transaction is sent for the TR
 667  *                                      All other types: when ICNT3 is
 668  *                                      decremented
 669  */
 670 enum cppi5_tr_event_size {
 671         CPPI5_TR_EVENT_SIZE_COMPLETION,
 672         CPPI5_TR_EVENT_SIZE_ICNT1_DEC,
 673         CPPI5_TR_EVENT_SIZE_ICNT2_DEC,
 674         CPPI5_TR_EVENT_SIZE_ICNT3_DEC,
 675         CPPI5_TR_EVENT_SIZE_MAX
 676 };
 677
 678 /**
 679  * enum cppi5_tr_trigger - TR Flags TRIGGERx field specifies the type of trigger
 680  *                         used to enable the TR to transfer data as specified
 681  *                         by TRIGGERx_TYPE field.
 682  * @CPPI5_TR_TRIGGER_NONE:              No trigger
 683  * @CPPI5_TR_TRIGGER_GLOBAL0:           Global trigger 0
 684  * @CPPI5_TR_TRIGGER_GLOBAL1:           Global trigger 1
 685  * @CPPI5_TR_TRIGGER_LOCAL_EVENT:       Local Event
 686  */
 687 enum cppi5_tr_trigger {
 688         CPPI5_TR_TRIGGER_NONE,
 689         CPPI5_TR_TRIGGER_GLOBAL0,
 690         CPPI5_TR_TRIGGER_GLOBAL1,
 691         CPPI5_TR_TRIGGER_LOCAL_EVENT,
 692         CPPI5_TR_TRIGGER_MAX
 693 };
 694
 695 /**
 696  * enum cppi5_tr_trigger_type - TR Flags TRIGGERx_TYPE field specifies the type
 697  *                              of data transfer that will be enabled by
 698  *                              receiving a trigger as specified by TRIGGERx.
 699  * @CPPI5_TR_TRIGGER_TYPE_ICNT1_DEC:    The second inner most loop (ICNT1) will
 700  *                                      be decremented by 1
 701  * @CPPI5_TR_TRIGGER_TYPE_ICNT2_DEC:    The third inner most loop (ICNT2) will
 702  *                                      be decremented by 1
 703  * @CPPI5_TR_TRIGGER_TYPE_ICNT3_DEC:    The outer most loop (ICNT3) will be
 704  *                                      decremented by 1
 705  * @CPPI5_TR_TRIGGER_TYPE_ALL:          The entire TR will be allowed to
 706  *                                      complete
 707  */
 708 enum cppi5_tr_trigger_type {
 709         CPPI5_TR_TRIGGER_TYPE_ICNT1_DEC,
 710         CPPI5_TR_TRIGGER_TYPE_ICNT2_DEC,
 711         CPPI5_TR_TRIGGER_TYPE_ICNT3_DEC,
 712         CPPI5_TR_TRIGGER_TYPE_ALL,
 713         CPPI5_TR_TRIGGER_TYPE_MAX
 714 };
 715
 716 typedef u32 cppi5_tr_flags_t;
 717
 718 /**
 719  * struct cppi5_tr_type0_t - Type 0 (One dimensional data move) TR (16 byte)
 720  * @flags:              TR flags (type, triggers, event, configuration)
 721  * @icnt0:              Total loop iteration count for level 0 (innermost)
 722  * @_reserved:          Not used
 723  * @addr:               Starting address for the source data or destination data
 724  */
 725 struct cppi5_tr_type0_t {
 726         cppi5_tr_flags_t flags;
 727         u16 icnt0;
 728         u16 _reserved;
 729         u64 addr;
 730 } __aligned(16) __packed;
 731
 732 /**
 733  * struct cppi5_tr_type1_t - Type 1 (Two dimensional data move) TR (32 byte)
 734  * @flags:              TR flags (type, triggers, event, configuration)
 735  * @icnt0:              Total loop iteration count for level 0 (innermost)
 736  * @icnt1:              Total loop iteration count for level 1
 737  * @addr:               Starting address for the source data or destination data
 738  * @dim1:               Signed dimension for loop level 1
 739  */
 740 struct cppi5_tr_type1_t {
 741         cppi5_tr_flags_t flags;
 742         u16 icnt0;
 743         u16 icnt1;
 744         u64 addr;
 745         s32 dim1;
 746 } __aligned(32) __packed;
 747
 748 /**
 749  * struct cppi5_tr_type2_t - Type 2 (Three dimensional data move) TR (32 byte)
 750  * @flags:              TR flags (type, triggers, event, configuration)
 751  * @icnt0:              Total loop iteration count for level 0 (innermost)
 752  * @icnt1:              Total loop iteration count for level 1
 753  * @addr:               Starting address for the source data or destination data
 754  * @dim1:               Signed dimension for loop level 1
 755  * @icnt2:              Total loop iteration count for level 2
 756  * @_reserved:          Not used
 757  * @dim2:               Signed dimension for loop level 2
 758  */
 759 struct cppi5_tr_type2_t {
 760         cppi5_tr_flags_t flags;
 761         u16 icnt0;
 762         u16 icnt1;
 763         u64 addr;
 764         s32 dim1;
 765         u16 icnt2;
 766         u16 _reserved;
 767         s32 dim2;
 768 } __aligned(32) __packed;
 769
 770 /**
 771  * struct cppi5_tr_type3_t - Type 3 (Four dimensional data move) TR (32 byte)
 772  * @flags:              TR flags (type, triggers, event, configuration)
 773  * @icnt0:              Total loop iteration count for level 0 (innermost)
 774  * @icnt1:              Total loop iteration count for level 1
 775  * @addr:               Starting address for the source data or destination data
 776  * @dim1:               Signed dimension for loop level 1
 777  * @icnt2:              Total loop iteration count for level 2
 778  * @icnt3:              Total loop iteration count for level 3 (outermost)
 779  * @dim2:               Signed dimension for loop level 2
 780  * @dim3:               Signed dimension for loop level 3
 781  */
 782 struct cppi5_tr_type3_t {
 783         cppi5_tr_flags_t flags;
 784         u16 icnt0;
 785         u16 icnt1;
 786         u64 addr;
 787         s32 dim1;
 788         u16 icnt2;
 789         u16 icnt3;
 790         s32 dim2;
 791         s32 dim3;
 792 } __aligned(32) __packed;
 793
 794 /**
 795  * struct cppi5_tr_type15_t - Type 15 (Four Dimensional Block Copy with
 796  *                            Repacking and Indirection Support) TR (64 byte)
 797  * @flags:              TR flags (type, triggers, event, configuration)
 798  * @icnt0:              Total loop iteration count for level 0 (innermost) for
 799  *                      source
 800  * @icnt1:              Total loop iteration count for level 1 for source
 801  * @addr:               Starting address for the source data
 802  * @dim1:               Signed dimension for loop level 1 for source
 803  * @icnt2:              Total loop iteration count for level 2 for source
 804  * @icnt3:              Total loop iteration count for level 3 (outermost) for
 805  *                      source
 806  * @dim2:               Signed dimension for loop level 2 for source
 807  * @dim3:               Signed dimension for loop level 3 for source
 808  * @_reserved:          Not used
 809  * @ddim1:              Signed dimension for loop level 1 for destination
 810  * @daddr:              Starting address for the destination data
 811  * @ddim2:              Signed dimension for loop level 2 for destination
 812  * @ddim3:              Signed dimension for loop level 3 for destination
 813  * @dicnt0:             Total loop iteration count for level 0 (innermost) for
 814  *                      destination
 815  * @dicnt1:             Total loop iteration count for level 1 for destination
 816  * @dicnt2:             Total loop iteration count for level 2 for destination
 817  * @sicnt3:             Total loop iteration count for level 3 (outermost) for
 818  *                      destination
 819  */
 820 struct cppi5_tr_type15_t {
 821         cppi5_tr_flags_t flags;
 822         u16 icnt0;
 823         u16 icnt1;
 824         u64 addr;
 825         s32 dim1;
 826         u16 icnt2;
 827         u16 icnt3;
 828         s32 dim2;
 829         s32 dim3;
 830         u32 _reserved;
 831         s32 ddim1;
 832         u64 daddr;
 833         s32 ddim2;
 834         s32 ddim3;
 835         u16 dicnt0;
 836         u16 dicnt1;
 837         u16 dicnt2;
 838         u16 dicnt3;
 839 } __aligned(64) __packed;
 840
 841 /**
 842  * struct cppi5_tr_resp_t - TR response record
 843  * @status:             Status type and info
 844  * @_reserved:          Not used
 845  * @cmd_id:             Command ID for the TR for TR identification
 846  * @flags:              Configuration Specific Flags
 847  */
 848 struct cppi5_tr_resp_t {
 849         u8 status;
 850         u8 _reserved;
 851         u8 cmd_id;
 852         u8 flags;
 853 } __packed;
 854
 855 #define CPPI5_TR_RESPONSE_STATUS_TYPE_SHIFT     (0U)
 856 #define CPPI5_TR_RESPONSE_STATUS_TYPE_MASK      GENMASK(3, 0)
 857 #define CPPI5_TR_RESPONSE_STATUS_INFO_SHIFT     (4U)
 858 #define CPPI5_TR_RESPONSE_STATUS_INFO_MASK      GENMASK(7, 4)
 859 #define CPPI5_TR_RESPONSE_CMDID_SHIFT           (16U)
 860 #define CPPI5_TR_RESPONSE_CMDID_MASK            GENMASK(23, 16)
 861 #define CPPI5_TR_RESPONSE_CFG_SPECIFIC_SHIFT    (24U)
 862 #define CPPI5_TR_RESPONSE_CFG_SPECIFIC_MASK     GENMASK(31, 24)
 863
 864 /**
 865  * enum cppi5_tr_resp_status_type - TR Response Status Type field is used to
 866  *                                  determine what type of status is being
 867  *                                  returned.
 868  * @CPPI5_TR_RESPONSE_STATUS_NONE:              No error, completion: completed
 869  * @CPPI5_TR_RESPONSE_STATUS_TRANSFER_ERR:      Transfer Error, completion: none
 870  *                                              or partially completed
 871  * @CPPI5_TR_RESPONSE_STATUS_ABORTED_ERR:       Aborted Error, completion: none
 872  *                                              or partially completed
 873  * @CPPI5_TR_RESPONSE_STATUS_SUBMISSION_ERR:    Submission Error, completion:
 874  *                                              none
 875  * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_ERR:   Unsupported Error, completion:
 876  *                                              none
 877  * @CPPI5_TR_RESPONSE_STATUS_TRANSFER_EXCEPTION: Transfer Exception, completion:
 878  *                                              partially completed
 879  * @CPPI5_TR_RESPONSE_STATUS__TEARDOWN_FLUSH:   Teardown Flush, completion: none
 880  */
 881 enum cppi5_tr_resp_status_type {
 882         CPPI5_TR_RESPONSE_STATUS_NONE,
 883         CPPI5_TR_RESPONSE_STATUS_TRANSFER_ERR,
 884         CPPI5_TR_RESPONSE_STATUS_ABORTED_ERR,
 885         CPPI5_TR_RESPONSE_STATUS_SUBMISSION_ERR,
 886         CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_ERR,
 887         CPPI5_TR_RESPONSE_STATUS_TRANSFER_EXCEPTION,
 888         CPPI5_TR_RESPONSE_STATUS__TEARDOWN_FLUSH,
 889         CPPI5_TR_RESPONSE_STATUS_MAX
 890 };
 891
 892 /**
 893  * enum cppi5_tr_resp_status_submission - TR Response Status field values which
 894  *                                        corresponds Submission Error
 895  * @CPPI5_TR_RESPONSE_STATUS_SUBMISSION_ICNT0:  ICNT0 was 0
 896  * @CPPI5_TR_RESPONSE_STATUS_SUBMISSION_FIFO_FULL: Channel FIFO was full when TR
 897  *                                              received
 898  * @CPPI5_TR_RESPONSE_STATUS_SUBMISSION_OWN:    Channel is not owned by the
 899  *                                              submitter
 900  */
 901 enum cppi5_tr_resp_status_submission {
 902         CPPI5_TR_RESPONSE_STATUS_SUBMISSION_ICNT0,
 903         CPPI5_TR_RESPONSE_STATUS_SUBMISSION_FIFO_FULL,
 904         CPPI5_TR_RESPONSE_STATUS_SUBMISSION_OWN,
 905         CPPI5_TR_RESPONSE_STATUS_SUBMISSION_MAX
 906 };
 907
 908 /**
 909  * enum cppi5_tr_resp_status_unsupported - TR Response Status field values which
 910  *                                         corresponds Unsupported Error
 911  * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_TR_TYPE:       TR Type not supported
 912  * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_STATIC:        STATIC not supported
 913  * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_EOL:           EOL not supported
 914  * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_CFG_SPECIFIC:  CONFIGURATION SPECIFIC
 915  *                                                      not supported
 916  * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_AMODE:         AMODE not supported
 917  * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_ELTYPE:        ELTYPE not supported
 918  * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_DFMT:          DFMT not supported
 919  * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_SECTR:         SECTR not supported
 920  * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_AMODE_SPECIFIC: AMODE SPECIFIC field
 921  *                                                      not supported
 922  */
 923 enum cppi5_tr_resp_status_unsupported {
 924         CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_TR_TYPE,
 925         CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_STATIC,
 926         CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_EOL,
 927         CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_CFG_SPECIFIC,
 928         CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_AMODE,
 929         CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_ELTYPE,
 930         CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_DFMT,
 931         CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_SECTR,
 932         CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_AMODE_SPECIFIC,
 933         CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_MAX
 934 };
 935
 936 /**
 937  * cppi5_trdesc_calc_size - Calculate TR Descriptor size
 938  * @tr_count: number of TR records
 939  * @tr_size: Nominal size of TR record (max) [16, 32, 64, 128]
 940  *
 941  * Returns required TR Descriptor size
 942  */
 943 static inline size_t cppi5_trdesc_calc_size(u32 tr_count, u32 tr_size)
 944 {
 945         /*
 946          * The Size of a TR descriptor is:
 947          * 1 x tr_size : the first 16 bytes is used by the packet info block +
 948          * tr_count x tr_size : Transfer Request Records +
 949          * tr_count x sizeof(struct cppi5_tr_resp_t) : Transfer Response Records
 950          */
 951         return tr_size * (tr_count + 1) +
 952                 sizeof(struct cppi5_tr_resp_t) * tr_count;
 953 }
 954
 955 /**
 956  * cppi5_trdesc_init - Init TR Descriptor
 957  * @desc: TR Descriptor
 958  * @tr_count: number of TR records
 959  * @tr_size: Nominal size of TR record (max) [16, 32, 64, 128]
 960  * @reload_idx: Absolute index to jump to on the 2nd and following passes
 961  *              through the TR packet.
 962  * @reload_count: Number of times to jump from last entry to reload_idx. 0x1ff
 963  *                indicates infinite looping.
 964  *
 965  * Init TR Descriptor
 966  */
 967 static inline void cppi5_trdesc_init(struct cppi5_desc_hdr_t *desc_hdr,
 968                                      u32 tr_count, u32 tr_size, u32 reload_idx,
 969                                      u32 reload_count)
 970 {
 971         desc_hdr->pkt_info0 = CPPI5_INFO0_DESC_TYPE_VAL_TR <<
 972                               CPPI5_INFO0_HDESC_TYPE_SHIFT;
 973         desc_hdr->pkt_info0 |=
 974                         (reload_count << CPPI5_INFO0_TRDESC_RLDCNT_SHIFT) &
 975                         CPPI5_INFO0_TRDESC_RLDCNT_MASK;
 976         desc_hdr->pkt_info0 |=
 977                         (reload_idx << CPPI5_INFO0_TRDESC_RLDIDX_SHIFT) &
 978                         CPPI5_INFO0_TRDESC_RLDIDX_MASK;
 979         desc_hdr->pkt_info0 |= (tr_count - 1) & CPPI5_INFO0_TRDESC_LASTIDX_MASK;
 980
 981         desc_hdr->pkt_info1 |= ((ffs(tr_size >> 4) - 1) <<
 982                                 CPPI5_INFO1_TRDESC_RECSIZE_SHIFT) &
 983                                 CPPI5_INFO1_TRDESC_RECSIZE_MASK;
 984 }
 985
 986 /**
 987  * cppi5_tr_init - Init TR record
 988  * @flags: Pointer to the TR's flags
 989  * @type: TR type
 990  * @static_tr: TR is static
 991  * @wait: Wait for TR completion before allow the next TR to start
 992  * @event_size: output event generation cfg
 993  * @cmd_id: TR identifier (application specifics)
 994  *
 995  * Init TR record
 996  */
 997 static inline void cppi5_tr_init(cppi5_tr_flags_t *flags,
 998                                  enum cppi5_tr_types type, bool static_tr,
 999                                  bool wait, enum cppi5_tr_event_size event_size,
1000                                  u32 cmd_id)
1001 {
1002         *flags = type;
1003         *flags |= (event_size << CPPI5_TR_EVENT_SIZE_SHIFT) &
1004                   CPPI5_TR_EVENT_SIZE_MASK;
1005
1006         *flags |= (cmd_id << CPPI5_TR_CMD_ID_SHIFT) &
1007                   CPPI5_TR_CMD_ID_MASK;
1008
1009         if (static_tr && (type == CPPI5_TR_TYPE8 || type == CPPI5_TR_TYPE9))
1010                 *flags |= CPPI5_TR_STATIC;
1011
1012         if (wait)
1013                 *flags |= CPPI5_TR_WAIT;
1014 }
1015
1016 /**
1017  * cppi5_tr_set_trigger - Configure trigger0/1 and trigger0/1_type
1018  * @flags: Pointer to the TR's flags
1019  * @trigger0: trigger0 selection
1020  * @trigger0_type: type of data transfer that will be enabled by trigger0
1021  * @trigger1: trigger1 selection
1022  * @trigger1_type: type of data transfer that will be enabled by trigger1
1023  *
1024  * Configure the triggers for the TR
1025  */
1026 static inline void cppi5_tr_set_trigger(cppi5_tr_flags_t *flags,
1027                 enum cppi5_tr_trigger trigger0,
1028                 enum cppi5_tr_trigger_type trigger0_type,
1029                 enum cppi5_tr_trigger trigger1,
1030                 enum cppi5_tr_trigger_type trigger1_type)
1031 {
1032         *flags &= ~(CPPI5_TR_TRIGGER0_MASK | CPPI5_TR_TRIGGER0_TYPE_MASK |
1033                     CPPI5_TR_TRIGGER1_MASK | CPPI5_TR_TRIGGER1_TYPE_MASK);
1034         *flags |= (trigger0 << CPPI5_TR_TRIGGER0_SHIFT) &
1035                   CPPI5_TR_TRIGGER0_MASK;
1036         *flags |= (trigger0_type << CPPI5_TR_TRIGGER0_TYPE_SHIFT) &
1037                   CPPI5_TR_TRIGGER0_TYPE_MASK;
1038
1039         *flags |= (trigger1 << CPPI5_TR_TRIGGER1_SHIFT) &
1040                   CPPI5_TR_TRIGGER1_MASK;
1041         *flags |= (trigger1_type << CPPI5_TR_TRIGGER1_TYPE_SHIFT) &
1042                   CPPI5_TR_TRIGGER1_TYPE_MASK;
1043 }
1044
1045 /**
1046  * cppi5_tr_cflag_set - Update the Configuration specific flags
1047  * @flags: Pointer to the TR's flags
1048  * @csf: Configuration specific flags
1049  *
1050  * Set a bit in Configuration Specific Flags section of the TR flags.
1051  */
1052 static inline void cppi5_tr_csf_set(cppi5_tr_flags_t *flags, u32 csf)
1053 {
1054         *flags &= ~CPPI5_TR_CSF_FLAGS_MASK;
1055         *flags |= (csf << CPPI5_TR_CSF_FLAGS_SHIFT) &
1056                   CPPI5_TR_CSF_FLAGS_MASK;
1057 }
1058
1059 #endif /* __TI_CPPI5_H__ */