1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare eDMA core driver
6 * Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
12 #include <linux/device.h>
13 #include <linux/dmaengine.h>
15 #define EDMA_MAX_WR_CH 8
16 #define EDMA_MAX_RD_CH 8
20 struct dw_edma_region {
26 struct dw_edma_core_ops {
27 int (*irq_vector)(struct device *dev, unsigned int nr);
30 enum dw_edma_map_format {
31 EDMA_MF_EDMA_LEGACY = 0x0,
32 EDMA_MF_EDMA_UNROLL = 0x1,
33 EDMA_MF_HDMA_COMPAT = 0x5
37 * struct dw_edma_chip - representation of DesignWare eDMA controller hardware
38 * @dev: struct device of the eDMA controller
40 * @nr_irqs: total number of DMA IRQs
41 * @ops DMA channel to IRQ number mapping
42 * @reg_base DMA register base address
43 * @ll_wr_cnt DMA write link list count
44 * @ll_rd_cnt DMA read link list count
45 * @rg_region DMA register region
46 * @ll_region_wr DMA descriptor link list memory for write channel
47 * @ll_region_rd DMA descriptor link list memory for read channel
48 * @dt_region_wr DMA data memory for write channel
49 * @dt_region_rd DMA data memory for read channel
50 * @mf DMA register map format
51 * @dw: struct dw_edma that is filled by dw_edma_probe()
57 const struct dw_edma_core_ops *ops;
59 void __iomem *reg_base;
63 /* link list address */
64 struct dw_edma_region ll_region_wr[EDMA_MAX_WR_CH];
65 struct dw_edma_region ll_region_rd[EDMA_MAX_RD_CH];
68 struct dw_edma_region dt_region_wr[EDMA_MAX_WR_CH];
69 struct dw_edma_region dt_region_rd[EDMA_MAX_RD_CH];
71 enum dw_edma_map_format mf;
76 /* Export to the platform drivers */
77 #if IS_ENABLED(CONFIG_DW_EDMA)
78 int dw_edma_probe(struct dw_edma_chip *chip);
79 int dw_edma_remove(struct dw_edma_chip *chip);
81 static inline int dw_edma_probe(struct dw_edma_chip *chip)
86 static inline int dw_edma_remove(struct dw_edma_chip *chip)
90 #endif /* CONFIG_DW_EDMA */
92 #endif /* _DW_EDMA_H */