1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
9 #include <test/export.h>
11 #define K210_PLL_CLKR GENMASK(3, 0)
12 #define K210_PLL_CLKF GENMASK(9, 4)
13 #define K210_PLL_CLKOD GENMASK(13, 10) /* Output Divider */
14 #define K210_PLL_BWADJ GENMASK(19, 14) /* BandWidth Adjust */
15 #define K210_PLL_RESET BIT(20)
16 #define K210_PLL_PWRD BIT(21) /* PoWeReD */
17 #define K210_PLL_INTFB BIT(22) /* Internal FeedBack */
18 #define K210_PLL_BYPASS BIT(23)
19 #define K210_PLL_TEST BIT(24)
20 #define K210_PLL_EN BIT(25)
21 #define K210_PLL_TEST_EN BIT(26)
23 #define K210_PLL_LOCK 0
24 #define K210_PLL_CLEAR_SLIP 2
25 #define K210_PLL_TEST_OUT 3
29 void __iomem *reg; /* Base PLL register */
30 void __iomem *lock; /* Common PLL lock register */
31 u8 shift; /* Offset of bits in lock register */
32 u8 width; /* Width of lock bits to test against */
35 #define to_k210_pll(_clk) container_of(_clk, struct k210_pll, clk)
37 struct k210_pll_config {
43 #ifdef CONFIG_UNIT_TEST
44 TEST_STATIC int k210_pll_calc_config(u32 rate, u32 rate_in,
45 struct k210_pll_config *best);
49 extern const struct clk_ops k210_pll_ops;
51 struct clk *k210_register_pll_struct(const char *name, const char *parent_name,
52 struct k210_pll *pll);
53 struct clk *k210_register_pll(const char *name, const char *parent_name,
54 void __iomem *reg, void __iomem *lock, u8 shift,
57 #endif /* K210_PLL_H */