include/imx_lpi2c.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductors, Inc.
   4  *
   5  * I2CLP driver for i.MX
   6  *
   7  */
   8 #ifndef __IMX_LPI2C_H__
   9 #define __IMX_LPI2C_H__
  10
  11 struct imx_lpi2c_bus {
  12         int index;
  13         ulong base;
  14         ulong driver_data;
  15         int speed;
  16         struct i2c_pads_info *pads_info;
  17         struct udevice *bus;
  18 };
  19
  20 struct imx_lpi2c_reg {
  21         u32 verid;
  22         u32 param;
  23         u8  reserved_0[8];
  24         u32 mcr;
  25         u32 msr;
  26         u32 mier;
  27         u32 mder;
  28         u32 mcfgr0;
  29         u32 mcfgr1;
  30         u32 mcfgr2;
  31         u32 mcfgr3;
  32         u8  reserved_1[16];
  33         u32 mdmr;
  34         u8  reserved_2[4];
  35         u32 mccr0;
  36         u8  reserved_3[4];
  37         u32 mccr1;
  38         u8  reserved_4[4];
  39         u32 mfcr;
  40         u32 mfsr;
  41         u32 mtdr;
  42         u8  reserved_5[12];
  43         u32 mrdr;
  44         u8  reserved_6[156];
  45         u32 scr;
  46         u32 ssr;
  47         u32 sier;
  48         u32 sder;
  49         u8  reserved_7[4];
  50         u32 scfgr1;
  51         u32 scfgr2;
  52         u8  reserved_8[20];
  53         u32 samr;
  54         u8  reserved_9[12];
  55         u32 sasr;
  56         u32 star;
  57         u8  reserved_10[8];
  58         u32 stdr;
  59         u8  reserved_11[12];
  60         u32 srdr;
  61 };
  62
  63 typedef enum lpi2c_status {
  64         LPI2C_SUCESS = 0,
  65         LPI2C_END_PACKET_ERR,
  66         LPI2C_STOP_ERR,
  67         LPI2C_NAK_ERR,
  68         LPI2C_ARB_LOST_ERR,
  69         LPI2C_FIFO_ERR,
  70         LPI2C_PIN_LOW_TIMEOUT_ERR,
  71         LPI2C_DATA_MATCH_ERR,
  72         LPI2C_BUSY,
  73         LPI2C_IDLE,
  74         LPI2C_BIT_ERR,
  75         LPI2C_NO_TRANS_PROG,
  76         LPI2C_DMA_REQ_FAIL,
  77 } lpi2c_status_t;
  78
  79 /* ----------------------------------------------------------------------------
  80    -- LPI2C Register Masks
  81    ---------------------------------------------------------------------------- */
  82
  83 /*!
  84  * @addtogroup LPI2C_Register_Masks LPI2C Register Masks
  85  * @{
  86  */
  87
  88 /*! @name VERID - Version ID Register */
  89 #define LPI2C_VERID_FEATURE_MASK                 (0xFFFFU)
  90 #define LPI2C_VERID_FEATURE_SHIFT                (0U)
  91 #define LPI2C_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
  92 #define LPI2C_VERID_MINOR_MASK                   (0xFF0000U)
  93 #define LPI2C_VERID_MINOR_SHIFT                  (16U)
  94 #define LPI2C_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
  95 #define LPI2C_VERID_MAJOR_MASK                   (0xFF000000U)
  96 #define LPI2C_VERID_MAJOR_SHIFT                  (24U)
  97 #define LPI2C_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
  98
  99 /*! @name PARAM - Parameter Register */
 100 #define LPI2C_PARAM_MTXFIFO_MASK                 (0xFU)
 101 #define LPI2C_PARAM_MTXFIFO_SHIFT                (0U)
 102 #define LPI2C_PARAM_MTXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
 103 #define LPI2C_PARAM_MRXFIFO_MASK                 (0xF00U)
 104 #define LPI2C_PARAM_MRXFIFO_SHIFT                (8U)
 105 #define LPI2C_PARAM_MRXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
 106
 107 /*! @name MCR - Master Control Register */
 108 #define LPI2C_MCR_MEN_MASK                       (0x1U)
 109 #define LPI2C_MCR_MEN_SHIFT                      (0U)
 110 #define LPI2C_MCR_MEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
 111 #define LPI2C_MCR_RST_MASK                       (0x2U)
 112 #define LPI2C_MCR_RST_SHIFT                      (1U)
 113 #define LPI2C_MCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
 114 #define LPI2C_MCR_DOZEN_MASK                     (0x4U)
 115 #define LPI2C_MCR_DOZEN_SHIFT                    (2U)
 116 #define LPI2C_MCR_DOZEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
 117 #define LPI2C_MCR_DBGEN_MASK                     (0x8U)
 118 #define LPI2C_MCR_DBGEN_SHIFT                    (3U)
 119 #define LPI2C_MCR_DBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
 120 #define LPI2C_MCR_RTF_MASK                       (0x100U)
 121 #define LPI2C_MCR_RTF_SHIFT                      (8U)
 122 #define LPI2C_MCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
 123 #define LPI2C_MCR_RRF_MASK                       (0x200U)
 124 #define LPI2C_MCR_RRF_SHIFT                      (9U)
 125 #define LPI2C_MCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
 126
 127 /*! @name MSR - Master Status Register */
 128 #define LPI2C_MSR_TDF_MASK                       (0x1U)
 129 #define LPI2C_MSR_TDF_SHIFT                      (0U)
 130 #define LPI2C_MSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
 131 #define LPI2C_MSR_RDF_MASK                       (0x2U)
 132 #define LPI2C_MSR_RDF_SHIFT                      (1U)
 133 #define LPI2C_MSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
 134 #define LPI2C_MSR_EPF_MASK                       (0x100U)
 135 #define LPI2C_MSR_EPF_SHIFT                      (8U)
 136 #define LPI2C_MSR_EPF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
 137 #define LPI2C_MSR_SDF_MASK                       (0x200U)
 138 #define LPI2C_MSR_SDF_SHIFT                      (9U)
 139 #define LPI2C_MSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
 140 #define LPI2C_MSR_NDF_MASK                       (0x400U)
 141 #define LPI2C_MSR_NDF_SHIFT                      (10U)
 142 #define LPI2C_MSR_NDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
 143 #define LPI2C_MSR_ALF_MASK                       (0x800U)
 144 #define LPI2C_MSR_ALF_SHIFT                      (11U)
 145 #define LPI2C_MSR_ALF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
 146 #define LPI2C_MSR_FEF_MASK                       (0x1000U)
 147 #define LPI2C_MSR_FEF_SHIFT                      (12U)
 148 #define LPI2C_MSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
 149 #define LPI2C_MSR_PLTF_MASK                      (0x2000U)
 150 #define LPI2C_MSR_PLTF_SHIFT                     (13U)
 151 #define LPI2C_MSR_PLTF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
 152 #define LPI2C_MSR_DMF_MASK                       (0x4000U)
 153 #define LPI2C_MSR_DMF_SHIFT                      (14U)
 154 #define LPI2C_MSR_DMF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
 155 #define LPI2C_MSR_MBF_MASK                       (0x1000000U)
 156 #define LPI2C_MSR_MBF_SHIFT                      (24U)
 157 #define LPI2C_MSR_MBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
 158 #define LPI2C_MSR_BBF_MASK                       (0x2000000U)
 159 #define LPI2C_MSR_BBF_SHIFT                      (25U)
 160 #define LPI2C_MSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
 161
 162 /*! @name MIER - Master Interrupt Enable Register */
 163 #define LPI2C_MIER_TDIE_MASK                     (0x1U)
 164 #define LPI2C_MIER_TDIE_SHIFT                    (0U)
 165 #define LPI2C_MIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
 166 #define LPI2C_MIER_RDIE_MASK                     (0x2U)
 167 #define LPI2C_MIER_RDIE_SHIFT                    (1U)
 168 #define LPI2C_MIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
 169 #define LPI2C_MIER_EPIE_MASK                     (0x100U)
 170 #define LPI2C_MIER_EPIE_SHIFT                    (8U)
 171 #define LPI2C_MIER_EPIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
 172 #define LPI2C_MIER_SDIE_MASK                     (0x200U)
 173 #define LPI2C_MIER_SDIE_SHIFT                    (9U)
 174 #define LPI2C_MIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
 175 #define LPI2C_MIER_NDIE_MASK                     (0x400U)
 176 #define LPI2C_MIER_NDIE_SHIFT                    (10U)
 177 #define LPI2C_MIER_NDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
 178 #define LPI2C_MIER_ALIE_MASK                     (0x800U)
 179 #define LPI2C_MIER_ALIE_SHIFT                    (11U)
 180 #define LPI2C_MIER_ALIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
 181 #define LPI2C_MIER_FEIE_MASK                     (0x1000U)
 182 #define LPI2C_MIER_FEIE_SHIFT                    (12U)
 183 #define LPI2C_MIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
 184 #define LPI2C_MIER_PLTIE_MASK                    (0x2000U)
 185 #define LPI2C_MIER_PLTIE_SHIFT                   (13U)
 186 #define LPI2C_MIER_PLTIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
 187 #define LPI2C_MIER_DMIE_MASK                     (0x4000U)
 188 #define LPI2C_MIER_DMIE_SHIFT                    (14U)
 189 #define LPI2C_MIER_DMIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
 190
 191 /*! @name MDER - Master DMA Enable Register */
 192 #define LPI2C_MDER_TDDE_MASK                     (0x1U)
 193 #define LPI2C_MDER_TDDE_SHIFT                    (0U)
 194 #define LPI2C_MDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
 195 #define LPI2C_MDER_RDDE_MASK                     (0x2U)
 196 #define LPI2C_MDER_RDDE_SHIFT                    (1U)
 197 #define LPI2C_MDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
 198
 199 /*! @name MCFGR0 - Master Configuration Register 0 */
 200 #define LPI2C_MCFGR0_HREN_MASK                   (0x1U)
 201 #define LPI2C_MCFGR0_HREN_SHIFT                  (0U)
 202 #define LPI2C_MCFGR0_HREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
 203 #define LPI2C_MCFGR0_HRPOL_MASK                  (0x2U)
 204 #define LPI2C_MCFGR0_HRPOL_SHIFT                 (1U)
 205 #define LPI2C_MCFGR0_HRPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
 206 #define LPI2C_MCFGR0_HRSEL_MASK                  (0x4U)
 207 #define LPI2C_MCFGR0_HRSEL_SHIFT                 (2U)
 208 #define LPI2C_MCFGR0_HRSEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
 209 #define LPI2C_MCFGR0_CIRFIFO_MASK                (0x100U)
 210 #define LPI2C_MCFGR0_CIRFIFO_SHIFT               (8U)
 211 #define LPI2C_MCFGR0_CIRFIFO(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
 212 #define LPI2C_MCFGR0_RDMO_MASK                   (0x200U)
 213 #define LPI2C_MCFGR0_RDMO_SHIFT                  (9U)
 214 #define LPI2C_MCFGR0_RDMO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
 215
 216 /*! @name MCFGR1 - Master Configuration Register 1 */
 217 #define LPI2C_MCFGR1_PRESCALE_MASK               (0x7U)
 218 #define LPI2C_MCFGR1_PRESCALE_SHIFT              (0U)
 219 #define LPI2C_MCFGR1_PRESCALE(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
 220 #define LPI2C_MCFGR1_AUTOSTOP_MASK               (0x100U)
 221 #define LPI2C_MCFGR1_AUTOSTOP_SHIFT              (8U)
 222 #define LPI2C_MCFGR1_AUTOSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
 223 #define LPI2C_MCFGR1_IGNACK_MASK                 (0x200U)
 224 #define LPI2C_MCFGR1_IGNACK_SHIFT                (9U)
 225 #define LPI2C_MCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
 226 #define LPI2C_MCFGR1_TIMECFG_MASK                (0x400U)
 227 #define LPI2C_MCFGR1_TIMECFG_SHIFT               (10U)
 228 #define LPI2C_MCFGR1_TIMECFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
 229 #define LPI2C_MCFGR1_MATCFG_MASK                 (0x70000U)
 230 #define LPI2C_MCFGR1_MATCFG_SHIFT                (16U)
 231 #define LPI2C_MCFGR1_MATCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
 232 #define LPI2C_MCFGR1_PINCFG_MASK                 (0x7000000U)
 233 #define LPI2C_MCFGR1_PINCFG_SHIFT                (24U)
 234 #define LPI2C_MCFGR1_PINCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
 235
 236 /*! @name MCFGR2 - Master Configuration Register 2 */
 237 #define LPI2C_MCFGR2_BUSIDLE_MASK                (0xFFFU)
 238 #define LPI2C_MCFGR2_BUSIDLE_SHIFT               (0U)
 239 #define LPI2C_MCFGR2_BUSIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
 240 #define LPI2C_MCFGR2_FILTSCL_MASK                (0xF0000U)
 241 #define LPI2C_MCFGR2_FILTSCL_SHIFT               (16U)
 242 #define LPI2C_MCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
 243 #define LPI2C_MCFGR2_FILTSDA_MASK                (0xF000000U)
 244 #define LPI2C_MCFGR2_FILTSDA_SHIFT               (24U)
 245 #define LPI2C_MCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
 246
 247 /*! @name MCFGR3 - Master Configuration Register 3 */
 248 #define LPI2C_MCFGR3_PINLOW_MASK                 (0xFFF00U)
 249 #define LPI2C_MCFGR3_PINLOW_SHIFT                (8U)
 250 #define LPI2C_MCFGR3_PINLOW(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
 251
 252 /*! @name MDMR - Master Data Match Register */
 253 #define LPI2C_MDMR_MATCH0_MASK                   (0xFFU)
 254 #define LPI2C_MDMR_MATCH0_SHIFT                  (0U)
 255 #define LPI2C_MDMR_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
 256 #define LPI2C_MDMR_MATCH1_MASK                   (0xFF0000U)
 257 #define LPI2C_MDMR_MATCH1_SHIFT                  (16U)
 258 #define LPI2C_MDMR_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
 259
 260 /*! @name MCCR0 - Master Clock Configuration Register 0 */
 261 #define LPI2C_MCCR0_CLKLO_MASK                   (0x3FU)
 262 #define LPI2C_MCCR0_CLKLO_SHIFT                  (0U)
 263 #define LPI2C_MCCR0_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
 264 #define LPI2C_MCCR0_CLKHI_MASK                   (0x3F00U)
 265 #define LPI2C_MCCR0_CLKHI_SHIFT                  (8U)
 266 #define LPI2C_MCCR0_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
 267 #define LPI2C_MCCR0_SETHOLD_MASK                 (0x3F0000U)
 268 #define LPI2C_MCCR0_SETHOLD_SHIFT                (16U)
 269 #define LPI2C_MCCR0_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
 270 #define LPI2C_MCCR0_DATAVD_MASK                  (0x3F000000U)
 271 #define LPI2C_MCCR0_DATAVD_SHIFT                 (24U)
 272 #define LPI2C_MCCR0_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
 273
 274 /*! @name MCCR1 - Master Clock Configuration Register 1 */
 275 #define LPI2C_MCCR1_CLKLO_MASK                   (0x3FU)
 276 #define LPI2C_MCCR1_CLKLO_SHIFT                  (0U)
 277 #define LPI2C_MCCR1_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
 278 #define LPI2C_MCCR1_CLKHI_MASK                   (0x3F00U)
 279 #define LPI2C_MCCR1_CLKHI_SHIFT                  (8U)
 280 #define LPI2C_MCCR1_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
 281 #define LPI2C_MCCR1_SETHOLD_MASK                 (0x3F0000U)
 282 #define LPI2C_MCCR1_SETHOLD_SHIFT                (16U)
 283 #define LPI2C_MCCR1_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
 284 #define LPI2C_MCCR1_DATAVD_MASK                  (0x3F000000U)
 285 #define LPI2C_MCCR1_DATAVD_SHIFT                 (24U)
 286 #define LPI2C_MCCR1_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
 287
 288 /*! @name MFCR - Master FIFO Control Register */
 289 #define LPI2C_MFCR_TXWATER_MASK                  (0xFFU)
 290 #define LPI2C_MFCR_TXWATER_SHIFT                 (0U)
 291 #define LPI2C_MFCR_TXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
 292 #define LPI2C_MFCR_RXWATER_MASK                  (0xFF0000U)
 293 #define LPI2C_MFCR_RXWATER_SHIFT                 (16U)
 294 #define LPI2C_MFCR_RXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
 295
 296 /*! @name MFSR - Master FIFO Status Register */
 297 #define LPI2C_MFSR_TXCOUNT_MASK                  (0xFFU)
 298 #define LPI2C_MFSR_TXCOUNT_SHIFT                 (0U)
 299 #define LPI2C_MFSR_TXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
 300 #define LPI2C_MFSR_RXCOUNT_MASK                  (0xFF0000U)
 301 #define LPI2C_MFSR_RXCOUNT_SHIFT                 (16U)
 302 #define LPI2C_MFSR_RXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
 303
 304 /*! @name MTDR - Master Transmit Data Register */
 305 #define LPI2C_MTDR_DATA_MASK                     (0xFFU)
 306 #define LPI2C_MTDR_DATA_SHIFT                    (0U)
 307 #define LPI2C_MTDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
 308 #define LPI2C_MTDR_CMD_MASK                      (0x700U)
 309 #define LPI2C_MTDR_CMD_SHIFT                     (8U)
 310 #define LPI2C_MTDR_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
 311
 312 /*! @name MRDR - Master Receive Data Register */
 313 #define LPI2C_MRDR_DATA_MASK                     (0xFFU)
 314 #define LPI2C_MRDR_DATA_SHIFT                    (0U)
 315 #define LPI2C_MRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
 316 #define LPI2C_MRDR_RXEMPTY_MASK                  (0x4000U)
 317 #define LPI2C_MRDR_RXEMPTY_SHIFT                 (14U)
 318 #define LPI2C_MRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
 319
 320 /*! @name SCR - Slave Control Register */
 321 #define LPI2C_SCR_SEN_MASK                       (0x1U)
 322 #define LPI2C_SCR_SEN_SHIFT                      (0U)
 323 #define LPI2C_SCR_SEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
 324 #define LPI2C_SCR_RST_MASK                       (0x2U)
 325 #define LPI2C_SCR_RST_SHIFT                      (1U)
 326 #define LPI2C_SCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
 327 #define LPI2C_SCR_FILTEN_MASK                    (0x10U)
 328 #define LPI2C_SCR_FILTEN_SHIFT                   (4U)
 329 #define LPI2C_SCR_FILTEN(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
 330 #define LPI2C_SCR_FILTDZ_MASK                    (0x20U)
 331 #define LPI2C_SCR_FILTDZ_SHIFT                   (5U)
 332 #define LPI2C_SCR_FILTDZ(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
 333 #define LPI2C_SCR_RTF_MASK                       (0x100U)
 334 #define LPI2C_SCR_RTF_SHIFT                      (8U)
 335 #define LPI2C_SCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
 336 #define LPI2C_SCR_RRF_MASK                       (0x200U)
 337 #define LPI2C_SCR_RRF_SHIFT                      (9U)
 338 #define LPI2C_SCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
 339
 340 /*! @name SSR - Slave Status Register */
 341 #define LPI2C_SSR_TDF_MASK                       (0x1U)
 342 #define LPI2C_SSR_TDF_SHIFT                      (0U)
 343 #define LPI2C_SSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
 344 #define LPI2C_SSR_RDF_MASK                       (0x2U)
 345 #define LPI2C_SSR_RDF_SHIFT                      (1U)
 346 #define LPI2C_SSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
 347 #define LPI2C_SSR_AVF_MASK                       (0x4U)
 348 #define LPI2C_SSR_AVF_SHIFT                      (2U)
 349 #define LPI2C_SSR_AVF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
 350 #define LPI2C_SSR_TAF_MASK                       (0x8U)
 351 #define LPI2C_SSR_TAF_SHIFT                      (3U)
 352 #define LPI2C_SSR_TAF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
 353 #define LPI2C_SSR_RSF_MASK                       (0x100U)
 354 #define LPI2C_SSR_RSF_SHIFT                      (8U)
 355 #define LPI2C_SSR_RSF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
 356 #define LPI2C_SSR_SDF_MASK                       (0x200U)
 357 #define LPI2C_SSR_SDF_SHIFT                      (9U)
 358 #define LPI2C_SSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
 359 #define LPI2C_SSR_BEF_MASK                       (0x400U)
 360 #define LPI2C_SSR_BEF_SHIFT                      (10U)
 361 #define LPI2C_SSR_BEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
 362 #define LPI2C_SSR_FEF_MASK                       (0x800U)
 363 #define LPI2C_SSR_FEF_SHIFT                      (11U)
 364 #define LPI2C_SSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
 365 #define LPI2C_SSR_AM0F_MASK                      (0x1000U)
 366 #define LPI2C_SSR_AM0F_SHIFT                     (12U)
 367 #define LPI2C_SSR_AM0F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
 368 #define LPI2C_SSR_AM1F_MASK                      (0x2000U)
 369 #define LPI2C_SSR_AM1F_SHIFT                     (13U)
 370 #define LPI2C_SSR_AM1F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
 371 #define LPI2C_SSR_GCF_MASK                       (0x4000U)
 372 #define LPI2C_SSR_GCF_SHIFT                      (14U)
 373 #define LPI2C_SSR_GCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
 374 #define LPI2C_SSR_SARF_MASK                      (0x8000U)
 375 #define LPI2C_SSR_SARF_SHIFT                     (15U)
 376 #define LPI2C_SSR_SARF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
 377 #define LPI2C_SSR_SBF_MASK                       (0x1000000U)
 378 #define LPI2C_SSR_SBF_SHIFT                      (24U)
 379 #define LPI2C_SSR_SBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
 380 #define LPI2C_SSR_BBF_MASK                       (0x2000000U)
 381 #define LPI2C_SSR_BBF_SHIFT                      (25U)
 382 #define LPI2C_SSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
 383
 384 /*! @name SIER - Slave Interrupt Enable Register */
 385 #define LPI2C_SIER_TDIE_MASK                     (0x1U)
 386 #define LPI2C_SIER_TDIE_SHIFT                    (0U)
 387 #define LPI2C_SIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
 388 #define LPI2C_SIER_RDIE_MASK                     (0x2U)
 389 #define LPI2C_SIER_RDIE_SHIFT                    (1U)
 390 #define LPI2C_SIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
 391 #define LPI2C_SIER_AVIE_MASK                     (0x4U)
 392 #define LPI2C_SIER_AVIE_SHIFT                    (2U)
 393 #define LPI2C_SIER_AVIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
 394 #define LPI2C_SIER_TAIE_MASK                     (0x8U)
 395 #define LPI2C_SIER_TAIE_SHIFT                    (3U)
 396 #define LPI2C_SIER_TAIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
 397 #define LPI2C_SIER_RSIE_MASK                     (0x100U)
 398 #define LPI2C_SIER_RSIE_SHIFT                    (8U)
 399 #define LPI2C_SIER_RSIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
 400 #define LPI2C_SIER_SDIE_MASK                     (0x200U)
 401 #define LPI2C_SIER_SDIE_SHIFT                    (9U)
 402 #define LPI2C_SIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
 403 #define LPI2C_SIER_BEIE_MASK                     (0x400U)
 404 #define LPI2C_SIER_BEIE_SHIFT                    (10U)
 405 #define LPI2C_SIER_BEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
 406 #define LPI2C_SIER_FEIE_MASK                     (0x800U)
 407 #define LPI2C_SIER_FEIE_SHIFT                    (11U)
 408 #define LPI2C_SIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
 409 #define LPI2C_SIER_AM0IE_MASK                    (0x1000U)
 410 #define LPI2C_SIER_AM0IE_SHIFT                   (12U)
 411 #define LPI2C_SIER_AM0IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
 412 #define LPI2C_SIER_AM1F_MASK                     (0x2000U)
 413 #define LPI2C_SIER_AM1F_SHIFT                    (13U)
 414 #define LPI2C_SIER_AM1F(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)
 415 #define LPI2C_SIER_GCIE_MASK                     (0x4000U)
 416 #define LPI2C_SIER_GCIE_SHIFT                    (14U)
 417 #define LPI2C_SIER_GCIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
 418 #define LPI2C_SIER_SARIE_MASK                    (0x8000U)
 419 #define LPI2C_SIER_SARIE_SHIFT                   (15U)
 420 #define LPI2C_SIER_SARIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
 421
 422 /*! @name SDER - Slave DMA Enable Register */
 423 #define LPI2C_SDER_TDDE_MASK                     (0x1U)
 424 #define LPI2C_SDER_TDDE_SHIFT                    (0U)
 425 #define LPI2C_SDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
 426 #define LPI2C_SDER_RDDE_MASK                     (0x2U)
 427 #define LPI2C_SDER_RDDE_SHIFT                    (1U)
 428 #define LPI2C_SDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
 429 #define LPI2C_SDER_AVDE_MASK                     (0x4U)
 430 #define LPI2C_SDER_AVDE_SHIFT                    (2U)
 431 #define LPI2C_SDER_AVDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
 432
 433 /*! @name SCFGR1 - Slave Configuration Register 1 */
 434 #define LPI2C_SCFGR1_ADRSTALL_MASK               (0x1U)
 435 #define LPI2C_SCFGR1_ADRSTALL_SHIFT              (0U)
 436 #define LPI2C_SCFGR1_ADRSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
 437 #define LPI2C_SCFGR1_RXSTALL_MASK                (0x2U)
 438 #define LPI2C_SCFGR1_RXSTALL_SHIFT               (1U)
 439 #define LPI2C_SCFGR1_RXSTALL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
 440 #define LPI2C_SCFGR1_TXDSTALL_MASK               (0x4U)
 441 #define LPI2C_SCFGR1_TXDSTALL_SHIFT              (2U)
 442 #define LPI2C_SCFGR1_TXDSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
 443 #define LPI2C_SCFGR1_ACKSTALL_MASK               (0x8U)
 444 #define LPI2C_SCFGR1_ACKSTALL_SHIFT              (3U)
 445 #define LPI2C_SCFGR1_ACKSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
 446 #define LPI2C_SCFGR1_GCEN_MASK                   (0x100U)
 447 #define LPI2C_SCFGR1_GCEN_SHIFT                  (8U)
 448 #define LPI2C_SCFGR1_GCEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
 449 #define LPI2C_SCFGR1_SAEN_MASK                   (0x200U)
 450 #define LPI2C_SCFGR1_SAEN_SHIFT                  (9U)
 451 #define LPI2C_SCFGR1_SAEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
 452 #define LPI2C_SCFGR1_TXCFG_MASK                  (0x400U)
 453 #define LPI2C_SCFGR1_TXCFG_SHIFT                 (10U)
 454 #define LPI2C_SCFGR1_TXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
 455 #define LPI2C_SCFGR1_RXCFG_MASK                  (0x800U)
 456 #define LPI2C_SCFGR1_RXCFG_SHIFT                 (11U)
 457 #define LPI2C_SCFGR1_RXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
 458 #define LPI2C_SCFGR1_IGNACK_MASK                 (0x1000U)
 459 #define LPI2C_SCFGR1_IGNACK_SHIFT                (12U)
 460 #define LPI2C_SCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
 461 #define LPI2C_SCFGR1_HSMEN_MASK                  (0x2000U)
 462 #define LPI2C_SCFGR1_HSMEN_SHIFT                 (13U)
 463 #define LPI2C_SCFGR1_HSMEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
 464 #define LPI2C_SCFGR1_ADDRCFG_MASK                (0x70000U)
 465 #define LPI2C_SCFGR1_ADDRCFG_SHIFT               (16U)
 466 #define LPI2C_SCFGR1_ADDRCFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
 467
 468 /*! @name SCFGR2 - Slave Configuration Register 2 */
 469 #define LPI2C_SCFGR2_CLKHOLD_MASK                (0xFU)
 470 #define LPI2C_SCFGR2_CLKHOLD_SHIFT               (0U)
 471 #define LPI2C_SCFGR2_CLKHOLD(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
 472 #define LPI2C_SCFGR2_DATAVD_MASK                 (0x3F00U)
 473 #define LPI2C_SCFGR2_DATAVD_SHIFT                (8U)
 474 #define LPI2C_SCFGR2_DATAVD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
 475 #define LPI2C_SCFGR2_FILTSCL_MASK                (0xF0000U)
 476 #define LPI2C_SCFGR2_FILTSCL_SHIFT               (16U)
 477 #define LPI2C_SCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
 478 #define LPI2C_SCFGR2_FILTSDA_MASK                (0xF000000U)
 479 #define LPI2C_SCFGR2_FILTSDA_SHIFT               (24U)
 480 #define LPI2C_SCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
 481
 482 /*! @name SAMR - Slave Address Match Register */
 483 #define LPI2C_SAMR_ADDR0_MASK                    (0x7FEU)
 484 #define LPI2C_SAMR_ADDR0_SHIFT                   (1U)
 485 #define LPI2C_SAMR_ADDR0(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
 486 #define LPI2C_SAMR_ADDR1_MASK                    (0x7FE0000U)
 487 #define LPI2C_SAMR_ADDR1_SHIFT                   (17U)
 488 #define LPI2C_SAMR_ADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
 489
 490 /*! @name SASR - Slave Address Status Register */
 491 #define LPI2C_SASR_RADDR_MASK                    (0x7FFU)
 492 #define LPI2C_SASR_RADDR_SHIFT                   (0U)
 493 #define LPI2C_SASR_RADDR(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
 494 #define LPI2C_SASR_ANV_MASK                      (0x4000U)
 495 #define LPI2C_SASR_ANV_SHIFT                     (14U)
 496 #define LPI2C_SASR_ANV(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
 497
 498 /*! @name STAR - Slave Transmit ACK Register */
 499 #define LPI2C_STAR_TXNACK_MASK                   (0x1U)
 500 #define LPI2C_STAR_TXNACK_SHIFT                  (0U)
 501 #define LPI2C_STAR_TXNACK(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
 502
 503 /*! @name STDR - Slave Transmit Data Register */
 504 #define LPI2C_STDR_DATA_MASK                     (0xFFU)
 505 #define LPI2C_STDR_DATA_SHIFT                    (0U)
 506 #define LPI2C_STDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
 507
 508 /*! @name SRDR - Slave Receive Data Register */
 509 #define LPI2C_SRDR_DATA_MASK                     (0xFFU)
 510 #define LPI2C_SRDR_DATA_SHIFT                    (0U)
 511 #define LPI2C_SRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
 512 #define LPI2C_SRDR_RXEMPTY_MASK                  (0x4000U)
 513 #define LPI2C_SRDR_RXEMPTY_SHIFT                 (14U)
 514 #define LPI2C_SRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
 515 #define LPI2C_SRDR_SOF_MASK                      (0x8000U)
 516 #define LPI2C_SRDR_SOF_SHIFT                     (15U)
 517 #define LPI2C_SRDR_SOF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
 518
 519 #endif /* __ASM_ARCH_IMX_I2C_H__ */