4 #include "qemu-common.h"
7 #include "exec/memory.h"
8 #include "sysemu/dma.h"
10 /* PCI includes legacy ISA access. */
11 #include "hw/isa/isa.h"
13 #include "hw/pci/pcie.h"
17 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
18 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
19 #define PCI_FUNC(devfn) ((devfn) & 0x07)
20 #define PCI_SLOT_MAX 32
21 #define PCI_FUNC_MAX 8
23 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
24 #include "hw/pci/pci_ids.h"
26 /* QEMU-specific Vendor and Device ID definitions */
29 #define PCI_DEVICE_ID_IBM_440GX 0x027f
30 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
32 /* Hitachi (0x1054) */
33 #define PCI_VENDOR_ID_HITACHI 0x1054
34 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
37 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010
38 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
39 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
40 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
41 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
43 /* Realtek (0x10ec) */
44 #define PCI_DEVICE_ID_REALTEK_8029 0x8029
47 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
49 /* Marvell (0x11ab) */
50 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
52 /* QEMU/Bochs VGA (0x1234) */
53 #define PCI_VENDOR_ID_QEMU 0x1234
54 #define PCI_DEVICE_ID_QEMU_VGA 0x1111
57 #define PCI_VENDOR_ID_VMWARE 0x15ad
58 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
59 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
60 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
61 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
62 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0
63 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
64 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0
67 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209
68 #define PCI_DEVICE_ID_INTEL_82557 0x1229
69 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922
71 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
72 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
73 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
74 #define PCI_SUBDEVICE_ID_QEMU 0x1100
76 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000
77 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
78 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
79 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
80 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004
81 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005
82 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009
84 #define PCI_DEVICE_ID_VIRTIO_GL 0x1006
87 #define PCI_VENDOR_ID_REDHAT 0x1b36
88 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001
89 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002
90 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003
91 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004
92 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005
93 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100
95 #define FMT_PCIBUS PRIx64
97 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
98 uint32_t address, uint32_t data, int len);
99 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
100 uint32_t address, int len);
101 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
102 pcibus_t addr, pcibus_t size, int type);
103 typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
105 typedef struct PCIIORegion {
106 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
107 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
110 MemoryRegion *memory;
111 MemoryRegion *address_space;
114 #define PCI_ROM_SLOT 6
115 #define PCI_NUM_REGIONS 7
121 QEMU_PCI_VGA_NUM_REGIONS,
124 #define QEMU_PCI_VGA_MEM_BASE 0xa0000
125 #define QEMU_PCI_VGA_MEM_SIZE 0x20000
126 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
127 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc
128 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
129 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20
131 #include "hw/pci/pci_regs.h"
133 /* PCI HEADER_TYPE */
134 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
136 /* Size of the standard PCI config header */
137 #define PCI_CONFIG_HEADER_SIZE 0x40
138 /* Size of the standard PCI config space */
139 #define PCI_CONFIG_SPACE_SIZE 0x100
140 /* Size of the standart PCIe config space: 4KB */
141 #define PCIE_CONFIG_SPACE_SIZE 0x1000
143 #define PCI_NUM_PINS 4 /* A-D */
145 /* Bits in cap_present field. */
147 QEMU_PCI_CAP_MSI = 0x1,
148 QEMU_PCI_CAP_MSIX = 0x2,
149 QEMU_PCI_CAP_EXPRESS = 0x4,
151 /* multifunction capable device */
152 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3
153 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
155 /* command register SERR bit enabled */
156 #define QEMU_PCI_CAP_SERR_BITNR 4
157 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
158 /* Standard hot plug controller. */
159 #define QEMU_PCI_SHPC_BITNR 5
160 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
161 #define QEMU_PCI_SLOTID_BITNR 6
162 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
165 #define TYPE_PCI_DEVICE "pci-device"
166 #define PCI_DEVICE(obj) \
167 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
168 #define PCI_DEVICE_CLASS(klass) \
169 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
170 #define PCI_DEVICE_GET_CLASS(obj) \
171 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
173 typedef struct PCIINTxRoute {
182 typedef struct PCIDeviceClass {
183 DeviceClass parent_class;
185 int (*init)(PCIDevice *dev);
186 PCIUnregisterFunc *exit;
187 PCIConfigReadFunc *config_read;
188 PCIConfigWriteFunc *config_write;
194 uint16_t subsystem_vendor_id; /* only for header type = 0 */
195 uint16_t subsystem_id; /* only for header type = 0 */
198 * pci-to-pci bridge or normal device.
199 * This doesn't mean pci host switch.
200 * When card bus bridge is supported, this would be enhanced.
205 int is_express; /* is this device pci express? */
207 /* device isn't hot-pluggable */
214 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
215 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
217 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
218 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
219 unsigned int vector_start,
220 unsigned int vector_end);
225 /* PCI config space */
228 /* Used to enable config checks on load. Note that writable bits are
229 * never checked even if set in cmask. */
232 /* Used to implement R/W bytes */
235 /* Used to implement RW1C(Write 1 to Clear) bytes */
238 /* Used to allocate config space for capabilities. */
241 /* the following fields are read only */
245 PCIIORegion io_regions[PCI_NUM_REGIONS];
246 AddressSpace bus_master_as;
247 MemoryRegion bus_master_enable_region;
250 /* do not access the following fields */
251 PCIConfigReadFunc *config_read;
252 PCIConfigWriteFunc *config_write;
254 /* IRQ objects for the INTA-INTD pins. */
257 /* Legacy PCI VGA regions */
258 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
261 /* Current IRQ levels. Used internally by the generic PCI code. */
264 /* Capability bits */
265 uint32_t cap_present;
267 /* Offset of MSI-X capability in config space */
273 /* Space to store MSIX table & pending bit array */
276 /* MemoryRegion container for msix exclusive BAR setup */
277 MemoryRegion msix_exclusive_bar;
278 /* Memory Regions for MSIX table and pending bit entries. */
279 MemoryRegion msix_table_mmio;
280 MemoryRegion msix_pba_mmio;
281 /* Reference-count for entries actually in use by driver. */
282 unsigned *msix_entry_used;
283 /* MSIX function mask set or MSIX disabled */
284 bool msix_function_masked;
285 /* Version id needed for VMState */
288 /* Offset of MSI capability in config space */
292 PCIExpressDevice exp;
297 /* Location of option rom */
303 /* INTx routing notifier */
304 PCIINTxRoutingNotifier intx_routing_notifier;
306 /* MSI-X notifiers */
307 MSIVectorUseNotifier msix_vector_use_notifier;
308 MSIVectorReleaseNotifier msix_vector_release_notifier;
309 MSIVectorPollNotifier msix_vector_poll_notifier;
312 void pci_register_bar(PCIDevice *pci_dev, int region_num,
313 uint8_t attr, MemoryRegion *memory);
314 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
315 MemoryRegion *io_lo, MemoryRegion *io_hi);
316 void pci_unregister_vga(PCIDevice *pci_dev);
317 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
319 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
320 uint8_t offset, uint8_t size);
322 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
324 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
327 uint32_t pci_default_read_config(PCIDevice *d,
328 uint32_t address, int len);
329 void pci_default_write_config(PCIDevice *d,
330 uint32_t address, uint32_t val, int len);
331 void pci_device_save(PCIDevice *s, QEMUFile *f);
332 int pci_device_load(PCIDevice *s, QEMUFile *f);
333 MemoryRegion *pci_address_space(PCIDevice *dev);
334 MemoryRegion *pci_address_space_io(PCIDevice *dev);
336 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
337 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
338 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
341 PCI_HOTPLUG_DISABLED,
343 PCI_COLDPLUG_ENABLED,
346 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev,
347 PCIHotplugState state);
349 #define TYPE_PCI_BUS "PCI"
350 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
351 #define TYPE_PCIE_BUS "PCIE"
353 bool pci_bus_is_express(PCIBus *bus);
354 bool pci_bus_is_root(PCIBus *bus);
355 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
357 MemoryRegion *address_space_mem,
358 MemoryRegion *address_space_io,
359 uint8_t devfn_min, const char *typename);
360 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
361 MemoryRegion *address_space_mem,
362 MemoryRegion *address_space_io,
363 uint8_t devfn_min, const char *typename);
364 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
365 void *irq_opaque, int nirq);
366 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
367 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
368 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
369 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
370 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
371 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
373 MemoryRegion *address_space_mem,
374 MemoryRegion *address_space_io,
375 uint8_t devfn_min, int nirq, const char *typename);
376 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
377 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
378 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
379 void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
380 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
381 PCIINTxRoutingNotifier notifier);
382 void pci_device_reset(PCIDevice *dev);
383 void pci_bus_reset(PCIBus *bus);
385 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
386 const char *default_devaddr);
387 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
388 const char *default_devaddr);
390 PCIDevice *pci_vga_init(PCIBus *bus);
392 int pci_bus_num(PCIBus *s);
393 void pci_for_each_device(PCIBus *bus, int bus_num,
394 void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque),
396 PCIBus *pci_find_root_bus(int domain);
397 int pci_find_domain(const PCIBus *bus);
398 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
399 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
400 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
402 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
405 void pci_device_deassert_intx(PCIDevice *dev);
407 typedef DMAContext *(*PCIDMAContextFunc)(PCIBus *, void *, int);
409 void pci_setup_iommu(PCIBus *bus, PCIDMAContextFunc fn, void *opaque);
412 pci_set_byte(uint8_t *config, uint8_t val)
417 static inline uint8_t
418 pci_get_byte(const uint8_t *config)
424 pci_set_word(uint8_t *config, uint16_t val)
426 cpu_to_le16wu((uint16_t *)config, val);
429 static inline uint16_t
430 pci_get_word(const uint8_t *config)
432 return le16_to_cpupu((const uint16_t *)config);
436 pci_set_long(uint8_t *config, uint32_t val)
438 cpu_to_le32wu((uint32_t *)config, val);
441 static inline uint32_t
442 pci_get_long(const uint8_t *config)
444 return le32_to_cpupu((const uint32_t *)config);
448 pci_set_quad(uint8_t *config, uint64_t val)
450 cpu_to_le64w((uint64_t *)config, val);
453 static inline uint64_t
454 pci_get_quad(const uint8_t *config)
456 return le64_to_cpup((const uint64_t *)config);
460 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
462 pci_set_word(&pci_config[PCI_VENDOR_ID], val);
466 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
468 pci_set_word(&pci_config[PCI_DEVICE_ID], val);
472 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
474 pci_set_byte(&pci_config[PCI_REVISION_ID], val);
478 pci_config_set_class(uint8_t *pci_config, uint16_t val)
480 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
484 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
486 pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
490 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
492 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
496 * helper functions to do bit mask operation on configuration space.
497 * Just to set bit, use test-and-set and discard returned value.
498 * Just to clear bit, use test-and-clear and discard returned value.
499 * NOTE: They aren't atomic.
501 static inline uint8_t
502 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
504 uint8_t val = pci_get_byte(config);
505 pci_set_byte(config, val & ~mask);
509 static inline uint8_t
510 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
512 uint8_t val = pci_get_byte(config);
513 pci_set_byte(config, val | mask);
517 static inline uint16_t
518 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
520 uint16_t val = pci_get_word(config);
521 pci_set_word(config, val & ~mask);
525 static inline uint16_t
526 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
528 uint16_t val = pci_get_word(config);
529 pci_set_word(config, val | mask);
533 static inline uint32_t
534 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
536 uint32_t val = pci_get_long(config);
537 pci_set_long(config, val & ~mask);
541 static inline uint32_t
542 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
544 uint32_t val = pci_get_long(config);
545 pci_set_long(config, val | mask);
549 static inline uint64_t
550 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
552 uint64_t val = pci_get_quad(config);
553 pci_set_quad(config, val & ~mask);
557 static inline uint64_t
558 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
560 uint64_t val = pci_get_quad(config);
561 pci_set_quad(config, val | mask);
565 /* Access a register specified by a mask */
567 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
569 uint8_t val = pci_get_byte(config);
570 uint8_t rval = reg << (ffs(mask) - 1);
571 pci_set_byte(config, (~mask & val) | (mask & rval));
574 static inline uint8_t
575 pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
577 uint8_t val = pci_get_byte(config);
578 return (val & mask) >> (ffs(mask) - 1);
582 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
584 uint16_t val = pci_get_word(config);
585 uint16_t rval = reg << (ffs(mask) - 1);
586 pci_set_word(config, (~mask & val) | (mask & rval));
589 static inline uint16_t
590 pci_get_word_by_mask(uint8_t *config, uint16_t mask)
592 uint16_t val = pci_get_word(config);
593 return (val & mask) >> (ffs(mask) - 1);
597 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
599 uint32_t val = pci_get_long(config);
600 uint32_t rval = reg << (ffs(mask) - 1);
601 pci_set_long(config, (~mask & val) | (mask & rval));
604 static inline uint32_t
605 pci_get_long_by_mask(uint8_t *config, uint32_t mask)
607 uint32_t val = pci_get_long(config);
608 return (val & mask) >> (ffs(mask) - 1);
612 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
614 uint64_t val = pci_get_quad(config);
615 uint64_t rval = reg << (ffs(mask) - 1);
616 pci_set_quad(config, (~mask & val) | (mask & rval));
619 static inline uint64_t
620 pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
622 uint64_t val = pci_get_quad(config);
623 return (val & mask) >> (ffs(mask) - 1);
626 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
628 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
631 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
632 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
634 static inline int pci_is_express(const PCIDevice *d)
636 return d->cap_present & QEMU_PCI_CAP_EXPRESS;
639 static inline uint32_t pci_config_size(const PCIDevice *d)
641 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
644 /* DMA access functions */
645 static inline DMAContext *pci_dma_context(PCIDevice *dev)
650 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
651 void *buf, dma_addr_t len, DMADirection dir)
653 dma_memory_rw(pci_dma_context(dev), addr, buf, len, dir);
657 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
658 void *buf, dma_addr_t len)
660 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
663 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
664 const void *buf, dma_addr_t len)
666 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
669 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
670 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \
673 return ld##_l##_dma(pci_dma_context(dev), addr); \
675 static inline void st##_s##_pci_dma(PCIDevice *dev, \
676 dma_addr_t addr, uint##_bits##_t val) \
678 st##_s##_dma(pci_dma_context(dev), addr, val); \
681 PCI_DMA_DEFINE_LDST(ub, b, 8);
682 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
683 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
684 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
685 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
686 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
687 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
689 #undef PCI_DMA_DEFINE_LDST
691 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
692 dma_addr_t *plen, DMADirection dir)
696 buf = dma_memory_map(pci_dma_context(dev), addr, plen, dir);
700 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
701 DMADirection dir, dma_addr_t access_len)
703 dma_memory_unmap(pci_dma_context(dev), buffer, len, dir, access_len);
706 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
709 qemu_sglist_init(qsg, alloc_hint, pci_dma_context(dev));
712 extern const VMStateDescription vmstate_pci_device;
714 #define VMSTATE_PCI_DEVICE(_field, _state) { \
715 .name = (stringify(_field)), \
716 .size = sizeof(PCIDevice), \
717 .vmsd = &vmstate_pci_device, \
718 .flags = VMS_STRUCT, \
719 .offset = vmstate_offset_value(_state, _field, PCIDevice), \
722 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
723 .name = (stringify(_field)), \
724 .size = sizeof(PCIDevice), \
725 .vmsd = &vmstate_pci_device, \
726 .flags = VMS_STRUCT|VMS_POINTER, \
727 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \