1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Common internal memory map for some Freescale SoCs
5 * Copyright 2014 Freescale Semiconductor, Inc.
14 #ifdef CONFIG_SYS_FSL_SEC_LE
15 #define sec_in32(a) in_le32(a)
16 #define sec_out32(a, v) out_le32(a, v)
17 #define sec_in16(a) in_le16(a)
18 #define sec_clrbits32 clrbits_le32
19 #define sec_setbits32 setbits_le32
20 #elif defined(CONFIG_SYS_FSL_SEC_BE)
21 #define sec_in32(a) in_be32(a)
22 #define sec_out32(a, v) out_be32(a, v)
23 #define sec_in16(a) in_be16(a)
24 #define sec_clrbits32 clrbits_be32
25 #define sec_setbits32 setbits_be32
26 #elif defined(CONFIG_SYS_FSL_HAS_SEC)
27 #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
30 /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
31 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
32 /* RNG4 TRNG test registers */
34 #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
35 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in
36 both entropy shifter and
37 statistical checker */
38 #define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both
40 statistical checker */
41 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in
42 entropy shifter, raw data
43 in statistical checker */
44 #define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */
45 u32 rtmctl; /* misc. control register */
46 u32 rtscmisc; /* statistical check misc. register */
47 u32 rtpkrrng; /* poker range register */
48 #define RTSDCTL_ENT_DLY_MIN 3200
49 #define RTSDCTL_ENT_DLY_MAX 12800
51 u32 rtpkrmax; /* PRGM=1: poker max. limit register */
52 u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
54 #define RTSDCTL_ENT_DLY_SHIFT 16
55 #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
56 u32 rtsdctl; /* seed control register */
58 u32 rtsblim; /* PRGM=1: sparse bit limit register */
59 u32 rttotsam; /* PRGM=0: total samples register */
61 u32 rtfreqmin; /* frequency count min. limit register */
62 #define RTFRQMAX_DISABLE (1 << 20)
64 u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */
65 u32 rtfreqcnt; /* PRGM=0: freq. count register */
68 #define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001
69 #define RNG_STATE1_HANDLE_INSTANTIATED 0x00000002
70 #define RNG_STATE_HANDLE_MASK \
71 (RNG_STATE0_HANDLE_INSTANTIATED | RNG_STATE1_HANDLE_INSTANTIATED)
72 #define RDSTA_SKVN 0x40000000
73 u32 rdsta; /*RNG DRNG Status Register*/
77 /* Version registers (Era 10+) */
79 u32 crca; /* CRCA_VERSION */
80 u32 afha; /* AFHA_VERSION */
81 u32 kfha; /* KFHA_VERSION */
82 u32 pkha; /* PKHA_VERSION */
83 u32 aesa; /* AESA_VERSION */
84 u32 mdha; /* MDHA_VERSION */
85 u32 desa; /* DESA_VERSION */
86 u32 snw8a; /* SNW8A_VERSION */
87 u32 snw9a; /* SNW9A_VERSION */
88 u32 zuce; /* ZUCE_VERSION */
89 u32 zuca; /* ZUCA_VERSION */
90 u32 ccha; /* CCHA_VERSION */
91 u32 ptha; /* PTHA_VERSION */
92 u32 rng; /* RNG_VERSION */
93 u32 trng; /* TRNG_VERSION */
94 u32 aaha; /* AAHA_VERSION */
96 u32 sr; /* SR_VERSION */
97 u32 dma; /* DMA_VERSION */
98 u32 ai; /* AI_VERSION */
99 u32 qi; /* QI_VERSION */
100 u32 jr; /* JR_VERSION */
101 u32 deco; /* DECO_VERSION */
104 #define CHA_VER_NUM_MASK 0x000000ff
105 #define CHA_VER_MISC_SHIFT 8
106 #define CHA_VER_MISC_MASK 0x0000ff00
107 #define CHA_VER_REV_SHIFT 16
108 #define CHA_VER_REV_MASK 0x00ff0000
109 #define CHA_VER_VID_SHIFT 24
110 #define CHA_VER_VID_MASK 0xff000000
112 typedef struct ccsr_sec {
114 u32 mcfgr; /* Master CFG Register */
118 u32 ms; /* Job Ring LIODN Register, MS */
119 u32 ls; /* Job Ring LIODN Register, LS */
122 u32 jrstartr; /* Job Ring Start Register */
124 u32 ms; /* RTIC LIODN Register, MS */
125 u32 ls; /* RTIC LIODN Register, LS */
128 u32 decorr; /* DECO Request Register */
130 u32 ms; /* DECO LIODN Register, MS */
131 u32 ls; /* DECO LIODN Register, LS */
133 u32 dar; /* DECO Avail Register */
134 u32 drr; /* DECO Reset Register */
136 struct rng4tst rng; /* RNG Registers */
138 struct version_regs vreg; /* version registers since era 10 */
140 u32 crnr_ms; /* CHA Revision Number Register, MS */
141 u32 crnr_ls; /* CHA Revision Number Register, LS */
142 u32 ctpr_ms; /* Compile Time Parameters Register, MS */
143 u32 ctpr_ls; /* Compile Time Parameters Register, LS */
145 u32 far_ms; /* Fault Address Register, MS */
146 u32 far_ls; /* Fault Address Register, LS */
147 u32 falr; /* Fault Address LIODN Register */
148 u32 fadr; /* Fault Address Detail Register */
150 u32 csta; /* CAAM Status Register */
151 u32 smpart; /* Secure Memory Partition Parameters */
152 u32 smvid; /* Secure Memory Version ID */
153 u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
154 u32 ccbvid; /* CHA Cluster Block Version ID Register */
155 u32 chavid_ms; /* CHA Version ID Register, MS */
156 u32 chavid_ls; /* CHA Version ID Register, LS */
157 u32 chanum_ms; /* CHA Number Register, MS */
158 u32 chanum_ls; /* CHA Number Register, LS */
159 u32 secvid_ms; /* SEC Version ID Register, MS */
160 u32 secvid_ls; /* SEC Version ID Register, LS */
161 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
166 u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
167 u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
168 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
175 #define SEC_CTPR_MS_AXI_LIODN 0x08000000
176 #define SEC_CTPR_MS_QI 0x02000000
177 #define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001
178 #define SEC_CTPR_MS_VIRT_EN_POR 0x00000002
179 #define SEC_RVID_MA 0x0f000000
180 #define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
181 #define SEC_CHANUM_MS_JRNUM_SHIFT 28
182 #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
183 #define SEC_CHANUM_MS_DECONUM_SHIFT 24
184 #define SEC_SECVID_MS_IPID_MASK 0xffff0000
185 #define SEC_SECVID_MS_IPID_SHIFT 16
186 #define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
187 #define SEC_SECVID_MS_MAJ_REV_SHIFT 8
188 #define SEC_CCBVID_ERA_MASK 0xff000000
189 #define SEC_CCBVID_ERA_SHIFT 24
190 #define SEC_SCFGR_RDBENABLE 0x00000400
191 #define SEC_SCFGR_VIRT_EN 0x00008000
192 #define SEC_CHAVID_LS_RNG_SHIFT 16
193 #define SEC_CHAVID_RNG_LS_MASK 0x000f0000
195 #define CONFIG_JRSTARTR_JR0 0x00000001
198 #if defined(CONFIG_SYS_FSL_SEC_LE) && \
199 !(defined(CONFIG_MX6) || defined(CONFIG_MX7))
212 #if defined(CONFIG_SYS_FSL_SEC_LE) && \
213 !(defined(CONFIG_MX6) || defined(CONFIG_MX7))
241 * Scatter Gather Entry - Specifies the the Scatter Gather Format
242 * related information
245 #if defined(CONFIG_SYS_FSL_SEC_LE) && \
246 !(defined(CONFIG_MX6) || defined(CONFIG_MX7))
247 uint32_t addr_lo; /* Memory Address - lo */
248 uint32_t addr_hi; /* Memory Address of start of buffer - hi */
250 uint32_t addr_hi; /* Memory Address of start of buffer - hi */
251 uint32_t addr_lo; /* Memory Address - lo */
254 uint32_t len_flag; /* Length of the data in the frame */
255 #define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF
256 #define SG_ENTRY_EXTENSION_BIT 0x80000000
257 #define SG_ENTRY_FINAL_BIT 0x40000000
258 uint32_t bpid_offset;
259 #define SG_ENTRY_BPID_MASK 0x00FF0000
260 #define SG_ENTRY_BPID_SHIFT 16
261 #define SG_ENTRY_OFFSET_MASK 0x00001FFF
262 #define SG_ENTRY_OFFSET_SHIFT 0
265 #define BLOB_SIZE(x) ((x) + 32 + 16) /* Blob buffer size */
267 #if defined(CONFIG_MX6) || defined(CONFIG_MX7)
268 /* Job Ring Base Address */
269 #define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
270 /* Secure Memory Offset varies accross versions */
271 #define SM_V1_OFFSET 0x0f4
272 #define SM_V2_OFFSET 0xa00
273 /*Secure Memory Versioning */
274 #define SMVID_V2 0x20105
275 #define SM_VERSION(x) (x < SMVID_V2 ? 1 : 2)
276 #define SM_OFFSET(x) (x == 1 ? SM_V1_OFFSET : SM_V2_OFFSET)
277 /* CAAM Job Ring 0 Registers */
278 /* Secure Memory Partition Owner register */
279 #define SMCSJR_PO (3 << 6)
280 /* JR Allocation Error */
281 #define SMCSJR_AERR (3 << 12)
282 /* Secure memory partition 0 page 0 owner register */
283 #define CAAM_SMPO_0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC)
284 /* Secure memory command register */
285 #define CAAM_SMCJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_CMD(v))
286 /* Secure memory command status register */
287 #define CAAM_SMCSJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_STATUS(v))
288 /* Secure memory access permissions register */
289 #define CAAM_SMAPJR(v, jr, y) \
290 (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_PERM(v) + y * 16)
291 /* Secure memory access group 2 register */
292 #define CAAM_SMAG2JR(v, jr, y) \
293 (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP2(v) + y * 16)
294 /* Secure memory access group 1 register */
295 #define CAAM_SMAG1JR(v, jr, y) \
296 (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP1(v) + y * 16)
298 /* Commands and macros for secure memory */
299 #define SM_CMD(v) (v == 1 ? 0x0 : 0x1E4)
300 #define SM_STATUS(v) (v == 1 ? 0x8 : 0x1EC)
301 #define SM_PERM(v) (v == 1 ? 0x10 : 0x4)
302 #define SM_GROUP2(v) (v == 1 ? 0x14 : 0x8)
303 #define SM_GROUP1(v) (v == 1 ? 0x18 : 0xC)
304 #define CMD_PAGE_ALLOC 0x1
305 #define CMD_PAGE_DEALLOC 0x2
306 #define CMD_PART_DEALLOC 0x3
307 #define CMD_INQUIRY 0x5
308 #define CMD_COMPLETE (3 << 14)
309 #define PAGE_AVAILABLE 0
310 #define PAGE_OWNED (3 << 6)
311 #define PAGE(x) (x << 16)
312 #define PARTITION(x) (x << 8)
313 #define PARTITION_OWNER(x) (0x3 << (x*2))
315 /* Address of secure 4kbyte pages */
316 #define SEC_MEM_PAGE0 CAAM_ARB_BASE_ADDR
317 #define SEC_MEM_PAGE1 (CAAM_ARB_BASE_ADDR + 0x1000)
318 #define SEC_MEM_PAGE2 (CAAM_ARB_BASE_ADDR + 0x2000)
319 #define SEC_MEM_PAGE3 (CAAM_ARB_BASE_ADDR + 0x3000)
321 #define JR_MID 2 /* Matches ROM configuration */
322 #define KS_G1 (1 << JR_MID) /* CAAM only */
323 #define PERM 0x0000B008 /* Clear on release, lock SMAP
324 * lock SMAG group 1 Blob */
326 /* HAB WRAPPED KEY header */
327 #define WRP_HDR_SIZE 0x08
330 /* HAB WRAPPED KEY Data */
335 /* Partition and Page IDs */
336 #define PARTITION_1 1
339 #define ERROR_IN_PAGE_ALLOC 1
340 #define ECONSTRJDESC -1
345 * Encapsulates the src in a secure blob and stores it dst
346 * @src: reference to the plaintext
347 * @dst: reference to the output adrress
348 * @len: size in bytes of src
349 * @return: 0 on success, error otherwise
351 int blob_dek(const u8 *src, u8 *dst, u8 len);
353 #if defined(CONFIG_ARCH_C29X)
354 int sec_init_idx(uint8_t);
358 u8 caam_get_era(void);
361 #endif /* __FSL_SEC_H */