2 * Common internal memory map for some Freescale SoCs
4 * Copyright 2014 Freescale Semiconductor, Inc.
14 #ifdef CONFIG_SYS_FSL_SEC_LE
15 #define sec_in32(a) in_le32(a)
16 #define sec_out32(a, v) out_le32(a, v)
17 #define sec_in16(a) in_le16(a)
18 #define sec_clrbits32 clrbits_le32
19 #define sec_setbits32 setbits_le32
20 #elif defined(CONFIG_SYS_FSL_SEC_BE)
21 #define sec_in32(a) in_be32(a)
22 #define sec_out32(a, v) out_be32(a, v)
23 #define sec_in16(a) in_be16(a)
24 #define sec_clrbits32 clrbits_be32
25 #define sec_setbits32 setbits_be32
27 #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
30 /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
31 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
32 /* RNG4 TRNG test registers */
34 #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
35 u32 rtmctl; /* misc. control register */
36 u32 rtscmisc; /* statistical check misc. register */
37 u32 rtpkrrng; /* poker range register */
38 #define RTSDCTL_ENT_DLY_MIN 3200
39 #define RTSDCTL_ENT_DLY_MAX 12800
41 u32 rtpkrmax; /* PRGM=1: poker max. limit register */
42 u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
44 #define RTSDCTL_ENT_DLY_SHIFT 16
45 #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
46 u32 rtsdctl; /* seed control register */
48 u32 rtsblim; /* PRGM=1: sparse bit limit register */
49 u32 rttotsam; /* PRGM=0: total samples register */
51 u32 rtfreqmin; /* frequency count min. limit register */
52 #define RTFRQMAX_DISABLE (1 << 20)
54 u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */
55 u32 rtfreqcnt; /* PRGM=0: freq. count register */
58 #define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001
59 u32 rdsta; /*RNG DRNG Status Register*/
63 typedef struct ccsr_sec {
65 u32 mcfgr; /* Master CFG Register */
69 u32 ms; /* Job Ring LIODN Register, MS */
70 u32 ls; /* Job Ring LIODN Register, LS */
73 u32 jrstartr; /* Job Ring Start Register */
75 u32 ms; /* RTIC LIODN Register, MS */
76 u32 ls; /* RTIC LIODN Register, LS */
79 u32 decorr; /* DECO Request Register */
81 u32 ms; /* DECO LIODN Register, MS */
82 u32 ls; /* DECO LIODN Register, LS */
85 u32 dar; /* DECO Avail Register */
86 u32 drr; /* DECO Reset Register */
88 struct rng4tst rng; /* RNG Registers */
90 u32 crnr_ms; /* CHA Revision Number Register, MS */
91 u32 crnr_ls; /* CHA Revision Number Register, LS */
92 u32 ctpr_ms; /* Compile Time Parameters Register, MS */
93 u32 ctpr_ls; /* Compile Time Parameters Register, LS */
95 u32 far_ms; /* Fault Address Register, MS */
96 u32 far_ls; /* Fault Address Register, LS */
97 u32 falr; /* Fault Address LIODN Register */
98 u32 fadr; /* Fault Address Detail Register */
100 u32 csta; /* CAAM Status Register */
102 u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
103 u32 ccbvid; /* CHA Cluster Block Version ID Register */
104 u32 chavid_ms; /* CHA Version ID Register, MS */
105 u32 chavid_ls; /* CHA Version ID Register, LS */
106 u32 chanum_ms; /* CHA Number Register, MS */
107 u32 chanum_ls; /* CHA Number Register, LS */
108 u32 secvid_ms; /* SEC Version ID Register, MS */
109 u32 secvid_ls; /* SEC Version ID Register, LS */
111 u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
112 u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
116 #define SEC_CTPR_MS_AXI_LIODN 0x08000000
117 #define SEC_CTPR_MS_QI 0x02000000
118 #define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001
119 #define SEC_CTPR_MS_VIRT_EN_POR 0x00000002
120 #define SEC_RVID_MA 0x0f000000
121 #define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
122 #define SEC_CHANUM_MS_JRNUM_SHIFT 28
123 #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
124 #define SEC_CHANUM_MS_DECONUM_SHIFT 24
125 #define SEC_SECVID_MS_IPID_MASK 0xffff0000
126 #define SEC_SECVID_MS_IPID_SHIFT 16
127 #define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
128 #define SEC_SECVID_MS_MAJ_REV_SHIFT 8
129 #define SEC_CCBVID_ERA_MASK 0xff000000
130 #define SEC_CCBVID_ERA_SHIFT 24
131 #define SEC_SCFGR_RDBENABLE 0x00000400
132 #define SEC_SCFGR_VIRT_EN 0x00008000
133 #define SEC_CHAVID_LS_RNG_SHIFT 16
134 #define SEC_CHAVID_RNG_LS_MASK 0x000f0000
136 #define CONFIG_JRSTARTR_JR0 0x00000001
139 #if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6)
152 #if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6)
180 * Scatter Gather Entry - Specifies the the Scatter Gather Format
181 * related information
184 #if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6)
185 uint32_t addr_lo; /* Memory Address - lo */
186 uint16_t addr_hi; /* Memory Address of start of buffer - hi */
187 uint16_t reserved_zero;
189 uint16_t reserved_zero;
190 uint16_t addr_hi; /* Memory Address of start of buffer - hi */
191 uint32_t addr_lo; /* Memory Address - lo */
194 uint32_t len_flag; /* Length of the data in the frame */
195 #define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF
196 #define SG_ENTRY_EXTENSION_BIT 0x80000000
197 #define SG_ENTRY_FINAL_BIT 0x40000000
198 uint32_t bpid_offset;
199 #define SG_ENTRY_BPID_MASK 0x00FF0000
200 #define SG_ENTRY_BPID_SHIFT 16
201 #define SG_ENTRY_OFFSET_MASK 0x00001FFF
202 #define SG_ENTRY_OFFSET_SHIFT 0
206 /* CAAM Job Ring 0 Registers */
207 /* Secure Memory Partition Owner register */
208 #define SMCSJR_PO (3 << 6)
209 /* JR Allocation Error */
210 #define SMCSJR_AERR (3 << 12)
211 /* Secure memory partition 0 page 0 owner register */
212 #define CAAM_SMPO_0 CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC
213 /* Secure memory command register */
214 #define CAAM_SMCJR0 CONFIG_SYS_FSL_SEC_ADDR + 0x10f4
215 /* Secure memory command status register */
216 #define CAAM_SMCSJR0 CONFIG_SYS_FSL_SEC_ADDR + 0x10fc
217 /* Secure memory access permissions register */
218 #define CAAM_SMAPJR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1104 + y*16)
219 /* Secure memory access group 2 register */
220 #define CAAM_SMAG2JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1108 + y*16)
221 /* Secure memory access group 1 register */
222 #define CAAM_SMAG1JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x110C + y*16)
224 /* Commands and macros for secure memory */
225 #define CMD_PAGE_ALLOC 0x1
226 #define CMD_PAGE_DEALLOC 0x2
227 #define CMD_PART_DEALLOC 0x3
228 #define CMD_INQUIRY 0x5
229 #define CMD_COMPLETE (3 << 14)
230 #define PAGE_AVAILABLE 0
231 #define PAGE_OWNED (3 << 6)
232 #define PAGE(x) (x << 16)
233 #define PARTITION(x) (x << 8)
234 #define PARTITION_OWNER(x) (0x3 << (x*2))
236 /* Address of secure 4kbyte pages */
237 #define SEC_MEM_PAGE0 CAAM_ARB_BASE_ADDR
238 #define SEC_MEM_PAGE1 (CAAM_ARB_BASE_ADDR + 0x1000)
239 #define SEC_MEM_PAGE2 (CAAM_ARB_BASE_ADDR + 0x2000)
240 #define SEC_MEM_PAGE3 (CAAM_ARB_BASE_ADDR + 0x3000)
242 #define JR_MID 2 /* Matches ROM configuration */
243 #define KS_G1 (1 << JR_MID) /* CAAM only */
244 #define PERM 0x0000B008 /* Clear on release, lock SMAP
245 * lock SMAG group 1 Blob */
247 #define BLOB_SIZE(x) (x + 32 + 16) /* Blob buffer size */
249 /* HAB WRAPPED KEY header */
250 #define WRP_HDR_SIZE 0x08
253 /* HAB WRAPPED KEY Data */
258 /* Partition and Page IDs */
259 #define PARTITION_1 1
262 #define ERROR_IN_PAGE_ALLOC 1
263 #define ECONSTRJDESC -1
270 * Encapsulates the src in a secure blob and stores it dst
271 * @src: reference to the plaintext
272 * @dst: reference to the output adrress
273 * @len: size in bytes of src
274 * @return: 0 on success, error otherwise
276 int blob_dek(const u8 *src, u8 *dst, u8 len);
280 #endif /* __FSL_SEC_H */