2 * (c) 2009 Magnus Lilja <lilja.magnus@gmail.com>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * Register map and bit definitions for the Freescale NAND Flash Controller
28 * present in various i.MX devices.
30 * MX31 and MX27 have version 1, which has:
31 * 4 512-byte main buffers and
32 * 4 16-byte spare buffers
33 * to support up to 2K byte pagesize nand.
34 * Reading or writing a 2K page requires 4 FDI/FDO cycles.
36 * MX25 and MX35 have version 2.1, which has:
37 * 8 512-byte main buffers and
38 * 8 64-byte spare buffers
39 * to support up to 4K byte pagesize nand.
40 * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
41 * Also some of registers are moved and/or changed meaning as seen below.
43 #if defined(CONFIG_MX27) || defined(CONFIG_MX31)
45 #define is_mxc_nfc_1() 1
46 #define is_mxc_nfc_21() 0
47 #elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
49 #define is_mxc_nfc_1() 0
50 #define is_mxc_nfc_21() 1
52 #error "MXC NFC implementation not supported"
55 #if defined(MXC_NFC_V1)
56 #define NAND_MXC_NR_BUFS 4
57 #define NAND_MXC_SPARE_BUF_SIZE 16
58 #define NAND_MXC_REG_OFFSET 0xe00
59 #define NAND_MXC_2K_MULTI_CYCLE
60 #elif defined(MXC_NFC_V2_1)
61 #define NAND_MXC_NR_BUFS 8
62 #define NAND_MXC_SPARE_BUF_SIZE 64
63 #define NAND_MXC_REG_OFFSET 0x1e00
67 u8 main_area[NAND_MXC_NR_BUFS][0x200];
68 u8 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE];
70 * reserved size is offset of nfc registers
71 * minus total main and spare sizes
73 u8 reserved1[NAND_MXC_REG_OFFSET
74 - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
75 #if defined(MXC_NFC_V1)
82 u16 ecc_status_result;
86 u16 unlockstart_blkaddr;
87 u16 unlockend_blkaddr;
91 #elif defined(MXC_NFC_V2_1)
97 u32 ecc_status_result;
105 u16 unlockstart_blkaddr;
106 u16 unlockend_blkaddr;
107 u16 unlockstart_blkaddr1;
108 u16 unlockend_blkaddr1;
109 u16 unlockstart_blkaddr2;
110 u16 unlockend_blkaddr2;
111 u16 unlockstart_blkaddr3;
112 u16 unlockend_blkaddr3;
116 /* Set FCMD to 1, rest to 0 for Command operation */
119 /* Set FADD to 1, rest to 0 for Address operation */
122 /* Set FDI to 1, rest to 0 for Input operation */
123 #define NFC_INPUT 0x4
125 /* Set FDO to 001, rest to 0 for Data Output operation */
126 #define NFC_OUTPUT 0x8
128 /* Set FDO to 010, rest to 0 for Read ID operation */
131 /* Set FDO to 100, rest to 0 for Read Status operation */
132 #define NFC_STATUS 0x20
134 #define NFC_CONFIG1_SP_EN (1 << 2)
135 #define NFC_CONFIG1_RST (1 << 6)
136 #define NFC_CONFIG1_CE (1 << 7)
137 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
138 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
139 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
140 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
141 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
142 #define NFC_V2_CONFIG1_FP_INT (1 << 11)
144 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
146 #define operation config2
147 #define readnfc readw
148 #define writenfc writew
150 #endif /* __FSL_NFC_H */