1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2009-2012, 2013 Freescale Semiconductor, Inc.
4 * Jun-jie Zhang <b18070@freescale.com>
5 * Mingkai Hu <Mingkai.hu@freescale.com>
15 u32 miimcfg; /* MII management configuration reg */
16 u32 miimcom; /* MII management command reg */
17 u32 miimadd; /* MII management address reg */
18 u32 miimcon; /* MII management control reg */
19 u32 miimstat; /* MII management status reg */
20 u32 miimind; /* MII management indication reg */
21 u32 ifstat; /* Interface Status Register */
24 int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc);
26 /* PHY register offsets */
27 #define PHY_EXT_PAGE_ACCESS 0x1f
29 /* MII Management Configuration Register */
30 #define MIIMCFG_RESET_MGMT 0x80000000
31 #define MIIMCFG_MGMT_CLOCK_SELECT 0x00000007
32 #define MIIMCFG_INIT_VALUE 0x00000003
34 /* MII Management Command Register */
35 #define MIIMCOM_READ_CYCLE 0x00000001
36 #define MIIMCOM_SCAN_CYCLE 0x00000002
38 /* MII Management Address Register */
39 #define MIIMADD_PHY_ADDR_SHIFT 8
41 /* MII Management Indicator Register */
42 #define MIIMIND_BUSY 0x00000001
43 #define MIIMIND_NOTVALID 0x00000004
45 void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
46 int dev_addr, int reg, int value);
47 int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr,
48 int dev_addr, int regnum);
49 int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum);
50 int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
52 int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
53 int regnum, u16 value);
54 int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
56 int memac_mdio_reset(struct mii_dev *bus);
58 struct fsl_pq_mdio_info {
59 struct tsec_mii_mng __iomem *regs;
62 int fsl_pq_mdio_init(struct bd_info *bis, struct fsl_pq_mdio_info *info);
64 #endif /* __FSL_PHY_H__ */