include/fsl_immap.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Common internal memory map for some Freescale SoCs
   4  *
   5  * Copyright 2013-2014 Freescale Semiconductor, Inc.
   6  */
   7
   8 #ifndef __FSL_IMMAP_H
   9 #define __FSL_IMMAP_H
  10 /*
  11  * DDR memory controller registers
  12  * This structure works for mpc83xx (DDR2 and DDR3), mpc85xx, mpc86xx.
  13  */
  14 struct ccsr_ddr {
  15         u32     cs0_bnds;               /* Chip Select 0 Memory Bounds */
  16         u8      res_04[4];
  17         u32     cs1_bnds;               /* Chip Select 1 Memory Bounds */
  18         u8      res_0c[4];
  19         u32     cs2_bnds;               /* Chip Select 2 Memory Bounds */
  20         u8      res_14[4];
  21         u32     cs3_bnds;               /* Chip Select 3 Memory Bounds */
  22         u8      res_1c[100];
  23         u32     cs0_config;             /* Chip Select Configuration */
  24         u32     cs1_config;             /* Chip Select Configuration */
  25         u32     cs2_config;             /* Chip Select Configuration */
  26         u32     cs3_config;             /* Chip Select Configuration */
  27         u8      res_90[48];
  28         u32     cs0_config_2;           /* Chip Select Configuration 2 */
  29         u32     cs1_config_2;           /* Chip Select Configuration 2 */
  30         u32     cs2_config_2;           /* Chip Select Configuration 2 */
  31         u32     cs3_config_2;           /* Chip Select Configuration 2 */
  32         u8      res_d0[48];
  33         u32     timing_cfg_3;           /* SDRAM Timing Configuration 3 */
  34         u32     timing_cfg_0;           /* SDRAM Timing Configuration 0 */
  35         u32     timing_cfg_1;           /* SDRAM Timing Configuration 1 */
  36         u32     timing_cfg_2;           /* SDRAM Timing Configuration 2 */
  37         u32     sdram_cfg;              /* SDRAM Control Configuration */
  38         u32     sdram_cfg_2;            /* SDRAM Control Configuration 2 */
  39         u32     sdram_mode;             /* SDRAM Mode Configuration */
  40         u32     sdram_mode_2;           /* SDRAM Mode Configuration 2 */
  41         u32     sdram_md_cntl;          /* SDRAM Mode Control */
  42         u32     sdram_interval;         /* SDRAM Interval Configuration */
  43         u32     sdram_data_init;        /* SDRAM Data initialization */
  44         u8      res_12c[4];
  45         u32     sdram_clk_cntl;         /* SDRAM Clock Control */
  46         u8      res_134[20];
  47         u32     init_addr;              /* training init addr */
  48         u32     init_ext_addr;          /* training init extended addr */
  49         u8      res_150[16];
  50         u32     timing_cfg_4;           /* SDRAM Timing Configuration 4 */
  51         u32     timing_cfg_5;           /* SDRAM Timing Configuration 5 */
  52         u32     timing_cfg_6;           /* SDRAM Timing Configuration 6 */
  53         u32     timing_cfg_7;           /* SDRAM Timing Configuration 7 */
  54         u32     ddr_zq_cntl;            /* ZQ calibration control*/
  55         u32     ddr_wrlvl_cntl;         /* write leveling control*/
  56         u8      reg_178[4];
  57         u32     ddr_sr_cntr;            /* self refresh counter */
  58         u32     ddr_sdram_rcw_1;        /* Control Words 1 */
  59         u32     ddr_sdram_rcw_2;        /* Control Words 2 */
  60         u8      reg_188[8];
  61         u32     ddr_wrlvl_cntl_2;       /* write leveling control 2 */
  62         u32     ddr_wrlvl_cntl_3;       /* write leveling control 3 */
  63         u8      res_198[0x1a0-0x198];
  64         u32     ddr_sdram_rcw_3;
  65         u32     ddr_sdram_rcw_4;
  66         u32     ddr_sdram_rcw_5;
  67         u32     ddr_sdram_rcw_6;
  68         u8      res_1b0[0x200-0x1b0];
  69         u32     sdram_mode_3;           /* SDRAM Mode Configuration 3 */
  70         u32     sdram_mode_4;           /* SDRAM Mode Configuration 4 */
  71         u32     sdram_mode_5;           /* SDRAM Mode Configuration 5 */
  72         u32     sdram_mode_6;           /* SDRAM Mode Configuration 6 */
  73         u32     sdram_mode_7;           /* SDRAM Mode Configuration 7 */
  74         u32     sdram_mode_8;           /* SDRAM Mode Configuration 8 */
  75         u8      res_218[0x220-0x218];
  76         u32     sdram_mode_9;           /* SDRAM Mode Configuration 9 */
  77         u32     sdram_mode_10;          /* SDRAM Mode Configuration 10 */
  78         u32     sdram_mode_11;          /* SDRAM Mode Configuration 11 */
  79         u32     sdram_mode_12;          /* SDRAM Mode Configuration 12 */
  80         u32     sdram_mode_13;          /* SDRAM Mode Configuration 13 */
  81         u32     sdram_mode_14;          /* SDRAM Mode Configuration 14 */
  82         u32     sdram_mode_15;          /* SDRAM Mode Configuration 15 */
  83         u32     sdram_mode_16;          /* SDRAM Mode Configuration 16 */
  84         u8      res_240[0x250-0x240];
  85         u32     timing_cfg_8;           /* SDRAM Timing Configuration 8 */
  86         u32     timing_cfg_9;           /* SDRAM Timing Configuration 9 */
  87         u8      res_258[0x260-0x258];
  88         u32     sdram_cfg_3;
  89         u8      res_264[0x400-0x264];
  90         u32     dq_map_0;
  91         u32     dq_map_1;
  92         u32     dq_map_2;
  93         u32     dq_map_3;
  94         u8      res_410[0xb20-0x410];
  95         u32     ddr_dsr1;               /* Debug Status 1 */
  96         u32     ddr_dsr2;               /* Debug Status 2 */
  97         u32     ddr_cdr1;               /* Control Driver 1 */
  98         u32     ddr_cdr2;               /* Control Driver 2 */
  99         u8      res_b30[200];
 100         u32     ip_rev1;                /* IP Block Revision 1 */
 101         u32     ip_rev2;                /* IP Block Revision 2 */
 102         u32     eor;                    /* Enhanced Optimization Register */
 103         u8      res_c04[252];
 104         u32     mtcr;                   /* Memory Test Control Register */
 105         u8      res_d04[28];
 106         u32     mtp1;                   /* Memory Test Pattern 1 */
 107         u32     mtp2;                   /* Memory Test Pattern 2 */
 108         u32     mtp3;                   /* Memory Test Pattern 3 */
 109         u32     mtp4;                   /* Memory Test Pattern 4 */
 110         u32     mtp5;                   /* Memory Test Pattern 5 */
 111         u32     mtp6;                   /* Memory Test Pattern 6 */
 112         u32     mtp7;                   /* Memory Test Pattern 7 */
 113         u32     mtp8;                   /* Memory Test Pattern 8 */
 114         u32     mtp9;                   /* Memory Test Pattern 9 */
 115         u32     mtp10;                  /* Memory Test Pattern 10 */
 116         u8      res_d48[184];
 117         u32     data_err_inject_hi;     /* Data Path Err Injection Mask High */
 118         u32     data_err_inject_lo;     /* Data Path Err Injection Mask Low */
 119         u32     ecc_err_inject;         /* Data Path Err Injection Mask ECC */
 120         u8      res_e0c[20];
 121         u32     capture_data_hi;        /* Data Path Read Capture High */
 122         u32     capture_data_lo;        /* Data Path Read Capture Low */
 123         u32     capture_ecc;            /* Data Path Read Capture ECC */
 124         u8      res_e2c[20];
 125         u32     err_detect;             /* Error Detect */
 126         u32     err_disable;            /* Error Disable */
 127         u32     err_int_en;
 128         u32     capture_attributes;     /* Error Attrs Capture */
 129         u32     capture_address;        /* Error Addr Capture */
 130         u32     capture_ext_address;    /* Error Extended Addr Capture */
 131         u32     err_sbe;                /* Single-Bit ECC Error Management */
 132         u8      res_e5c[164];
 133         u32     debug[64];              /* debug_1 to debug_64 */
 134 };
 135
 136 #ifdef CONFIG_SYS_FSL_HAS_CCI400
 137 #define CCI400_CTRLORD_TERM_BARRIER     0x00000008
 138 #define CCI400_CTRLORD_EN_BARRIER       0
 139 #define CCI400_SHAORD_NON_SHAREABLE     0x00000002
 140 #define CCI400_DVM_MESSAGE_REQ_EN       0x00000002
 141 #define CCI400_SNOOP_REQ_EN             0x00000001
 142
 143 /* CCI-400 registers */
 144 struct ccsr_cci400 {
 145         u32 ctrl_ord;                   /* Control Override */
 146         u32 spec_ctrl;                  /* Speculation Control */
 147         u32 secure_access;              /* Secure Access */
 148         u32 status;                     /* Status */
 149         u32 impr_err;                   /* Imprecise Error */
 150         u8 res_14[0x100 - 0x14];
 151         u32 pmcr;                       /* Performance Monitor Control */
 152         u8 res_104[0xfd0 - 0x104];
 153         u32 pid[8];                     /* Peripheral ID */
 154         u32 cid[4];                     /* Component ID */
 155         struct {
 156                 u32 snoop_ctrl;         /* Snoop Control */
 157                 u32 sha_ord;            /* Shareable Override */
 158                 u8 res_1008[0x1100 - 0x1008];
 159                 u32 rc_qos_ord;         /* read channel QoS Value Override */
 160                 u32 wc_qos_ord;         /* read channel QoS Value Override */
 161                 u8 res_1108[0x110c - 0x1108];
 162                 u32 qos_ctrl;           /* QoS Control */
 163                 u32 max_ot;             /* Max OT */
 164                 u8 res_1114[0x1130 - 0x1114];
 165                 u32 target_lat;         /* Target Latency */
 166                 u32 latency_regu;       /* Latency Regulation */
 167                 u32 qos_range;          /* QoS Range */
 168                 u8 res_113c[0x2000 - 0x113c];
 169         } slave[5];                     /* Slave Interface */
 170         u8 res_6000[0x9004 - 0x6000];
 171         u32 cycle_counter;              /* Cycle counter */
 172         u32 count_ctrl;                 /* Count Control */
 173         u32 overflow_status;            /* Overflow Flag Status */
 174         u8 res_9010[0xa000 - 0x9010];
 175         struct {
 176                 u32 event_select;       /* Event Select */
 177                 u32 event_count;        /* Event Count */
 178                 u32 counter_ctrl;       /* Counter Control */
 179                 u32 overflow_status;    /* Overflow Flag Status */
 180                 u8 res_a010[0xb000 - 0xa010];
 181         } pcounter[4];                  /* Performance Counter */
 182         u8 res_e004[0x10000 - 0xe004];
 183 };
 184 #endif
 185
 186 #endif /* __FSL_IMMAP_H */