driver/ddr/fsl: Update DDR4 RTT values
[platform/kernel/u-boot.git] / include / fsl_ddr_sdram.h
1 /*
2  * Copyright 2008-2014 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * Version 2 as published by the Free Software Foundation.
7  */
8
9 #ifndef FSL_DDR_MEMCTL_H
10 #define FSL_DDR_MEMCTL_H
11
12 /*
13  * Pick a basic DDR Technology.
14  */
15 #include <ddr_spd.h>
16 #include <fsl_ddrc_version.h>
17
18 #define SDRAM_TYPE_DDR1         2
19 #define SDRAM_TYPE_DDR2         3
20 #define SDRAM_TYPE_LPDDR1       6
21 #define SDRAM_TYPE_DDR3         7
22 #define SDRAM_TYPE_DDR4         5
23
24 #define DDR_BL4         4       /* burst length 4 */
25 #define DDR_BC4         DDR_BL4 /* burst chop for ddr3 */
26 #define DDR_OTF         6       /* on-the-fly BC4 and BL8 */
27 #define DDR_BL8         8       /* burst length 8 */
28
29 #define DDR3_RTT_OFF            0
30 #define DDR3_RTT_60_OHM         1 /* RTT_Nom = RZQ/4 */
31 #define DDR3_RTT_120_OHM        2 /* RTT_Nom = RZQ/2 */
32 #define DDR3_RTT_40_OHM         3 /* RTT_Nom = RZQ/6 */
33 #define DDR3_RTT_20_OHM         4 /* RTT_Nom = RZQ/12 */
34 #define DDR3_RTT_30_OHM         5 /* RTT_Nom = RZQ/8 */
35
36 #define DDR4_RTT_OFF            0
37 #define DDR4_RTT_60_OHM         1       /* RZQ/4 */
38 #define DDR4_RTT_120_OHM        2       /* RZQ/2 */
39 #define DDR4_RTT_40_OHM         3       /* RZQ/6 */
40 #define DDR4_RTT_240_OHM        4       /* RZQ/1 */
41 #define DDR4_RTT_48_OHM         5       /* RZQ/5 */
42 #define DDR4_RTT_80_OHM         6       /* RZQ/3 */
43 #define DDR4_RTT_34_OHM         7       /* RZQ/7 */
44
45 #define DDR2_RTT_OFF            0
46 #define DDR2_RTT_75_OHM         1
47 #define DDR2_RTT_150_OHM        2
48 #define DDR2_RTT_50_OHM         3
49
50 #if defined(CONFIG_SYS_FSL_DDR1)
51 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR        (1)
52 typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
53 #ifndef CONFIG_FSL_SDRAM_TYPE
54 #define CONFIG_FSL_SDRAM_TYPE   SDRAM_TYPE_DDR1
55 #endif
56 #elif defined(CONFIG_SYS_FSL_DDR2)
57 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR        (3)
58 typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
59 #ifndef CONFIG_FSL_SDRAM_TYPE
60 #define CONFIG_FSL_SDRAM_TYPE   SDRAM_TYPE_DDR2
61 #endif
62 #elif defined(CONFIG_SYS_FSL_DDR3)
63 typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
64 #ifndef CONFIG_FSL_SDRAM_TYPE
65 #define CONFIG_FSL_SDRAM_TYPE   SDRAM_TYPE_DDR3
66 #endif
67 #elif defined(CONFIG_SYS_FSL_DDR4)
68 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR        (3)     /* FIXME */
69 typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
70 #ifndef CONFIG_FSL_SDRAM_TYPE
71 #define CONFIG_FSL_SDRAM_TYPE   SDRAM_TYPE_DDR4
72 #endif
73 #endif  /* #if defined(CONFIG_SYS_FSL_DDR1) */
74
75 #define FSL_DDR_ODT_NEVER               0x0
76 #define FSL_DDR_ODT_CS                  0x1
77 #define FSL_DDR_ODT_ALL_OTHER_CS        0x2
78 #define FSL_DDR_ODT_OTHER_DIMM          0x3
79 #define FSL_DDR_ODT_ALL                 0x4
80 #define FSL_DDR_ODT_SAME_DIMM           0x5
81 #define FSL_DDR_ODT_CS_AND_OTHER_DIMM   0x6
82 #define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7
83
84 /* define bank(chip select) interleaving mode */
85 #define FSL_DDR_CS0_CS1                 0x40
86 #define FSL_DDR_CS2_CS3                 0x20
87 #define FSL_DDR_CS0_CS1_AND_CS2_CS3     (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
88 #define FSL_DDR_CS0_CS1_CS2_CS3         (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
89
90 /* define memory controller interleaving mode */
91 #define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0
92 #define FSL_DDR_PAGE_INTERLEAVING       0x1
93 #define FSL_DDR_BANK_INTERLEAVING       0x2
94 #define FSL_DDR_SUPERBANK_INTERLEAVING  0x3
95 #define FSL_DDR_256B_INTERLEAVING       0x8
96 #define FSL_DDR_3WAY_1KB_INTERLEAVING   0xA
97 #define FSL_DDR_3WAY_4KB_INTERLEAVING   0xC
98 #define FSL_DDR_3WAY_8KB_INTERLEAVING   0xD
99 /* placeholder for 4-way interleaving */
100 #define FSL_DDR_4WAY_1KB_INTERLEAVING   0x1A
101 #define FSL_DDR_4WAY_4KB_INTERLEAVING   0x1C
102 #define FSL_DDR_4WAY_8KB_INTERLEAVING   0x1D
103
104 #define SDRAM_CS_CONFIG_EN              0x80000000
105
106 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
107  */
108 #define SDRAM_CFG_MEM_EN                0x80000000
109 #define SDRAM_CFG_SREN                  0x40000000
110 #define SDRAM_CFG_ECC_EN                0x20000000
111 #define SDRAM_CFG_RD_EN                 0x10000000
112 #define SDRAM_CFG_SDRAM_TYPE_DDR1       0x02000000
113 #define SDRAM_CFG_SDRAM_TYPE_DDR2       0x03000000
114 #define SDRAM_CFG_SDRAM_TYPE_MASK       0x07000000
115 #define SDRAM_CFG_SDRAM_TYPE_SHIFT      24
116 #define SDRAM_CFG_DYN_PWR               0x00200000
117 #define SDRAM_CFG_DBW_MASK              0x00180000
118 #define SDRAM_CFG_DBW_SHIFT             19
119 #define SDRAM_CFG_32_BE                 0x00080000
120 #define SDRAM_CFG_16_BE                 0x00100000
121 #define SDRAM_CFG_8_BE                  0x00040000
122 #define SDRAM_CFG_NCAP                  0x00020000
123 #define SDRAM_CFG_2T_EN                 0x00008000
124 #define SDRAM_CFG_BI                    0x00000001
125
126 #define SDRAM_CFG2_FRC_SR               0x80000000
127 #define SDRAM_CFG2_D_INIT               0x00000010
128 #define SDRAM_CFG2_ODT_CFG_MASK         0x00600000
129 #define SDRAM_CFG2_ODT_NEVER            0
130 #define SDRAM_CFG2_ODT_ONLY_WRITE       1
131 #define SDRAM_CFG2_ODT_ONLY_READ        2
132 #define SDRAM_CFG2_ODT_ALWAYS           3
133
134 #define TIMING_CFG_2_CPO_MASK   0x0F800000
135
136 #if defined(CONFIG_SYS_FSL_DDR_VER) && \
137         (CONFIG_SYS_FSL_DDR_VER > FSL_DDR_VER_4_4)
138 #define RD_TO_PRE_MASK          0xf
139 #define RD_TO_PRE_SHIFT         13
140 #define WR_DATA_DELAY_MASK      0xf
141 #define WR_DATA_DELAY_SHIFT     9
142 #else
143 #define RD_TO_PRE_MASK          0x7
144 #define RD_TO_PRE_SHIFT         13
145 #define WR_DATA_DELAY_MASK      0x7
146 #define WR_DATA_DELAY_SHIFT     10
147 #endif
148
149 /* DDR_MD_CNTL */
150 #define MD_CNTL_MD_EN           0x80000000
151 #define MD_CNTL_CS_SEL_CS0      0x00000000
152 #define MD_CNTL_CS_SEL_CS1      0x10000000
153 #define MD_CNTL_CS_SEL_CS2      0x20000000
154 #define MD_CNTL_CS_SEL_CS3      0x30000000
155 #define MD_CNTL_CS_SEL_CS0_CS1  0x40000000
156 #define MD_CNTL_CS_SEL_CS2_CS3  0x50000000
157 #define MD_CNTL_MD_SEL_MR       0x00000000
158 #define MD_CNTL_MD_SEL_EMR      0x01000000
159 #define MD_CNTL_MD_SEL_EMR2     0x02000000
160 #define MD_CNTL_MD_SEL_EMR3     0x03000000
161 #define MD_CNTL_SET_REF         0x00800000
162 #define MD_CNTL_SET_PRE         0x00400000
163 #define MD_CNTL_CKE_CNTL_LOW    0x00100000
164 #define MD_CNTL_CKE_CNTL_HIGH   0x00200000
165 #define MD_CNTL_WRCW            0x00080000
166 #define MD_CNTL_MD_VALUE(x)     (x & 0x0000FFFF)
167 #define MD_CNTL_CS_SEL(x)       (((x) & 0x7) << 28)
168 #define MD_CNTL_MD_SEL(x)       (((x) & 0xf) << 24)
169
170 /* DDR_CDR1 */
171 #define DDR_CDR1_DHC_EN 0x80000000
172 #define DDR_CDR1_ODT_SHIFT      17
173 #define DDR_CDR1_ODT_MASK       0x6
174 #define DDR_CDR2_ODT_MASK       0x1
175 #define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
176 #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
177 #define DDR_CDR2_VREF_OVRD(x)   (0x00008080 | ((((x) - 37) & 0x3F) << 8))
178 #define DDR_CDR2_VREF_TRAIN_EN  0x00000080
179 #define DDR_CDR2_VREF_RANGE_2   0x00000040
180
181 #if (defined(CONFIG_SYS_FSL_DDR_VER) && \
182         (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
183 #ifdef CONFIG_SYS_FSL_DDR3L
184 #define DDR_CDR_ODT_OFF         0x0
185 #define DDR_CDR_ODT_120ohm      0x1
186 #define DDR_CDR_ODT_200ohm      0x2
187 #define DDR_CDR_ODT_75ohm       0x3
188 #define DDR_CDR_ODT_60ohm       0x5
189 #define DDR_CDR_ODT_46ohm       0x7
190 #elif defined(CONFIG_SYS_FSL_DDR4)
191 #define DDR_CDR_ODT_OFF         0x0
192 #define DDR_CDR_ODT_100ohm      0x1
193 #define DDR_CDR_ODT_120OHM      0x2
194 #define DDR_CDR_ODT_80ohm       0x3
195 #define DDR_CDR_ODT_60ohm       0x4
196 #define DDR_CDR_ODT_40ohm       0x5
197 #define DDR_CDR_ODT_50ohm       0x6
198 #define DDR_CDR_ODT_30ohm       0x7
199 #else
200 #define DDR_CDR_ODT_OFF         0x0
201 #define DDR_CDR_ODT_120ohm      0x1
202 #define DDR_CDR_ODT_180ohm      0x2
203 #define DDR_CDR_ODT_75ohm       0x3
204 #define DDR_CDR_ODT_110ohm      0x4
205 #define DDR_CDR_ODT_60hm        0x5
206 #define DDR_CDR_ODT_70ohm       0x6
207 #define DDR_CDR_ODT_47ohm       0x7
208 #endif /* DDR3L */
209 #else
210 #define DDR_CDR_ODT_75ohm       0x0
211 #define DDR_CDR_ODT_55ohm       0x1
212 #define DDR_CDR_ODT_60ohm       0x2
213 #define DDR_CDR_ODT_50ohm       0x3
214 #define DDR_CDR_ODT_150ohm      0x4
215 #define DDR_CDR_ODT_43ohm       0x5
216 #define DDR_CDR_ODT_120ohm      0x6
217 #endif
218
219 #define DDR_INIT_ADDR_EXT_UIA   (1 << 31)
220
221 /* Record of register values computed */
222 typedef struct fsl_ddr_cfg_regs_s {
223         struct {
224                 unsigned int bnds;
225                 unsigned int config;
226                 unsigned int config_2;
227         } cs[CONFIG_CHIP_SELECTS_PER_CTRL];
228         unsigned int timing_cfg_3;
229         unsigned int timing_cfg_0;
230         unsigned int timing_cfg_1;
231         unsigned int timing_cfg_2;
232         unsigned int ddr_sdram_cfg;
233         unsigned int ddr_sdram_cfg_2;
234         unsigned int ddr_sdram_cfg_3;
235         unsigned int ddr_sdram_mode;
236         unsigned int ddr_sdram_mode_2;
237         unsigned int ddr_sdram_mode_3;
238         unsigned int ddr_sdram_mode_4;
239         unsigned int ddr_sdram_mode_5;
240         unsigned int ddr_sdram_mode_6;
241         unsigned int ddr_sdram_mode_7;
242         unsigned int ddr_sdram_mode_8;
243         unsigned int ddr_sdram_mode_9;
244         unsigned int ddr_sdram_mode_10;
245         unsigned int ddr_sdram_mode_11;
246         unsigned int ddr_sdram_mode_12;
247         unsigned int ddr_sdram_mode_13;
248         unsigned int ddr_sdram_mode_14;
249         unsigned int ddr_sdram_mode_15;
250         unsigned int ddr_sdram_mode_16;
251         unsigned int ddr_sdram_md_cntl;
252         unsigned int ddr_sdram_interval;
253         unsigned int ddr_data_init;
254         unsigned int ddr_sdram_clk_cntl;
255         unsigned int ddr_init_addr;
256         unsigned int ddr_init_ext_addr;
257         unsigned int timing_cfg_4;
258         unsigned int timing_cfg_5;
259         unsigned int timing_cfg_6;
260         unsigned int timing_cfg_7;
261         unsigned int timing_cfg_8;
262         unsigned int timing_cfg_9;
263         unsigned int ddr_zq_cntl;
264         unsigned int ddr_wrlvl_cntl;
265         unsigned int ddr_wrlvl_cntl_2;
266         unsigned int ddr_wrlvl_cntl_3;
267         unsigned int ddr_sr_cntr;
268         unsigned int ddr_sdram_rcw_1;
269         unsigned int ddr_sdram_rcw_2;
270         unsigned int ddr_sdram_rcw_3;
271         unsigned int ddr_sdram_rcw_4;
272         unsigned int ddr_sdram_rcw_5;
273         unsigned int ddr_sdram_rcw_6;
274         unsigned int dq_map_0;
275         unsigned int dq_map_1;
276         unsigned int dq_map_2;
277         unsigned int dq_map_3;
278         unsigned int ddr_eor;
279         unsigned int ddr_cdr1;
280         unsigned int ddr_cdr2;
281         unsigned int err_disable;
282         unsigned int err_int_en;
283         unsigned int debug[32];
284 } fsl_ddr_cfg_regs_t;
285
286 typedef struct memctl_options_partial_s {
287         unsigned int all_dimms_ecc_capable;
288         unsigned int all_dimms_tckmax_ps;
289         unsigned int all_dimms_burst_lengths_bitmask;
290         unsigned int all_dimms_registered;
291         unsigned int all_dimms_unbuffered;
292         /*      unsigned int lowest_common_spd_caslat; */
293         unsigned int all_dimms_minimum_trcd_ps;
294 } memctl_options_partial_t;
295
296 #define DDR_DATA_BUS_WIDTH_64 0
297 #define DDR_DATA_BUS_WIDTH_32 1
298 #define DDR_DATA_BUS_WIDTH_16 2
299 #define DDR_CSWL_CS0    0x04000001
300 /*
301  * Generalized parameters for memory controller configuration,
302  * might be a little specific to the FSL memory controller
303  */
304 typedef struct memctl_options_s {
305         /*
306          * Memory organization parameters
307          *
308          * if DIMM is present in the system
309          * where DIMMs are with respect to chip select
310          * where chip selects are with respect to memory boundaries
311          */
312         unsigned int registered_dimm_en;    /* use registered DIMM support */
313
314         /* Options local to a Chip Select */
315         struct cs_local_opts_s {
316                 unsigned int auto_precharge;
317                 unsigned int odt_rd_cfg;
318                 unsigned int odt_wr_cfg;
319                 unsigned int odt_rtt_norm;
320                 unsigned int odt_rtt_wr;
321         } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
322
323         /* Special configurations for chip select */
324         unsigned int memctl_interleaving;
325         unsigned int memctl_interleaving_mode;
326         unsigned int ba_intlv_ctl;
327         unsigned int addr_hash;
328
329         /* Operational mode parameters */
330         unsigned int ecc_mode;   /* Use ECC? */
331         /* Initialize ECC using memory controller? */
332         unsigned int ecc_init_using_memctl;
333         unsigned int dqs_config;        /* Use DQS? maybe only with DDR2? */
334         /* SREN - self-refresh during sleep */
335         unsigned int self_refresh_in_sleep;
336         /* SR_IE - Self-refresh interrupt enable */
337         unsigned int self_refresh_interrupt_en;
338         unsigned int dynamic_power;     /* DYN_PWR */
339         /* memory data width to use (16-bit, 32-bit, 64-bit) */
340         unsigned int data_bus_width;
341         unsigned int burst_length;      /* BL4, OTF and BL8 */
342         /* On-The-Fly Burst Chop enable */
343         unsigned int otf_burst_chop_en;
344         /* mirrior DIMMs for DDR3 */
345         unsigned int mirrored_dimm;
346         unsigned int quad_rank_present;
347         unsigned int ap_en;     /* address parity enable for RDIMM */
348         unsigned int x4_en;     /* enable x4 devices */
349
350         /* Global Timing Parameters */
351         unsigned int cas_latency_override;
352         unsigned int cas_latency_override_value;
353         unsigned int use_derated_caslat;
354         unsigned int additive_latency_override;
355         unsigned int additive_latency_override_value;
356
357         unsigned int clk_adjust;                /* */
358         unsigned int cpo_override;
359         unsigned int write_data_delay;          /* DQS adjust */
360
361         unsigned int cswl_override;
362         unsigned int wrlvl_override;
363         unsigned int wrlvl_sample;              /* Write leveling */
364         unsigned int wrlvl_start;
365         unsigned int wrlvl_ctl_2;
366         unsigned int wrlvl_ctl_3;
367
368         unsigned int half_strength_driver_enable;
369         unsigned int twot_en;
370         unsigned int threet_en;
371         unsigned int bstopre;
372         unsigned int tfaw_window_four_activates_ps;     /* tFAW --  FOUR_ACT */
373
374         /* Rtt impedance */
375         unsigned int rtt_override;              /* rtt_override enable */
376         unsigned int rtt_override_value;        /* that is Rtt_Nom for DDR3 */
377         unsigned int rtt_wr_override_value;     /* this is Rtt_WR for DDR3 */
378
379         /* Automatic self refresh */
380         unsigned int auto_self_refresh_en;
381         unsigned int sr_it;
382         /* ZQ calibration */
383         unsigned int zq_en;
384         /* Write leveling */
385         unsigned int wrlvl_en;
386         /* RCW override for RDIMM */
387         unsigned int rcw_override;
388         unsigned int rcw_1;
389         unsigned int rcw_2;
390         /* control register 1 */
391         unsigned int ddr_cdr1;
392         unsigned int ddr_cdr2;
393
394         unsigned int trwt_override;
395         unsigned int trwt;                      /* read-to-write turnaround */
396 } memctl_options_t;
397
398 phys_size_t fsl_ddr_sdram(void);
399 phys_size_t fsl_ddr_sdram_size(void);
400 phys_size_t fsl_other_ddr_sdram(unsigned long long base,
401                                 unsigned int first_ctrl,
402                                 unsigned int num_ctrls,
403                                 unsigned int dimm_slots_per_ctrl,
404                                 int (*board_need_reset)(void),
405                                 void (*board_reset)(void),
406                                 void (*board_de_reset)(void));
407 extern int fsl_use_spd(void);
408 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
409                              unsigned int ctrl_num, int step);
410 u32 fsl_ddr_get_intl3r(void);
411 void print_ddr_info(unsigned int start_ctrl);
412
413 static void __board_assert_mem_reset(void)
414 {
415 }
416
417 static void __board_deassert_mem_reset(void)
418 {
419 }
420
421 void board_assert_mem_reset(void)
422         __attribute__((weak, alias("__board_assert_mem_reset")));
423
424 void board_deassert_mem_reset(void)
425         __attribute__((weak, alias("__board_deassert_mem_reset")));
426
427 static int __board_need_mem_reset(void)
428 {
429         return 0;
430 }
431
432 int board_need_mem_reset(void)
433         __attribute__((weak, alias("__board_need_mem_reset")));
434
435 #if defined(CONFIG_DEEP_SLEEP)
436 void board_mem_sleep_setup(void);
437 bool is_warm_boot(void);
438 int fsl_dp_resume(void);
439 #endif
440
441 /*
442  * The 85xx boards have a common prototype for fixed_sdram so put the
443  * declaration here.
444  */
445 #ifdef CONFIG_MPC85xx
446 extern phys_size_t fixed_sdram(void);
447 #endif
448
449 #if defined(CONFIG_DDR_ECC)
450 extern void ddr_enable_ecc(unsigned int dram_size);
451 #endif
452
453
454 typedef struct fixed_ddr_parm{
455         int min_freq;
456         int max_freq;
457         fsl_ddr_cfg_regs_t *ddr_settings;
458 } fixed_ddr_parm_t;
459 #endif