2 * Copyright 2008-2016 Freescale Semiconductor, Inc.
3 * Copyright 2017-2018 NXP Semiconductor
5 * SPDX-License-Identifier: GPL-2.0
8 #ifndef DDR2_DIMM_PARAMS_H
9 #define DDR2_DIMM_PARAMS_H
11 #define EDC_DATA_PARITY 1
13 #define EDC_AC_PARITY 4
15 /* Parameters for a DDR dimm computed from the SPD */
16 typedef struct dimm_params_s {
18 /* DIMM organization parameters */
19 char mpart[19]; /* guaranteed null terminated */
22 unsigned int die_density;
23 unsigned long long rank_density;
24 unsigned long long capacity;
25 unsigned int data_width;
26 unsigned int primary_sdram_width;
27 unsigned int ec_sdram_width;
28 unsigned int registered_dimm;
29 unsigned int package_3ds; /* number of dies in 3DS DIMM */
30 unsigned int device_width; /* x4, x8, x16 components */
32 /* SDRAM device parameters */
33 unsigned int n_row_addr;
34 unsigned int n_col_addr;
35 unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */
36 #ifdef CONFIG_SYS_FSL_DDR4
37 unsigned int bank_addr_bits;
38 unsigned int bank_group_bits;
40 unsigned int n_banks_per_sdram_device;
42 unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */
43 unsigned int row_density;
45 /* used in computing base address of DIMMs */
46 unsigned long long base_address;
48 unsigned int mirrored_dimm; /* only for ddr3 */
50 /* DIMM timing parameters */
52 int mtb_ps; /* medium timebase ps */
53 int ftb_10th_ps; /* fine timebase, in 1/10 ps */
54 int taa_ps; /* minimum CAS latency time */
55 int tfaw_ps; /* four active window delay */
59 * The range for these are 1000-10000 so a short should be sufficient
62 int tckmin_x_minus_1_ps;
63 int tckmin_x_minus_2_ps;
66 /* SPD-defined CAS latencies */
67 unsigned int caslat_x;
68 unsigned int caslat_x_minus_1;
69 unsigned int caslat_x_minus_2;
71 unsigned int caslat_lowest_derated; /* Derated CAS latency */
73 /* basic timing parameters */
78 #ifdef CONFIG_SYS_FSL_DDR4
87 int twr_ps; /* maximum = 63750 ps */
88 int trfc_ps; /* max = 255 ns + 256 ns + .75 ns
90 int trrd_ps; /* maximum = 63750 ps */
91 int twtr_ps; /* maximum = 63750 ps */
92 int trtp_ps; /* byte 38, spd->trtp */
95 int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
100 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
101 int tis_ps; /* byte 32, spd->ca_setup */
102 int tih_ps; /* byte 33, spd->ca_hold */
103 int tds_ps; /* byte 34, spd->data_setup */
104 int tdh_ps; /* byte 35, spd->data_hold */
105 int tdqsq_max_ps; /* byte 44, spd->tdqsq */
106 int tqhs_ps; /* byte 45, spd->tqhs */
110 unsigned char rcw[16]; /* Register Control Word 0-15 */
111 #ifdef CONFIG_SYS_FSL_DDR4
112 unsigned int dq_mapping[18];
113 unsigned int dq_mapping_ors;
117 unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
118 const generic_spd_eeprom_t *spd,
119 dimm_params_t *pdimm,
120 unsigned int dimm_number);