Merge git://git.denx.de/u-boot-usb
[platform/kernel/u-boot.git] / include / fsl_ddr.h
1 /*
2  * Copyright 2008-2014 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * Version 2 as published by the Free Software Foundation.
7  */
8
9 #ifndef FSL_DDR_MAIN_H
10 #define FSL_DDR_MAIN_H
11
12 #include <fsl_ddrc_version.h>
13 #include <fsl_ddr_sdram.h>
14 #include <fsl_ddr_dimm_params.h>
15
16 #include <common_timing_params.h>
17
18 #ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
19 /* All controllers are for main memory */
20 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS       CONFIG_NUM_DDR_CONTROLLERS
21 #endif
22
23 #ifdef CONFIG_SYS_FSL_DDR_LE
24 #define ddr_in32(a)     in_le32(a)
25 #define ddr_out32(a, v) out_le32(a, v)
26 #define ddr_setbits32(a, v)     setbits_le32(a, v)
27 #define ddr_clrbits32(a, v)     clrbits_le32(a, v)
28 #define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set)
29 #else
30 #define ddr_in32(a)     in_be32(a)
31 #define ddr_out32(a, v) out_be32(a, v)
32 #define ddr_setbits32(a, v)     setbits_be32(a, v)
33 #define ddr_clrbits32(a, v)     clrbits_be32(a, v)
34 #define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set)
35 #endif
36
37 #define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR
38
39 u32 fsl_ddr_get_version(void);
40
41 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
42 /*
43  * Bind the main DDR setup driver's generic names
44  * to this specific DDR technology.
45  */
46 static __inline__ int
47 compute_dimm_parameters(const unsigned int ctrl_num,
48                         const generic_spd_eeprom_t *spd,
49                         dimm_params_t *pdimm,
50                         unsigned int dimm_number)
51 {
52         return ddr_compute_dimm_parameters(ctrl_num, spd, pdimm, dimm_number);
53 }
54 #endif
55
56 /*
57  * Data Structures
58  *
59  * All data structures have to be on the stack
60  */
61 #define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS
62 #define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
63
64 typedef struct {
65         generic_spd_eeprom_t
66            spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
67         struct dimm_params_s
68            dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
69         memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
70         common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
71         fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];
72         unsigned int first_ctrl;
73         unsigned int num_ctrls;
74         unsigned long long mem_base;
75         unsigned int dimm_slots_per_ctrl;
76         int (*board_need_mem_reset)(void);
77         void (*board_mem_reset)(void);
78         void (*board_mem_de_reset)(void);
79 } fsl_ddr_info_t;
80
81 /* Compute steps */
82 #define STEP_GET_SPD                 (1 << 0)
83 #define STEP_COMPUTE_DIMM_PARMS      (1 << 1)
84 #define STEP_COMPUTE_COMMON_PARMS    (1 << 2)
85 #define STEP_GATHER_OPTS             (1 << 3)
86 #define STEP_ASSIGN_ADDRESSES        (1 << 4)
87 #define STEP_COMPUTE_REGS            (1 << 5)
88 #define STEP_PROGRAM_REGS            (1 << 6)
89 #define STEP_ALL                     0xFFF
90
91 unsigned long long
92 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
93                                        unsigned int size_only);
94 const char *step_to_string(unsigned int step);
95
96 unsigned int compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
97                                const memctl_options_t *popts,
98                                fsl_ddr_cfg_regs_t *ddr,
99                                const common_timing_params_t *common_dimm,
100                                const dimm_params_t *dimm_parameters,
101                                unsigned int dbw_capacity_adjust,
102                                unsigned int size_only);
103 unsigned int compute_lowest_common_dimm_parameters(
104                                 const unsigned int ctrl_num,
105                                 const dimm_params_t *dimm_params,
106                                 common_timing_params_t *outpdimm,
107                                 unsigned int number_of_dimms);
108 unsigned int populate_memctl_options(int all_dimms_registered,
109                                 memctl_options_t *popts,
110                                 dimm_params_t *pdimm,
111                                 unsigned int ctrl_num);
112 void check_interleaving_options(fsl_ddr_info_t *pinfo);
113
114 unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk);
115 unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num);
116 unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos);
117 void fsl_ddr_set_lawbar(
118                 const common_timing_params_t *memctl_common_params,
119                 unsigned int memctl_interleaved,
120                 unsigned int ctrl_num);
121 void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
122                                  unsigned int last_ctrl);
123
124 int fsl_ddr_interactive_env_var_exists(void);
125 unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);
126 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
127                      unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
128
129 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
130 unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
131 void board_add_ram_info(int use_default);
132
133 /* processor specific function */
134 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
135                                    unsigned int ctrl_num, int step);
136
137 /* board specific function */
138 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
139                         unsigned int controller_number,
140                         unsigned int dimm_number);
141 #endif