include/fsl_ddr.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright 2008-2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef FSL_DDR_MAIN_H
   7 #define FSL_DDR_MAIN_H
   8
   9 #include <fsl_ddrc_version.h>
  10 #include <fsl_ddr_sdram.h>
  11 #include <fsl_ddr_dimm_params.h>
  12
  13 #include <common_timing_params.h>
  14
  15 struct cmd_tbl;
  16
  17 #ifdef CONFIG_SYS_FSL_DDR_LE
  18 #define ddr_in32(a)     in_le32(a)
  19 #define ddr_out32(a, v) out_le32(a, v)
  20 #define ddr_setbits32(a, v)     setbits_le32(a, v)
  21 #define ddr_clrbits32(a, v)     clrbits_le32(a, v)
  22 #define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set)
  23 #else
  24 #define ddr_in32(a)     in_be32(a)
  25 #define ddr_out32(a, v) out_be32(a, v)
  26 #define ddr_setbits32(a, v)     setbits_be32(a, v)
  27 #define ddr_clrbits32(a, v)     clrbits_be32(a, v)
  28 #define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set)
  29 #endif
  30
  31 u32 fsl_ddr_get_version(unsigned int ctrl_num);
  32
  33 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
  34 /*
  35  * Bind the main DDR setup driver's generic names
  36  * to this specific DDR technology.
  37  */
  38 static __inline__ int
  39 compute_dimm_parameters(const unsigned int ctrl_num,
  40                         const generic_spd_eeprom_t *spd,
  41                         dimm_params_t *pdimm,
  42                         unsigned int dimm_number)
  43 {
  44         return ddr_compute_dimm_parameters(ctrl_num, spd, pdimm, dimm_number);
  45 }
  46 #endif
  47
  48 /*
  49  * Data Structures
  50  *
  51  * All data structures have to be on the stack
  52  */
  53
  54 typedef struct {
  55         generic_spd_eeprom_t
  56            spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
  57         struct dimm_params_s
  58            dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
  59         memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
  60         common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
  61         fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];
  62         unsigned int first_ctrl;
  63         unsigned int num_ctrls;
  64         unsigned long long mem_base;
  65         unsigned int dimm_slots_per_ctrl;
  66         int (*board_need_mem_reset)(void);
  67         void (*board_mem_reset)(void);
  68         void (*board_mem_de_reset)(void);
  69 } fsl_ddr_info_t;
  70
  71 /* Compute steps */
  72 #define STEP_GET_SPD                 (1 << 0)
  73 #define STEP_COMPUTE_DIMM_PARMS      (1 << 1)
  74 #define STEP_COMPUTE_COMMON_PARMS    (1 << 2)
  75 #define STEP_GATHER_OPTS             (1 << 3)
  76 #define STEP_ASSIGN_ADDRESSES        (1 << 4)
  77 #define STEP_COMPUTE_REGS            (1 << 5)
  78 #define STEP_PROGRAM_REGS            (1 << 6)
  79 #define STEP_ALL                     0xFFF
  80
  81 unsigned long long
  82 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
  83                                        unsigned int size_only);
  84 const char *step_to_string(unsigned int step);
  85
  86 unsigned int compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
  87                                const memctl_options_t *popts,
  88                                fsl_ddr_cfg_regs_t *ddr,
  89                                const common_timing_params_t *common_dimm,
  90                                const dimm_params_t *dimm_parameters,
  91                                unsigned int dbw_capacity_adjust,
  92                                unsigned int size_only);
  93 unsigned int compute_lowest_common_dimm_parameters(
  94                                 const unsigned int ctrl_num,
  95                                 const dimm_params_t *dimm_params,
  96                                 common_timing_params_t *outpdimm,
  97                                 unsigned int number_of_dimms);
  98 unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
  99                                 memctl_options_t *popts,
 100                                 dimm_params_t *pdimm,
 101                                 unsigned int ctrl_num);
 102 void check_interleaving_options(fsl_ddr_info_t *pinfo);
 103
 104 unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk);
 105 unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num);
 106 unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos);
 107 void fsl_ddr_set_lawbar(
 108                 const common_timing_params_t *memctl_common_params,
 109                 unsigned int memctl_interleaved,
 110                 unsigned int ctrl_num);
 111 void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
 112                                  unsigned int last_ctrl);
 113
 114 int fsl_ddr_interactive_env_var_exists(void);
 115 unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);
 116 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 117                      unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
 118
 119 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
 120 unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
 121 void board_add_ram_info(int use_default);
 122
 123 /* processor specific function */
 124 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 125                                    unsigned int ctrl_num, int step);
 126 void remove_unused_controllers(fsl_ddr_info_t *info);
 127
 128 /* board specific function */
 129 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 130                         unsigned int controller_number,
 131                         unsigned int dimm_number);
 132 void update_spd_address(unsigned int ctrl_num,
 133                         unsigned int slot,
 134                         unsigned int *addr);
 135
 136 void erratum_a009942_check_cpo(void);
 137 #endif