Merge branch 'master' of git://git.denx.de/u-boot-arm
[platform/kernel/u-boot.git] / include / fsl_ddr.h
1 /*
2  * Copyright 2008-2011 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * Version 2 as published by the Free Software Foundation.
7  */
8
9 #ifndef FSL_DDR_MAIN_H
10 #define FSL_DDR_MAIN_H
11
12 #include <fsl_ddr_sdram.h>
13 #include <fsl_ddr_dimm_params.h>
14
15 #include <common_timing_params.h>
16
17 #ifdef CONFIG_SYS_FSL_DDR_LE
18 #define ddr_in32(a)     in_le32(a)
19 #define ddr_out32(a, v) out_le32(a, v)
20 #else
21 #define ddr_in32(a)     in_be32(a)
22 #define ddr_out32(a, v) out_be32(a, v)
23 #endif
24
25 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
26 /*
27  * Bind the main DDR setup driver's generic names
28  * to this specific DDR technology.
29  */
30 static __inline__ int
31 compute_dimm_parameters(const generic_spd_eeprom_t *spd,
32                         dimm_params_t *pdimm,
33                         unsigned int dimm_number)
34 {
35         return ddr_compute_dimm_parameters(spd, pdimm, dimm_number);
36 }
37 #endif
38
39 /*
40  * Data Structures
41  *
42  * All data structures have to be on the stack
43  */
44 #define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS
45 #define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
46
47 typedef struct {
48         generic_spd_eeprom_t
49            spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
50         struct dimm_params_s
51            dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
52         memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
53         common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
54         fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];
55 } fsl_ddr_info_t;
56
57 /* Compute steps */
58 #define STEP_GET_SPD                 (1 << 0)
59 #define STEP_COMPUTE_DIMM_PARMS      (1 << 1)
60 #define STEP_COMPUTE_COMMON_PARMS    (1 << 2)
61 #define STEP_GATHER_OPTS             (1 << 3)
62 #define STEP_ASSIGN_ADDRESSES        (1 << 4)
63 #define STEP_COMPUTE_REGS            (1 << 5)
64 #define STEP_PROGRAM_REGS            (1 << 6)
65 #define STEP_ALL                     0xFFF
66
67 unsigned long long
68 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
69                                        unsigned int size_only);
70
71 const char *step_to_string(unsigned int step);
72
73 unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts,
74                                fsl_ddr_cfg_regs_t *ddr,
75                                const common_timing_params_t *common_dimm,
76                                const dimm_params_t *dimm_parameters,
77                                unsigned int dbw_capacity_adjust,
78                                unsigned int size_only);
79 unsigned int compute_lowest_common_dimm_parameters(
80                                 const dimm_params_t *dimm_params,
81                                 common_timing_params_t *outpdimm,
82                                 unsigned int number_of_dimms);
83 unsigned int populate_memctl_options(int all_dimms_registered,
84                                 memctl_options_t *popts,
85                                 dimm_params_t *pdimm,
86                                 unsigned int ctrl_num);
87 void check_interleaving_options(fsl_ddr_info_t *pinfo);
88
89 unsigned int mclk_to_picos(unsigned int mclk);
90 unsigned int get_memory_clk_period_ps(void);
91 unsigned int picos_to_mclk(unsigned int picos);
92 void fsl_ddr_set_lawbar(
93                 const common_timing_params_t *memctl_common_params,
94                 unsigned int memctl_interleaved,
95                 unsigned int ctrl_num);
96
97 int fsl_ddr_interactive_env_var_exists(void);
98 unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);
99 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
100                            unsigned int ctrl_num);
101
102 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
103 unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
104 void board_add_ram_info(int use_default);
105
106 /* processor specific function */
107 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
108                                    unsigned int ctrl_num, int step);
109
110 /* board specific function */
111 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
112                         unsigned int controller_number,
113                         unsigned int dimm_number);
114 #endif