include/fsl_ddr.h

   1 /*
   2  * Copyright 2008-2014 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #ifndef FSL_DDR_MAIN_H
  10 #define FSL_DDR_MAIN_H
  11
  12 #include <fsl_ddrc_version.h>
  13 #include <fsl_ddr_sdram.h>
  14 #include <fsl_ddr_dimm_params.h>
  15
  16 #include <common_timing_params.h>
  17
  18 #ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
  19 /* All controllers are for main memory */
  20 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS       CONFIG_NUM_DDR_CONTROLLERS
  21 #endif
  22
  23 #ifdef CONFIG_SYS_FSL_DDR_LE
  24 #define ddr_in32(a)     in_le32(a)
  25 #define ddr_out32(a, v) out_le32(a, v)
  26 #else
  27 #define ddr_in32(a)     in_be32(a)
  28 #define ddr_out32(a, v) out_be32(a, v)
  29 #endif
  30
  31 #define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR
  32
  33 u32 fsl_ddr_get_version(void);
  34
  35 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
  36 /*
  37  * Bind the main DDR setup driver's generic names
  38  * to this specific DDR technology.
  39  */
  40 static __inline__ int
  41 compute_dimm_parameters(const generic_spd_eeprom_t *spd,
  42                         dimm_params_t *pdimm,
  43                         unsigned int dimm_number)
  44 {
  45         return ddr_compute_dimm_parameters(spd, pdimm, dimm_number);
  46 }
  47 #endif
  48
  49 /*
  50  * Data Structures
  51  *
  52  * All data structures have to be on the stack
  53  */
  54 #define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS
  55 #define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
  56
  57 typedef struct {
  58         generic_spd_eeprom_t
  59            spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
  60         struct dimm_params_s
  61            dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
  62         memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
  63         common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
  64         fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];
  65         unsigned int first_ctrl;
  66         unsigned int num_ctrls;
  67         unsigned long long mem_base;
  68         unsigned int dimm_slots_per_ctrl;
  69         int (*board_need_mem_reset)(void);
  70         void (*board_mem_reset)(void);
  71         void (*board_mem_de_reset)(void);
  72 } fsl_ddr_info_t;
  73
  74 /* Compute steps */
  75 #define STEP_GET_SPD                 (1 << 0)
  76 #define STEP_COMPUTE_DIMM_PARMS      (1 << 1)
  77 #define STEP_COMPUTE_COMMON_PARMS    (1 << 2)
  78 #define STEP_GATHER_OPTS             (1 << 3)
  79 #define STEP_ASSIGN_ADDRESSES        (1 << 4)
  80 #define STEP_COMPUTE_REGS            (1 << 5)
  81 #define STEP_PROGRAM_REGS            (1 << 6)
  82 #define STEP_ALL                     0xFFF
  83
  84 unsigned long long
  85 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
  86                                        unsigned int size_only);
  87 const char *step_to_string(unsigned int step);
  88
  89 unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts,
  90                                fsl_ddr_cfg_regs_t *ddr,
  91                                const common_timing_params_t *common_dimm,
  92                                const dimm_params_t *dimm_parameters,
  93                                unsigned int dbw_capacity_adjust,
  94                                unsigned int size_only);
  95 unsigned int compute_lowest_common_dimm_parameters(
  96                                 const dimm_params_t *dimm_params,
  97                                 common_timing_params_t *outpdimm,
  98                                 unsigned int number_of_dimms);
  99 unsigned int populate_memctl_options(int all_dimms_registered,
 100                                 memctl_options_t *popts,
 101                                 dimm_params_t *pdimm,
 102                                 unsigned int ctrl_num);
 103 void check_interleaving_options(fsl_ddr_info_t *pinfo);
 104
 105 unsigned int mclk_to_picos(unsigned int mclk);
 106 unsigned int get_memory_clk_period_ps(void);
 107 unsigned int picos_to_mclk(unsigned int picos);
 108 void fsl_ddr_set_lawbar(
 109                 const common_timing_params_t *memctl_common_params,
 110                 unsigned int memctl_interleaved,
 111                 unsigned int ctrl_num);
 112
 113 int fsl_ddr_interactive_env_var_exists(void);
 114 unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);
 115 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 116                      unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
 117
 118 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
 119 unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
 120 void board_add_ram_info(int use_default);
 121
 122 /* processor specific function */
 123 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 124                                    unsigned int ctrl_num, int step);
 125
 126 /* board specific function */
 127 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 128                         unsigned int controller_number,
 129                         unsigned int dimm_number);
 130 #endif