Merge git://git.denx.de/u-boot-fsl-qoriq
[platform/kernel/u-boot.git] / include / fsl_ddr.h
1 /*
2  * Copyright 2008-2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0
5  */
6
7 #ifndef FSL_DDR_MAIN_H
8 #define FSL_DDR_MAIN_H
9
10 #include <fsl_ddrc_version.h>
11 #include <fsl_ddr_sdram.h>
12 #include <fsl_ddr_dimm_params.h>
13
14 #include <common_timing_params.h>
15
16 #ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
17 /* All controllers are for main memory */
18 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS       CONFIG_SYS_NUM_DDR_CTLRS
19 #endif
20
21 #ifdef CONFIG_SYS_FSL_DDR_LE
22 #define ddr_in32(a)     in_le32(a)
23 #define ddr_out32(a, v) out_le32(a, v)
24 #define ddr_setbits32(a, v)     setbits_le32(a, v)
25 #define ddr_clrbits32(a, v)     clrbits_le32(a, v)
26 #define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set)
27 #else
28 #define ddr_in32(a)     in_be32(a)
29 #define ddr_out32(a, v) out_be32(a, v)
30 #define ddr_setbits32(a, v)     setbits_be32(a, v)
31 #define ddr_clrbits32(a, v)     clrbits_be32(a, v)
32 #define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set)
33 #endif
34
35 u32 fsl_ddr_get_version(unsigned int ctrl_num);
36
37 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
38 /*
39  * Bind the main DDR setup driver's generic names
40  * to this specific DDR technology.
41  */
42 static __inline__ int
43 compute_dimm_parameters(const unsigned int ctrl_num,
44                         const generic_spd_eeprom_t *spd,
45                         dimm_params_t *pdimm,
46                         unsigned int dimm_number)
47 {
48         return ddr_compute_dimm_parameters(ctrl_num, spd, pdimm, dimm_number);
49 }
50 #endif
51
52 /*
53  * Data Structures
54  *
55  * All data structures have to be on the stack
56  */
57 #define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
58
59 typedef struct {
60         generic_spd_eeprom_t
61            spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
62         struct dimm_params_s
63            dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
64         memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
65         common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
66         fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];
67         unsigned int first_ctrl;
68         unsigned int num_ctrls;
69         unsigned long long mem_base;
70         unsigned int dimm_slots_per_ctrl;
71         int (*board_need_mem_reset)(void);
72         void (*board_mem_reset)(void);
73         void (*board_mem_de_reset)(void);
74 } fsl_ddr_info_t;
75
76 /* Compute steps */
77 #define STEP_GET_SPD                 (1 << 0)
78 #define STEP_COMPUTE_DIMM_PARMS      (1 << 1)
79 #define STEP_COMPUTE_COMMON_PARMS    (1 << 2)
80 #define STEP_GATHER_OPTS             (1 << 3)
81 #define STEP_ASSIGN_ADDRESSES        (1 << 4)
82 #define STEP_COMPUTE_REGS            (1 << 5)
83 #define STEP_PROGRAM_REGS            (1 << 6)
84 #define STEP_ALL                     0xFFF
85
86 unsigned long long
87 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
88                                        unsigned int size_only);
89 const char *step_to_string(unsigned int step);
90
91 unsigned int compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
92                                const memctl_options_t *popts,
93                                fsl_ddr_cfg_regs_t *ddr,
94                                const common_timing_params_t *common_dimm,
95                                const dimm_params_t *dimm_parameters,
96                                unsigned int dbw_capacity_adjust,
97                                unsigned int size_only);
98 unsigned int compute_lowest_common_dimm_parameters(
99                                 const unsigned int ctrl_num,
100                                 const dimm_params_t *dimm_params,
101                                 common_timing_params_t *outpdimm,
102                                 unsigned int number_of_dimms);
103 unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
104                                 memctl_options_t *popts,
105                                 dimm_params_t *pdimm,
106                                 unsigned int ctrl_num);
107 void check_interleaving_options(fsl_ddr_info_t *pinfo);
108
109 unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk);
110 unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num);
111 unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos);
112 void fsl_ddr_set_lawbar(
113                 const common_timing_params_t *memctl_common_params,
114                 unsigned int memctl_interleaved,
115                 unsigned int ctrl_num);
116 void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
117                                  unsigned int last_ctrl);
118
119 int fsl_ddr_interactive_env_var_exists(void);
120 unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);
121 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
122                      unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
123
124 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
125 unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
126 void board_add_ram_info(int use_default);
127
128 /* processor specific function */
129 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
130                                    unsigned int ctrl_num, int step);
131 void remove_unused_controllers(fsl_ddr_info_t *info);
132
133 /* board specific function */
134 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
135                         unsigned int controller_number,
136                         unsigned int dimm_number);
137 void update_spd_address(unsigned int ctrl_num,
138                         unsigned int slot,
139                         unsigned int *addr);
140
141 void erratum_a009942_check_cpo(void);
142 #endif