1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2014 Freescale Semiconductor
11 #define MC_CCSR_BASE_ADDR \
12 ((struct mc_ccsr_registers __iomem *)0x8340000)
14 #define GCR1_P1_STOP BIT(31)
15 #define GCR1_P2_STOP BIT(30)
16 #define GCR1_P1_DE_RST BIT(23)
17 #define GCR1_P2_DE_RST BIT(22)
18 #define GCR1_M1_DE_RST BIT(15)
19 #define GCR1_M2_DE_RST BIT(14)
20 #define GCR1_M_ALL_DE_RST (GCR1_M1_DE_RST | GCR1_M2_DE_RST)
21 #define GSR_FS_MASK 0x3fffffff
23 #define SOC_MC_PORTALS_BASE_ADDR ((void __iomem *)0x00080C000000)
24 #define SOC_QBMAN_PORTALS_BASE_ADDR ((void __iomem *)0x000818000000)
25 #define SOC_MC_PORTAL_STRIDE 0x10000
27 #define SOC_MC_PORTAL_ADDR(_portal_id) \
28 ((void __iomem *)((uintptr_t)SOC_MC_PORTALS_BASE_ADDR + \
29 (_portal_id) * SOC_MC_PORTAL_STRIDE))
31 #define MC_PORTAL_OFFSET_TO_PORTAL_ID(_portal_offset) \
32 ((_portal_offset) / SOC_MC_PORTAL_STRIDE)
34 struct mc_ccsr_registers {
54 void fdt_fsl_mc_fixup_iommu_map_entry(void *blob);
55 int get_mc_boot_status(void);
56 int get_dpl_apply_status(void);
57 #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
58 int get_aiop_apply_status(void);
60 u64 mc_get_dram_addr(void);
61 unsigned long mc_get_dram_block_size(void);
62 int fsl_mc_ldpaa_init(bd_t *bis);
63 int fsl_mc_ldpaa_exit(bd_t *bd);
64 void mc_env_boot(void);