1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
7 #include <linux/types.h> /* for ulong typedef */
12 #ifndef CONFIG_MAX_FPGA_DEVICES
13 #define CONFIG_MAX_FPGA_DEVICES 5
16 /* fpga_xxxx function return value definitions */
17 #define FPGA_SUCCESS 0
20 /* device numbers must be non-negative */
21 #define FPGA_INVALID_DEVICE -1
23 #define FPGA_ENC_USR_KEY 1
24 #define FPGA_NO_ENC_OR_NO_AUTH 2
26 /* root data type defintions */
27 typedef enum { /* typedef fpga_type */
28 fpga_min_type, /* range check value */
29 fpga_xilinx, /* Xilinx Family) */
30 fpga_altera, /* unimplemented */
31 fpga_lattice, /* Lattice family */
32 fpga_undefined /* invalid range check value */
33 } fpga_type; /* end, typedef fpga_type */
35 typedef struct { /* typedef fpga_desc */
36 fpga_type devtype; /* switch value to select sub-functions */
37 void *devdesc; /* real device descriptor */
38 } fpga_desc; /* end, typedef fpga_desc */
40 typedef struct { /* typedef fpga_desc */
41 unsigned int blocksize;
48 struct fpga_secure_info {
60 /* root function definitions */
62 int fpga_add(fpga_type devtype, void *desc);
64 const fpga_desc *const fpga_get_desc(int devnum);
65 int fpga_is_partial_data(int devnum, size_t img_len);
66 int fpga_load(int devnum, const void *buf, size_t bsize,
67 bitstream_type bstype);
68 int fpga_fsload(int devnum, const void *buf, size_t size,
69 fpga_fs_info *fpga_fsinfo);
70 int fpga_loads(int devnum, const void *buf, size_t size,
71 struct fpga_secure_info *fpga_sec_info);
72 int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
73 bitstream_type bstype);
74 int fpga_dump(int devnum, const void *buf, size_t bsize);
75 int fpga_info(int devnum);
76 const fpga_desc *const fpga_validate(int devnum, const void *buf,
77 size_t bsize, char *fn);