2 * Copyright 2009-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/types.h>
12 #include <asm/fsl_enet.h>
43 #ifdef CONFIG_SYS_FMAN_V3
44 #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000)
45 #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
46 #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000)
47 #define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfd000)
49 #define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xe1120)
50 #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000)
53 #define DEFAULT_FM_MDIO_NAME "FSL_MDIO0"
54 #define DEFAULT_FM_TGEC_MDIO_NAME "FM_TGEC_MDIO"
56 /* Fman ethernet info struct */
57 #define FM_ETH_INFO_INITIALIZER(idx, pregs) \
59 .phy_regs = (void *)pregs, \
60 .enet_if = PHY_INTERFACE_MODE_NONE, \
62 #ifdef CONFIG_SYS_FMAN_V3
63 #define FM_DTSEC_INFO_INITIALIZER(idx, n) \
65 FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC_MDIO_ADDR) \
68 .type = FM_ETH_1G_E, \
69 .port = FM##idx##_DTSEC##n, \
70 .rx_port_id = RX_PORT_1G_BASE + n - 1, \
71 .tx_port_id = TX_PORT_1G_BASE + n - 1, \
72 .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
73 offsetof(struct ccsr_fman, memac[n-1]),\
76 #define FM_TGEC_INFO_INITIALIZER(idx, n) \
78 FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \
81 .type = FM_ETH_10G_E, \
82 .port = FM##idx##_10GEC##n, \
83 .rx_port_id = RX_PORT_10G_BASE + n - 1, \
84 .tx_port_id = TX_PORT_10G_BASE + n - 1, \
85 .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
86 offsetof(struct ccsr_fman, memac[n-1+8]),\
89 #define FM_DTSEC_INFO_INITIALIZER(idx, n) \
91 FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR) \
94 .type = FM_ETH_1G_E, \
95 .port = FM##idx##_DTSEC##n, \
96 .rx_port_id = RX_PORT_1G_BASE + n - 1, \
97 .tx_port_id = TX_PORT_1G_BASE + n - 1, \
98 .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
99 offsetof(struct ccsr_fman, mac_1g[n-1]),\
102 #define FM_TGEC_INFO_INITIALIZER(idx, n) \
104 FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
107 .type = FM_ETH_10G_E, \
108 .port = FM##idx##_10GEC##n, \
109 .rx_port_id = RX_PORT_10G_BASE + n - 1, \
110 .tx_port_id = TX_PORT_10G_BASE + n - 1, \
111 .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
112 offsetof(struct ccsr_fman, mac_10g[n-1]),\
124 enum fm_eth_type type;
126 phy_interface_t enet_if;
131 struct tgec_mdio_info {
132 struct tgec_mdio_controller *regs;
136 struct memac_mdio_info {
137 struct memac_mdio_controller *regs;
141 int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info);
142 int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info);
144 int fm_standard_init(bd_t *bis);
145 void fman_enet_init(void);
146 void fdt_fixup_fman_ethernet(void *fdt);
147 phy_interface_t fm_info_get_enet_if(enum fm_port port);
148 void fm_info_set_phy_address(enum fm_port port, int address);
149 int fm_info_get_phy_address(enum fm_port port);
150 void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus);
151 void fm_disable_port(enum fm_port port);
152 void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port,
153 unsigned int port_num, int phy_base_addr);
154 int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr,
155 unsigned int port_num, unsigned regnum);