1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2009-2012 Freescale Semiconductor, Inc.
12 #include <asm/types.h>
45 /* Historically, on FMan v3 platforms, the first MDIO bus has been used for
46 * Clause 22 PHYs and the second MDIO bus for 10G Clause 45 PHYs (thus the
49 * On LS1046A-FRWY, the QSGMII PHY is connected to the second MDIO bus,
50 * and no TGEC ports are present on-board.
52 #ifdef CONFIG_SYS_FMAN_V3
53 #ifdef CONFIG_TARGET_LS1046AFRWY
54 #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfd000)
56 #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfc000)
58 #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfd000)
59 #if (CFG_SYS_NUM_FMAN == 2)
60 #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM2_ADDR + 0xfc000)
61 #define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM2_ADDR + 0xfd000)
64 #define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xe1120)
65 #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xf1000)
68 #define DEFAULT_FM_MDIO_NAME "FSL_MDIO0"
69 #define DEFAULT_FM_TGEC_MDIO_NAME "FM_TGEC_MDIO"
71 /* Fman ethernet info struct */
72 #define FM_ETH_INFO_INITIALIZER(idx, pregs) \
74 .phy_regs = (void *)pregs, \
75 .enet_if = PHY_INTERFACE_MODE_NA, \
77 #ifdef CONFIG_SYS_FMAN_V3
78 #define FM_DTSEC_INFO_INITIALIZER(idx, n) \
80 FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC_MDIO_ADDR) \
83 .type = FM_ETH_1G_E, \
84 .port = FM##idx##_DTSEC##n, \
85 .rx_port_id = RX_PORT_1G_BASE + n - 1, \
86 .tx_port_id = TX_PORT_1G_BASE + n - 1, \
87 .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
88 offsetof(struct ccsr_fman, memac[n-1]),\
91 #ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
92 #define FM_TGEC_INFO_INITIALIZER(idx, n) \
94 FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
97 .type = FM_ETH_10G_E, \
98 .port = FM##idx##_10GEC##n, \
99 .rx_port_id = RX_PORT_10G_BASE2 + n - 1, \
100 .tx_port_id = TX_PORT_10G_BASE2 + n - 1, \
101 .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
102 offsetof(struct ccsr_fman, memac[n-1]),\
105 #if (CFG_SYS_NUM_FMAN == 2)
106 #define FM_TGEC_INFO_INITIALIZER(idx, n) \
108 FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \
111 .type = FM_ETH_10G_E, \
112 .port = FM##idx##_10GEC##n, \
113 .rx_port_id = RX_PORT_10G_BASE + n - 1, \
114 .tx_port_id = TX_PORT_10G_BASE + n - 1, \
115 .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
116 offsetof(struct ccsr_fman, memac[n-1+8]),\
119 #define FM_TGEC_INFO_INITIALIZER(idx, n) \
121 FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
124 .type = FM_ETH_10G_E, \
125 .port = FM##idx##_10GEC##n, \
126 .rx_port_id = RX_PORT_10G_BASE + n - 1, \
127 .tx_port_id = TX_PORT_10G_BASE + n - 1, \
128 .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
129 offsetof(struct ccsr_fman, memac[n-1+8]),\
134 #if (CFG_SYS_NUM_FM1_10GEC >= 3)
135 #define FM_TGEC_INFO_INITIALIZER2(idx, n) \
137 FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
140 .type = FM_ETH_10G_E, \
141 .port = FM##idx##_10GEC##n, \
142 .rx_port_id = RX_PORT_10G_BASE2 + n - 3, \
143 .tx_port_id = TX_PORT_10G_BASE2 + n - 3, \
144 .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
145 offsetof(struct ccsr_fman, memac[n-1-2]),\
150 #define FM_DTSEC_INFO_INITIALIZER(idx, n) \
152 FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR) \
155 .type = FM_ETH_1G_E, \
156 .port = FM##idx##_DTSEC##n, \
157 .rx_port_id = RX_PORT_1G_BASE + n - 1, \
158 .tx_port_id = TX_PORT_1G_BASE + n - 1, \
159 .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
160 offsetof(struct ccsr_fman, mac_1g[n-1]),\
163 #define FM_TGEC_INFO_INITIALIZER(idx, n) \
165 FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
168 .type = FM_ETH_10G_E, \
169 .port = FM##idx##_10GEC##n, \
170 .rx_port_id = RX_PORT_10G_BASE + n - 1, \
171 .tx_port_id = TX_PORT_10G_BASE + n - 1, \
172 .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
173 offsetof(struct ccsr_fman, mac_10g[n-1]),\
185 enum fm_eth_type type;
187 phy_interface_t enet_if;
192 struct tgec_mdio_info {
193 struct tgec_mdio_controller *regs;
197 struct memac_mdio_info {
198 struct memac_mdio_controller *regs;
202 int fm_tgec_mdio_init(struct bd_info *bis, struct tgec_mdio_info *info);
203 int fm_memac_mdio_init(struct bd_info *bis, struct memac_mdio_info *info);
205 int fm_standard_init(struct bd_info *bis);
206 void fman_enet_init(void);
207 void fdt_fixup_fman_ethernet(void *fdt);
208 phy_interface_t fm_info_get_enet_if(enum fm_port port);
209 void fm_info_set_phy_address(enum fm_port port, int address);
210 int fm_info_get_phy_address(enum fm_port port);
211 void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus);
212 void fm_disable_port(enum fm_port port);
213 void fm_enable_port(enum fm_port port);
214 void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port,
215 unsigned int port_num, int phy_base_addr);
216 int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr,
217 unsigned int port_num, unsigned regnum);