include/fm_eth.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2009-2012 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __FM_ETH_H__
   8 #define __FM_ETH_H__
   9
  10 #include <common.h>
  11 #include <phy.h>
  12 #include <asm/types.h>
  13
  14 enum fm_port {
  15         FM1_DTSEC1,
  16         FM1_DTSEC2,
  17         FM1_DTSEC3,
  18         FM1_DTSEC4,
  19         FM1_DTSEC5,
  20         FM1_DTSEC6,
  21         FM1_DTSEC9,
  22         FM1_DTSEC10,
  23         FM1_10GEC1,
  24         FM1_10GEC2,
  25         FM1_10GEC3,
  26         FM1_10GEC4,
  27         FM2_DTSEC1,
  28         FM2_DTSEC2,
  29         FM2_DTSEC3,
  30         FM2_DTSEC4,
  31         FM2_DTSEC5,
  32         FM2_DTSEC6,
  33         FM2_DTSEC9,
  34         FM2_DTSEC10,
  35         FM2_10GEC1,
  36         FM2_10GEC2,
  37         NUM_FM_PORTS,
  38 };
  39
  40 enum fm_eth_type {
  41         FM_ETH_1G_E,
  42         FM_ETH_10G_E,
  43 };
  44
  45 /* Historically, on FMan v3 platforms, the first MDIO bus has been used for
  46  * Clause 22 PHYs and the second MDIO bus for 10G Clause 45 PHYs (thus the
  47  * TGEC name).
  48  *
  49  * On LS1046A-FRWY, the QSGMII PHY is connected to the second MDIO bus,
  50  * and no TGEC ports are present on-board.
  51  */
  52 #ifdef CONFIG_SYS_FMAN_V3
  53 #ifdef CONFIG_TARGET_LS1046AFRWY
  54 #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR  (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
  55 #else
  56 #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR  (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000)
  57 #endif
  58 #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR   (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
  59 #if (CONFIG_SYS_NUM_FMAN == 2)
  60 #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR  (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000)
  61 #define CONFIG_SYS_FM2_TGEC_MDIO_ADDR   (CONFIG_SYS_FSL_FM2_ADDR + 0xfd000)
  62 #endif
  63 #else
  64 #define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xe1120)
  65 #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR   (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000)
  66 #endif
  67
  68 #define DEFAULT_FM_MDIO_NAME "FSL_MDIO0"
  69 #define DEFAULT_FM_TGEC_MDIO_NAME "FM_TGEC_MDIO"
  70
  71 /* Fman ethernet info struct */
  72 #define FM_ETH_INFO_INITIALIZER(idx, pregs) \
  73         .fm             = idx,                                          \
  74         .phy_regs       = (void *)pregs,                                \
  75         .enet_if        = PHY_INTERFACE_MODE_NONE,                      \
  76
  77 #ifdef CONFIG_SYS_FMAN_V3
  78 #define FM_DTSEC_INFO_INITIALIZER(idx, n) \
  79 {                                                                       \
  80         FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC_MDIO_ADDR)    \
  81         .index          = idx,                                          \
  82         .num            = n - 1,                                        \
  83         .type           = FM_ETH_1G_E,                                  \
  84         .port           = FM##idx##_DTSEC##n,                           \
  85         .rx_port_id     = RX_PORT_1G_BASE + n - 1,                      \
  86         .tx_port_id     = TX_PORT_1G_BASE + n - 1,                      \
  87         .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET +             \
  88                                 offsetof(struct ccsr_fman, memac[n-1]),\
  89 }
  90
  91 #ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
  92 #define FM_TGEC_INFO_INITIALIZER(idx, n) \
  93 {                                                                       \
  94         FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR)     \
  95         .index          = idx,                                          \
  96         .num            = n - 1,                                        \
  97         .type           = FM_ETH_10G_E,                                 \
  98         .port           = FM##idx##_10GEC##n,                           \
  99         .rx_port_id     = RX_PORT_10G_BASE2 + n - 1,                    \
 100         .tx_port_id     = TX_PORT_10G_BASE2 + n - 1,                    \
 101         .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET +             \
 102                                  offsetof(struct ccsr_fman, memac[n-1]),\
 103 }
 104 #else
 105 #if (CONFIG_SYS_NUM_FMAN == 2)
 106 #define FM_TGEC_INFO_INITIALIZER(idx, n) \
 107 {                                                                       \
 108         FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR)     \
 109         .index          = idx,                                          \
 110         .num            = n - 1,                                        \
 111         .type           = FM_ETH_10G_E,                                 \
 112         .port           = FM##idx##_10GEC##n,                           \
 113         .rx_port_id     = RX_PORT_10G_BASE + n - 1,                     \
 114         .tx_port_id     = TX_PORT_10G_BASE + n - 1,                     \
 115         .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET +             \
 116                                 offsetof(struct ccsr_fman, memac[n-1+8]),\
 117 }
 118 #else
 119 #define FM_TGEC_INFO_INITIALIZER(idx, n) \
 120 {                                                                       \
 121         FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR)     \
 122         .index          = idx,                                          \
 123         .num            = n - 1,                                        \
 124         .type           = FM_ETH_10G_E,                                 \
 125         .port           = FM##idx##_10GEC##n,                           \
 126         .rx_port_id     = RX_PORT_10G_BASE + n - 1,                     \
 127         .tx_port_id     = TX_PORT_10G_BASE + n - 1,                     \
 128         .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET +             \
 129                                 offsetof(struct ccsr_fman, memac[n-1+8]),\
 130 }
 131 #endif
 132 #endif
 133
 134 #if (CONFIG_SYS_NUM_FM1_10GEC >= 3)
 135 #define FM_TGEC_INFO_INITIALIZER2(idx, n) \
 136 {                                                                       \
 137         FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR)     \
 138         .index          = idx,                                          \
 139         .num            = n - 1,                                        \
 140         .type           = FM_ETH_10G_E,                                 \
 141         .port           = FM##idx##_10GEC##n,                           \
 142         .rx_port_id     = RX_PORT_10G_BASE2 + n - 3,                    \
 143         .tx_port_id     = TX_PORT_10G_BASE2 + n - 3,                    \
 144         .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET +             \
 145                                 offsetof(struct ccsr_fman, memac[n-1-2]),\
 146 }
 147 #endif
 148
 149 #else
 150 #define FM_DTSEC_INFO_INITIALIZER(idx, n) \
 151 {                                                                       \
 152         FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR)   \
 153         .index          = idx,                                          \
 154         .num            = n - 1,                                        \
 155         .type           = FM_ETH_1G_E,                                  \
 156         .port           = FM##idx##_DTSEC##n,                           \
 157         .rx_port_id     = RX_PORT_1G_BASE + n - 1,                      \
 158         .tx_port_id     = TX_PORT_1G_BASE + n - 1,                      \
 159         .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET +             \
 160                                 offsetof(struct ccsr_fman, mac_1g[n-1]),\
 161 }
 162
 163 #define FM_TGEC_INFO_INITIALIZER(idx, n) \
 164 {                                                                       \
 165         FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR)     \
 166         .index          = idx,                                          \
 167         .num            = n - 1,                                        \
 168         .type           = FM_ETH_10G_E,                                 \
 169         .port           = FM##idx##_10GEC##n,                           \
 170         .rx_port_id     = RX_PORT_10G_BASE + n - 1,                     \
 171         .tx_port_id     = TX_PORT_10G_BASE + n - 1,                     \
 172         .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET +             \
 173                                 offsetof(struct ccsr_fman, mac_10g[n-1]),\
 174 }
 175 #endif
 176 struct fm_eth_info {
 177         u8 enabled;
 178         u8 fm;
 179         u8 num;
 180         u8 phy_addr;
 181         int index;
 182         u16 rx_port_id;
 183         u16 tx_port_id;
 184         enum fm_port port;
 185         enum fm_eth_type type;
 186         void *phy_regs;
 187         phy_interface_t enet_if;
 188         u32 compat_offset;
 189         struct mii_dev *bus;
 190 };
 191
 192 struct tgec_mdio_info {
 193         struct tgec_mdio_controller *regs;
 194         char *name;
 195 };
 196
 197 struct memac_mdio_info {
 198         struct memac_mdio_controller *regs;
 199         char *name;
 200 };
 201
 202 int fm_tgec_mdio_init(struct bd_info *bis, struct tgec_mdio_info *info);
 203 int fm_memac_mdio_init(struct bd_info *bis, struct memac_mdio_info *info);
 204
 205 int fm_standard_init(struct bd_info *bis);
 206 void fman_enet_init(void);
 207 void fdt_fixup_fman_ethernet(void *fdt);
 208 phy_interface_t fm_info_get_enet_if(enum fm_port port);
 209 void fm_info_set_phy_address(enum fm_port port, int address);
 210 int fm_info_get_phy_address(enum fm_port port);
 211 void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus);
 212 void fm_disable_port(enum fm_port port);
 213 void fm_enable_port(enum fm_port port);
 214 void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port,
 215                 unsigned int port_num, int phy_base_addr);
 216 int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr,
 217                 unsigned int port_num, unsigned regnum);
 218
 219 #endif