Merge branch 'master' of git://git.denx.de/u-boot-sh
[platform/kernel/u-boot.git] / include / fm_eth.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2009-2012 Freescale Semiconductor, Inc.
4  */
5
6 #ifndef __FM_ETH_H__
7 #define __FM_ETH_H__
8
9 #include <common.h>
10 #include <phy.h>
11 #include <asm/types.h>
12
13 enum fm_port {
14         FM1_DTSEC1,
15         FM1_DTSEC2,
16         FM1_DTSEC3,
17         FM1_DTSEC4,
18         FM1_DTSEC5,
19         FM1_DTSEC6,
20         FM1_DTSEC9,
21         FM1_DTSEC10,
22         FM1_10GEC1,
23         FM1_10GEC2,
24         FM1_10GEC3,
25         FM1_10GEC4,
26         FM2_DTSEC1,
27         FM2_DTSEC2,
28         FM2_DTSEC3,
29         FM2_DTSEC4,
30         FM2_DTSEC5,
31         FM2_DTSEC6,
32         FM2_DTSEC9,
33         FM2_DTSEC10,
34         FM2_10GEC1,
35         FM2_10GEC2,
36         NUM_FM_PORTS,
37 };
38
39 enum fm_eth_type {
40         FM_ETH_1G_E,
41         FM_ETH_10G_E,
42 };
43
44 #ifdef CONFIG_SYS_FMAN_V3
45 #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR  (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000)
46 #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR   (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
47 #if (CONFIG_SYS_NUM_FMAN == 2)
48 #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR  (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000)
49 #define CONFIG_SYS_FM2_TGEC_MDIO_ADDR   (CONFIG_SYS_FSL_FM2_ADDR + 0xfd000)
50 #endif
51 #else
52 #define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xe1120)
53 #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR   (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000)
54 #endif
55
56 #define DEFAULT_FM_MDIO_NAME "FSL_MDIO0"
57 #define DEFAULT_FM_TGEC_MDIO_NAME "FM_TGEC_MDIO"
58
59 /* Fman ethernet info struct */
60 #define FM_ETH_INFO_INITIALIZER(idx, pregs) \
61         .fm             = idx,                                          \
62         .phy_regs       = (void *)pregs,                                \
63         .enet_if        = PHY_INTERFACE_MODE_NONE,                      \
64
65 #ifdef CONFIG_SYS_FMAN_V3
66 #define FM_DTSEC_INFO_INITIALIZER(idx, n) \
67 {                                                                       \
68         FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC_MDIO_ADDR)    \
69         .index          = idx,                                          \
70         .num            = n - 1,                                        \
71         .type           = FM_ETH_1G_E,                                  \
72         .port           = FM##idx##_DTSEC##n,                           \
73         .rx_port_id     = RX_PORT_1G_BASE + n - 1,                      \
74         .tx_port_id     = TX_PORT_1G_BASE + n - 1,                      \
75         .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET +             \
76                                 offsetof(struct ccsr_fman, memac[n-1]),\
77 }
78
79 #ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
80 #define FM_TGEC_INFO_INITIALIZER(idx, n) \
81 {                                                                       \
82         FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR)     \
83         .index          = idx,                                          \
84         .num            = n - 1,                                        \
85         .type           = FM_ETH_10G_E,                                 \
86         .port           = FM##idx##_10GEC##n,                           \
87         .rx_port_id     = RX_PORT_10G_BASE2 + n - 1,                    \
88         .tx_port_id     = TX_PORT_10G_BASE2 + n - 1,                    \
89         .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET +             \
90                                  offsetof(struct ccsr_fman, memac[n-1]),\
91 }
92 #else
93 #if (CONFIG_SYS_NUM_FMAN == 2)
94 #define FM_TGEC_INFO_INITIALIZER(idx, n) \
95 {                                                                       \
96         FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR)     \
97         .index          = idx,                                          \
98         .num            = n - 1,                                        \
99         .type           = FM_ETH_10G_E,                                 \
100         .port           = FM##idx##_10GEC##n,                           \
101         .rx_port_id     = RX_PORT_10G_BASE + n - 1,                     \
102         .tx_port_id     = TX_PORT_10G_BASE + n - 1,                     \
103         .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET +             \
104                                 offsetof(struct ccsr_fman, memac[n-1+8]),\
105 }
106 #else
107 #define FM_TGEC_INFO_INITIALIZER(idx, n) \
108 {                                                                       \
109         FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR)     \
110         .index          = idx,                                          \
111         .num            = n - 1,                                        \
112         .type           = FM_ETH_10G_E,                                 \
113         .port           = FM##idx##_10GEC##n,                           \
114         .rx_port_id     = RX_PORT_10G_BASE + n - 1,                     \
115         .tx_port_id     = TX_PORT_10G_BASE + n - 1,                     \
116         .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET +             \
117                                 offsetof(struct ccsr_fman, memac[n-1+8]),\
118 }
119 #endif
120 #endif
121
122 #if (CONFIG_SYS_NUM_FM1_10GEC >= 3)
123 #define FM_TGEC_INFO_INITIALIZER2(idx, n) \
124 {                                                                       \
125         FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR)     \
126         .index          = idx,                                          \
127         .num            = n - 1,                                        \
128         .type           = FM_ETH_10G_E,                                 \
129         .port           = FM##idx##_10GEC##n,                           \
130         .rx_port_id     = RX_PORT_10G_BASE2 + n - 3,                    \
131         .tx_port_id     = TX_PORT_10G_BASE2 + n - 3,                    \
132         .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET +             \
133                                 offsetof(struct ccsr_fman, memac[n-1-2]),\
134 }
135 #endif
136
137 #else
138 #define FM_DTSEC_INFO_INITIALIZER(idx, n) \
139 {                                                                       \
140         FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR)   \
141         .index          = idx,                                          \
142         .num            = n - 1,                                        \
143         .type           = FM_ETH_1G_E,                                  \
144         .port           = FM##idx##_DTSEC##n,                           \
145         .rx_port_id     = RX_PORT_1G_BASE + n - 1,                      \
146         .tx_port_id     = TX_PORT_1G_BASE + n - 1,                      \
147         .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET +             \
148                                 offsetof(struct ccsr_fman, mac_1g[n-1]),\
149 }
150
151 #define FM_TGEC_INFO_INITIALIZER(idx, n) \
152 {                                                                       \
153         FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR)     \
154         .index          = idx,                                          \
155         .num            = n - 1,                                        \
156         .type           = FM_ETH_10G_E,                                 \
157         .port           = FM##idx##_10GEC##n,                           \
158         .rx_port_id     = RX_PORT_10G_BASE + n - 1,                     \
159         .tx_port_id     = TX_PORT_10G_BASE + n - 1,                     \
160         .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET +             \
161                                 offsetof(struct ccsr_fman, mac_10g[n-1]),\
162 }
163 #endif
164 struct fm_eth_info {
165         u8 enabled;
166         u8 fm;
167         u8 num;
168         u8 phy_addr;
169         int index;
170         u16 rx_port_id;
171         u16 tx_port_id;
172         enum fm_port port;
173         enum fm_eth_type type;
174         void *phy_regs;
175         phy_interface_t enet_if;
176         u32 compat_offset;
177         struct mii_dev *bus;
178 };
179
180 struct tgec_mdio_info {
181         struct tgec_mdio_controller *regs;
182         char *name;
183 };
184
185 struct memac_mdio_info {
186         struct memac_mdio_controller *regs;
187         char *name;
188 };
189
190 int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info);
191 int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info);
192
193 int fm_standard_init(bd_t *bis);
194 void fman_enet_init(void);
195 void fdt_fixup_fman_ethernet(void *fdt);
196 phy_interface_t fm_info_get_enet_if(enum fm_port port);
197 void fm_info_set_phy_address(enum fm_port port, int address);
198 int fm_info_get_phy_address(enum fm_port port);
199 void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus);
200 void fm_disable_port(enum fm_port port);
201 void fm_enable_port(enum fm_port port);
202 void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port,
203                 unsigned int port_num, int phy_base_addr);
204 int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr,
205                 unsigned int port_num, unsigned regnum);
206
207 #endif