2 *-----------------------------------------------------------------------------
5 *-----------------------------------------------------------------------------
6 * Copyright (c) 2002-2010, Intel Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
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12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
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18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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26 *-----------------------------------------------------------------------------
29 *-----------------------------------------------------------------------------
34 #include <linux/version.h>
37 #include <igd_appcontext.h>
38 #include <igd_errno.h>
45 #include <igd_version.h>
53 /* To differentiate different engines for command buffer submission */
54 #define PSB_ENGINE_2D 0
55 #define PSB_ENGINE_VIDEO 1
56 #define PSB_ENGINE_RASTERIZER 2
57 #define PSB_ENGINE_TA 3
58 #define PSB_ENGINE_HPRAST 4
59 #define TNC_ENGINE_ENCODE 5
60 #define PSB_ENGINE_COMPOSITOR_MMU 6
63 /* OEM flags for buffer allocation through the PVR2DCreateFlipChain */
64 #ifndef PVR2D_CREATE_FLIPCHAIN_SHARED
65 #define PVR2D_CREATE_FLIPCHAIN_SHARED (1UL << 0)
66 #define PVR2D_CREATE_FLIPCHAIN_QUERY (1UL << 1)
67 #define PVR2D_CREATE_FLIPCHAIN_OEMOVERLAY (1UL << 2)
68 #define PVR2D_CREATE_FLIPCHAIN_AS_BLITCHAIN (1UL << 3)
71 #define PVR2D_CREATE_FLIPCHAIN_OEMDISPLAY (1UL << 4)
72 #define PVR2D_CREATE_FLIPCHAIN_OEMGENERAL (1UL << 5)
73 #define PVR2D_CREATE_FLIPCHAIN_OEMFLIPCHAIN (1UL << 6)
74 #define PVR2D_CREATE_FLIPCHAIN_CI (1UL << 7)
75 #define PVR2D_CREATE_FLIPCHAIN_CI_V4L2_MAP (1UL << 8)
76 /* Different command */
77 #define CMD_VIDEO_STATE 1
78 #define CMD_VIDEO_INITIALIZE 2
79 #define CMD_VIDEO_UNINITIALIZE 3
80 #define CMD_VIDEO_CLOSE_CONTEXT 4
81 #define CMD_VIDEO_CREATE_CONTEXT 5
82 #define CMD_VIDEO_SHUTDOWN 6
83 #define CMD_VIDEO_GET_FENCE_ID 7
84 #define CMD_VIDOE_GET_FRAME_SKIP 8
85 #define CMD_VIDEO_GET_MSVDX_STATUS 9
88 #define VIDEO_STATE_FW_LOADED 0x00000001
89 #define VIDEO_STATE_RENDEC_FREED 0x00000002
91 /* Different command for alter_ovl2 */
92 #define CMD_ALTER_OVL2 1
93 #define CMD_ALTER_OVL2_OSD 2
95 typedef enum _kdrm_test_pvrsrv_opcodes {
96 SINGLE_DC_SWAPING = 0,
97 DIH_DC_DRAW_OPEN_DEV1 = 1,
98 DIH_DC_MODE_CHANGE1_DEV1 = 2,
99 DIH_DC_MODE_CHANGE2_DEV1 = 3,
100 DIH_DC_CLOSE_DEV1 = 4,
101 DIH_DC_DRAW_OPEN_DEV2 = 5,
102 DIH_DC_MODE_CHANGE1_DEV2 = 6,
103 DIH_DC_MODE_CHANGE2_DEV2 = 7,
104 DIH_DC_CLOSE_DEV2 = 8,
105 } emgd_drm_test_pvrsrv_opcodes_t;
109 * This is where all the data structures used by the Koheo DRM interface are
110 * defined. These data structures are shared between and are used to pass data
111 * between the user-space & kernel-space code for each ioctl.
113 * The naming convention is: emgd_drm_<HAL-procedure-pointer-name>_t
116 typedef struct _kdrm_alter_cursor {
117 int rtn; /* (UP) - return value of HAL procedure */
118 igd_display_h display_handle; /* (DOWN) - an "opaque handle" */
119 igd_cursor_info_t cursor_info; /* (DOWN) */
121 * A pointer to the cursor data (in user space), which must be copied
122 * separately from this struct.
124 unsigned char *image; /* (DOWN) */
125 } emgd_drm_alter_cursor_t;
128 typedef struct _kdrm_alter_cursor_pos {
129 int rtn; /* (UP) - return value of HAL procedure */
130 igd_display_h display_handle; /* (DOWN) - an "opaque handle" */
131 igd_cursor_info_t cursor_info; /* (DOWN) */
132 } emgd_drm_alter_cursor_pos_t;
135 typedef struct _kdrm_alter_displays {
136 int rtn; /* (UP) - return value of HAL procedure */
137 igd_display_info_t primary_pt_info; /* (DOWN) */
138 igd_display_info_t secondary_pt_info; /* (DOWN) */
139 igd_framebuffer_info_t primary_fb_info; /* (DOWN) */
140 igd_framebuffer_info_t secondary_fb_info; /* (DOWN) */
141 unsigned long dc; /* (DOWN) */
142 unsigned long flags; /* (DOWN) */
144 igd_display_h primary; /* (UP) Generated "opaque handle" */
145 igd_display_h secondary; /* (UP) Generated "opaque handle" */
146 } emgd_drm_alter_displays_t;
149 typedef struct _kdrm_alter_ovl {
150 int rtn; /* (UP) - return value of HAL procedure */
151 igd_display_h display_handle; /* (DOWN) - an "opaque handle" */
152 igd_appcontext_h appcontext_h; /* (DOWN) a handle */
153 /* NOTE: igd_surface_t contains a pointer to an igd_palette_info_t struct
154 * (member name "palette_info"), which contains a pointer to an "unsigned
155 * long" "palette". Normally, each of these values must be copied from
156 * user to kernel space. However, an investigation found that the
157 * igd_palette_info_t struct is not used for either alter_ovl() or
158 * set_surface() (and igd_get_surface_plb() sets the value to 0,
159 * a.k.a. NULL). Thus, we're okay not copying this value.
161 igd_surface_t src_surf; /* (DOWN) */
162 igd_rect_t src_rect; /* (DOWN) */
163 igd_rect_t dst_rect; /* (DOWN) */
164 igd_ovl_info_t ovl_info; /* (DOWN) */
165 unsigned long flags; /* (DOWN) */
166 } emgd_drm_alter_ovl_t;
168 typedef struct _kdrm_alter_ovl2 {
169 int rtn; /* (UP) - return value of HAL procedure */
170 igd_display_h display_handle; /* (DOWN) - an "opaque handle" */
171 igd_surface_t src_surf; /* (DOWN) */
172 igd_rect_t src_rect; /* (DOWN) */
173 igd_rect_t dst_rect; /* (DOWN) */
174 igd_ovl_info_t ovl_info; /* (DOWN) */
175 unsigned long flags; /* (DOWN) */
176 int cmd; /* (DOWN) */
177 } emgd_drm_alter_ovl2_t;
180 typedef struct _kdrm_get_ovl_init_params {
181 ovl_um_context_t *ovl_um_context;
182 int rtn; /* (UP) - return value of HAL procedure */
183 } emgd_drm_get_ovl_init_params_t;
186 typedef struct _kdrm_appcontext_alloc {
187 igd_display_h display_handle; /* (DOWN) - an "opaque handle" */
188 int priority; /* (DOWN) */
189 unsigned int flags; /* (DOWN) */
190 igd_appcontext_h appcontext_h; /* (UP) a handle */
191 } emgd_drm_appcontext_alloc_t;
194 typedef struct _kdrm_appcontext_free {
195 igd_display_h display_handle; /* (DOWN) - an "opaque handle" */
196 int priority; /* (DOWN) */
197 igd_appcontext_h appcontext_h; /* (DOWN) a handle */
198 } emgd_drm_appcontext_free_t;
201 typedef struct _kdrm_driver_save_restore {
202 int rtn; /* (UP) - return value of HAL procedure */
203 } emgd_drm_driver_save_restore_t;
206 typedef struct _kdrm_enable_port {
207 igd_display_h display_handle; /* (DOWN) - an "opaque handle" */
208 int rtn; /* (UP) - return value of HAL procedure */
209 unsigned short port_number; /* (DOWN) */
210 unsigned long flag; /* (DOWN) */
211 unsigned long test; /* (DOWN) */
212 } emgd_drm_enable_port_t;
215 typedef struct _kdrm_get_attrs {
216 int rtn; /* (UP) - return value of HAL procedure */
217 unsigned short port_number; /* (DOWN) */
218 /** The number of attributes of memory allocated by user-space. */
219 unsigned int allocated_size; /* (DOWN) */
220 /** The number of attributes returned by the kernel. */
221 unsigned long list_size; /* (UP) */
223 * A pointer to the user-space-allocated memory for the kernel to copy the
224 * returned attribute list into. allocated_size is how many attributes
225 * this memory can contain. list_size is how many attributes the kernel is
226 * returning (or wants to return). If list_size > allocated_size, no data
227 * is copied back to user-space, and the user-space must re-allocate
228 * list_size amount of memory and try the ioctl again.
230 igd_attr_t *attr_list; /* (UP) */
231 int extended; /* (DOWN/UP) - true if there are/to get extended attributes */
232 } emgd_drm_get_attrs_t;
234 #define IGD_GET_DISPLAY_NO_3DD_REINIT 0x1
236 typedef struct _kdrm_get_display {
237 int rtn; /* (UP) - return value of HAL procedure */
238 igd_display_h display_handle; /* (DOWN) - an "opaque handle" */
239 unsigned short port_number; /* (DOWN) */
240 igd_framebuffer_info_t fb_info; /* (DOWN/UP) Caller alloc's; DRM returns */
241 igd_display_info_t pt_info; /* (DOWN/UP) Caller alloc's; DRM returns */
242 unsigned long flags; /* (DOWN) */
243 } emgd_drm_get_display_t;
246 typedef struct _kdrm_get_drm_config {
247 int rtn; /* (UP) - return value of HAL procedure */
248 /** Which configuration to use within "xorg.conf" */
249 long config_id; /* (UP) */
250 /** The set of compile-time parameters, specified in "user_config.c". */
251 igd_param_t params; /* (UP) */
252 /** The display config (e.g. 8 for DIH). */
253 int display_config; /* (UP) */
255 * Build configuration (e.g., DDK version used, debug vs release, etc.);
256 * if these don't match what userspace was built with, the driver may not
259 igd_build_config_t build_config;
260 } emgd_drm_get_drm_config_t;
263 typedef struct _kdrm_get_EDID_block {
264 int rtn; /* (UP) - return value of HAL procedure */
265 unsigned short port_number; /* (DOWN) */
266 unsigned char block_number; /* (DOWN) */
267 unsigned char edid_block[128]; /* (UP) */
268 } emgd_drm_get_EDID_block_t;
271 typedef struct _kdrm_get_EDID_info {
272 int rtn; /* (UP) - return value of HAL procedure */
273 unsigned short port_number; /* (DOWN) */
274 unsigned char edid_version; /* (UP) */
275 unsigned char edid_revision; /* (UP) */
276 unsigned long edid_size; /* (UP) */
277 } emgd_drm_get_EDID_info_t;
281 * This enum is used to state which of the 5 pixel format lists is desired to
282 * be returned in the emgd_drm_get_pixelformats_t struct (which only transfers
285 typedef enum _kdrm_which_pixelformat {
286 PIXEL_FORMAT_FRAMEBUFFER,
288 PIXEL_FORMAT_OVERLAY,
291 } emgd_drm_which_pixelformat_t;
294 * The igd_dispatch_t.get_pixelformats() procedure returns up-to 5 different
295 * lists of pixel formats. However, for Koheo drivers, only one of these lists
296 * is ever requested/returned. Thus, only one list needs to be passed between
297 * user/kernel space. Memory for the list is allocated in user space, and a
298 * pointer to it, along with its size and which format is desired, is passed to
299 * the kernel in this struct.
301 typedef struct _kdrm_get_pixelformats {
302 int rtn; /* (UP) - return value of HAL procedure */
303 igd_display_h display_handle; /* (DOWN) - an "opaque handle" */
304 emgd_drm_which_pixelformat_t format; /* (DOWN) */
305 /** The number of pixelformats of memory allocated by user-space. */
306 unsigned int allocated_size; /* (DOWN) */
307 /** The number of pixelformats returned by the kernel. */
308 unsigned int list_size; /* (UP) */
309 unsigned long *format_list; /* (DOWN/UP) */
310 } emgd_drm_get_pixelformats_t;
313 typedef struct _kdrm_get_port_info {
314 int rtn; /* (UP) - return value of HAL procedure */
315 unsigned short port_number; /* (DOWN) */
316 igd_port_info_t port_info; /* (UP) */
317 } emgd_drm_get_port_info_t;
320 typedef struct _kdrm_gmm_alloc_region {
321 int rtn; /* (UP) - return value of HAL procedure */
322 unsigned long offset; /* (UP) */
323 unsigned long size; /* (DOWN/UP) */
324 unsigned int type; /* (DOWN) */
325 unsigned long flags; /* (DOWN) */
326 } emgd_drm_gmm_alloc_region_t;
329 typedef struct _kdrm_gmm_alloc_surface {
330 int rtn; /* (UP) - return value of HAL procedure */
331 unsigned long offset; /* (UP) */
332 unsigned long pixel_format; /* (DOWN) */
333 unsigned int width; /* (DOWN/UP) */
334 unsigned int height; /* (DOWN/UP) */
335 unsigned int pitch; /* (UP) */
336 unsigned long size; /* (DOWN/UP) */
337 unsigned int type; /* (DOWN) */
338 unsigned long flags; /* (DOWN) */
339 } emgd_drm_gmm_alloc_surface_t;
342 typedef struct _kdrm_gmm_get_num_surface {
343 int rtn; /* (UP) - return value of HAL procedure */
344 unsigned long count; /* (UP) */
345 } emgd_drm_gmm_get_num_surface_t;
348 typedef struct _kdrm_gmm_get_surface_list {
349 int rtn; /* (UP) - return value of HAL procedure */
350 unsigned long allocated_size; /* (DOWN) */
351 unsigned long list_size; /* (UP) */
352 igd_surface_list_t **surface_list; /* (UP) */
353 } emgd_drm_gmm_get_surface_list_t;
356 typedef struct _kdrm_gmm_free {
357 unsigned long offset; /* (DOWN) */
358 } emgd_drm_gmm_free_t;
361 typedef struct _kdrm_gmm_flush_cache {
362 int rtn; /* (UP) - return value of HAL procedure */
363 } emgd_drm_gmm_flush_cache_t;
365 typedef struct _kdrm_video_cmd_buf {
368 unsigned long offset;
369 void *kernel_virt_addr;
370 unsigned long fence_id;
371 } emgd_drm_video_cmd_buf_t;
373 typedef struct _kdrm_device_info {
374 unsigned long device_id;
375 unsigned long revision_id;
376 unsigned short bridge_id;
377 unsigned long display_memory_size;
378 unsigned long display_memory_offset;
379 } emgd_drm_device_info_t;
381 typedef struct _kdrm_init_video {
390 unsigned long fw_size;
393 unsigned long wb_offset;
397 unsigned long status;
398 unsigned long context_id;
400 } emgd_drm_init_video_t;
402 typedef struct _kdrm_video_get_info {
407 unsigned long fence_id;
408 unsigned long frame_skip;
409 unsigned long queue_status; /* (UP) - return 1 if msvdx queue empty, else 0 */
410 unsigned long mtx_msg_status; /* (UP) - return 1 if msvdx current message complete, else 0 */
411 } emgd_drm_video_get_info_t;
413 typedef struct _kdrm_video_flush_tlb {
416 } emgd_drm_video_flush_tlb_t;
418 typedef struct _kdrm_preinit_mmu {
420 unsigned long memcontext;
421 } emgd_drm_preinit_mmu_t;
423 typedef struct _kdrm_get_display_info {
424 int rtn; /* (UP) - return value of HAL procedure */
425 igd_display_info_t primary_pt_info; /* (UP) */
426 igd_display_info_t secondary_pt_info; /* (UP) */
427 igd_framebuffer_info_t primary_fb_info; /* (UP) */
428 igd_framebuffer_info_t secondary_fb_info; /* (UP) */
429 unsigned long dc; /* (UP) */
430 unsigned long flags; /* (UP) */
432 igd_display_h primary; /* (UP) Generated "opaque handle" */
433 igd_display_h secondary; /* (UP) Generated "opaque handle" */
434 } emgd_drm_get_display_info_t;
436 typedef struct _kdrm_pan_display {
437 /* Note: the return value is a long this time: */
438 long rtn; /* (UP) - return value of HAL procedure */
439 igd_display_h display_handle; /* (DOWN) - an "opaque handle" */
440 unsigned long x_offset; /* (DOWN) */
441 unsigned long y_offset; /* (DOWN) */
442 } emgd_drm_pan_display_t;
445 typedef struct _kdrm_power_display {
446 int rtn; /* (UP) - return value of HAL procedure */
447 unsigned short port_number; /* (DOWN) */
448 unsigned long power_state; /* (DOWN) */
449 } emgd_drm_power_display_t;
452 typedef struct _kdrm_pwr_alter {
453 int rtn; /* (UP) - return value of HAL procedure */
454 unsigned int power_state; /* (DOWN) */
455 } emgd_drm_pwr_alter_t;
459 * Memory for the list is allocated in user space, and a pointer to it, along
460 * with its size, is passed to the kernel in this struct.
462 typedef struct _kdrm_query_dc {
463 int rtn; /* (UP) - return value of HAL procedure */
464 unsigned long request; /* (DOWN) */
465 unsigned long flags; /* (DOWN) */
466 /** The number of DCs of memory allocated by user-space. */
467 unsigned int allocated_size; /* (DOWN) */
468 /** The number of DCs returned by the kernel. */
469 unsigned int list_size; /* (UP) */
470 unsigned long *dc_list; /* (UP) */
471 } emgd_drm_query_dc_t;
474 typedef struct _kdrm_query_max_size_ovl {
475 int rtn; /* (UP) - return value of HAL procedure */
476 igd_display_h display_handle; /* (DOWN) - an "opaque handle" */
477 unsigned long pf; /* (DOWN) */
478 unsigned int max_width; /* (UP) */
479 unsigned int max_height; /* (UP) */
480 } emgd_drm_query_max_size_ovl_t;
483 typedef struct _kdrm_query_ovl {
484 int rtn; /* (UP) - return value of HAL procedure */
485 igd_display_h display_handle; /* (DOWN) - an "opaque handle" */
486 unsigned long flags; /* (DOWN) */
487 } emgd_drm_query_ovl_t;
490 typedef struct _kdrm_query_mode_list {
491 int rtn; /* (UP) - return value of HAL procedure */
492 unsigned long dc; /* (DOWN) */
493 unsigned long flags; /* (DOWN) */
494 /** The number of attributes of memory allocated by user-space. */
495 unsigned int allocated_size; /* (DOWN) */
496 /** The number of attributes returned by the kernel. */
497 unsigned int list_size; /* (UP) */
498 igd_display_info_t *mode_list; /* (DOWN/UP) */
499 } emgd_drm_query_mode_list_t;
502 typedef struct _kdrm_get_golden_htotal {
503 int rtn; /* (UP) - return value of HAL procedure */
504 igd_display_info_t *in_mode; /* (DOWN/UP) */
505 igd_display_info_t *out_mode; /* (DOWN/UP) */
506 } emgd_drm_get_golden_htotal_t;
508 typedef struct _kdrm_set_attrs {
509 int rtn; /* (UP) - return value of HAL procedure */
510 unsigned short port_number; /* (DOWN) */
511 /** The number of attributes sent to the kernel. */
512 unsigned int list_size; /* (DOWN) */
514 * Note: the attribute list is variable-sized data, but an ioctl must use a
515 * fixed-sized struct. Thus, this struct contains both a pointer to the
516 * attribute list (in user space, which must be copied separately from this
517 * struct) and the number of attibutes (above).
519 igd_attr_t *attr_list; /* (DOWN) */
520 } emgd_drm_set_attrs_t;
523 typedef struct _kdrm_set_palette_entry {
524 int rtn; /* (UP) - return value of HAL procedure */
525 igd_display_h display_handle; /* (DOWN) - an "opaque handle" */
526 unsigned long palette_entry; /* (DOWN) */
527 unsigned long palette_color; /* (DOWN) */
528 } emgd_drm_set_palette_entry_t;
531 typedef struct _kdrm_set_surface {
532 int rtn; /* (UP) - return value of HAL procedure */
533 igd_display_h display_handle; /* (DOWN) - an "opaque handle" */
534 int priority; /* (DOWN) */
535 igd_buffertype_t type; /* (DOWN) */
536 /* NOTE: igd_surface_t contains a pointer to an igd_palette_info_t struct:
537 * see the description above, in the typedef emgd_drm_alter_ovl_t.
539 igd_surface_t surface; /* (DOWN) */
540 igd_appcontext_h appcontext; /* (DOWN) a handle */
541 unsigned long flags; /* (DOWN) */
542 } emgd_drm_set_surface_t;
544 #define PRIMARY_DISPLAY 0
545 #define SECONDARY_DISPLAY 1
546 #define CLONE_PRIMARY PRIMARY_DISPLAY
547 #define CLONE_SECONDARY SECONDARY_DISPLAY
551 #define DUAL_SCREEN_MAX_DISPLAY 2
552 #define MAX_FFB_SURF_VEXT DUAL_SCREEN_MAX_DISPLAY
553 #define MAX_FFB_SURF_DIH 1
555 typedef struct _kdrm_dihclone_set_surface {
556 int rtn; /* (UP) - return value of HAL procedure */
557 unsigned long dih_clone_display; /* (DOWN) - primary or secondary display to clone */
558 unsigned long mode; /* (DOWN) - dih to clone or back to dih */
559 } emgd_drm_dihclone_set_surface_t;
561 typedef struct _kdrm_control_plane_format {
562 /* Note on modification to the structure to accomodate both
563 * Use PRIMARY/SECONDARY to indicate which display
564 * FB blend + overlay to turn ON/OFF. The relationship between
565 * plane, pipe and port is transparent to the user.
566 * A qualifier (use_plane) is used to decide which model the user wants.
568 int rtn; /* (UP) - return value of HAL procedure */
569 /* (DOWN) Turn off transparency by switching to XRGB format = 0
570 Turn on transparency by switching to ARGB format = 1 */
573 /* (DOWN) Plane A = 0
576 /* (DOWN) Primary/Secondary display handle */
577 igd_display_h primary_secondary_dsp;
579 /* If set, KMD will use the plane convention */
580 unsigned int use_plane;
581 } emgd_drm_control_plane_format_t;
584 typedef struct _kdrm_set_overlay_display{
585 int rtn; /* (UP) - return value of HAL procedure */
586 igd_display_h ovl_display[OVL_MAX_HW]; /* (DOWN) Overlay display handles */
587 } emgd_drm_set_overlay_display_t;
590 typedef struct _kdrm_sync {
591 int rtn; /* (UP) - return value of HAL procedure */
592 igd_display_h display_handle; /* (DOWN) - an "opaque handle" */
593 int priority; /* (DOWN) */
594 unsigned long in_sync; /* (DOWN/UP) */
595 unsigned long flags; /* (DOWN) */
599 typedef struct _kdrm_driver_pre_init {
600 int rtn; /* (UP) - return value of HAL procedure */
602 * The set of user-specified parameters, parsed at X server PreInit() time.
604 igd_param_t params; /* (DOWN) */
606 * The results of the HAL's igd_get_config_info() procedure. The
607 * user-space code allocates memory for this.
609 igd_config_info_t config_info; /* (UP) */
610 /* this is passed in by intelPreInit */
612 } emgd_drm_driver_pre_init_t;
615 typedef struct _kdrm_driver_get_ports {
616 int rtn; /* (UP) - return value of HAL procedure */
617 /** An array of ports discovered by the device-specific HAL driver. */
618 unsigned long ports[IGD_MAX_PORTS]; /* (UP) */
619 } emgd_drm_driver_get_ports_t;
622 typedef struct _kdrm_driver_get_chipset_info {
623 unsigned long device_id;
624 unsigned long revision_id;
626 char description[20];
627 } emgd_drm_driver_get_chipset_info_t;
630 typedef struct _kdrm_get_page_list {
631 int rtn; /* (UP) - return value of kernel-mode test code() */
632 igd_display_h display_handle; /* (DOWN) - an "opaque handle" */
633 unsigned long offset; /* (DOWN) - surface offset (ID) */
634 unsigned long addr_count; /* (DOWN) - size of address list */
635 unsigned long *addr_list; /* (UP) */
636 } emgd_drm_get_page_list_t;
638 typedef struct _kdrm_start_pvrsrv {
639 int xserver; /* (DOWN) - 1 if called by X server, else 0 */
640 int rtn; /* (UP) - return value of PVRSRVDrmLoad() */
641 } emgd_drm_start_pvrsrv_t;
643 typedef struct _kdrm_test_pvrsrv {
644 emgd_drm_test_pvrsrv_opcodes_t opcode; /* (DOWN) */
645 int rtn; /* (UP) - return value of kernel-mode test code() */
646 char rtn_msg[1024]; /* (UP) */
647 } emgd_drm_test_pvrsrv_t;
650 typedef struct _kdrm_query_2d_caps_hwhint {
651 unsigned long caps_val; /* (DOWN) */
652 unsigned long *status; /* (UP) */
653 } emgd_drm_query_2d_caps_hwhint_t;
655 /* For Buffer Class FCB #17711*/
656 typedef struct _kdrm_bc_ts {
662 unsigned long dev_id;
663 unsigned long buf_id;
664 unsigned long buf_tag;
665 unsigned long num_buf;
666 unsigned long pixel_format;
667 unsigned long phyaddr;
668 unsigned long virtaddr;
672 * This is where all the IOCTL's used by the egd DRM interface are
673 * defined. This information is shared between the user space code and
677 #define BASE DRM_COMMAND_BASE
680 * EMGD-specific ioctls. These get mapped to the device specific range
681 * between 0x40 and 0x79.
683 * Client driver must use these values!
685 #define DRM_IGD_ALTER_CURSOR 0x00
686 #define DRM_IGD_ALTER_CURSOR_POS 0x01
687 #define DRM_IGD_ALTER_DISPLAYS 0x02
688 #define DRM_IGD_ALTER_OVL 0x03
689 #define DRM_IGD_APPCTX_ALLOC 0x04
690 #define DRM_IGD_APPCTX_FREE 0x05
691 #define DRM_IGD_DRIVER_SAVE_RESTORE 0x06
692 #define DRM_IGD_ENABLE_PORT 0x07
693 #define DRM_IGD_GET_ATTRS 0x08
694 #define DRM_IGD_GET_DISPLAY 0x09
695 #define DRM_IGD_GET_EDID_BLOCK 0x0a
696 #define DRM_IGD_GET_EDID_INFO 0x0b
697 #define DRM_IGD_GET_PIXELFORMATS 0x0c
698 #define DRM_IGD_GET_PORT_INFO 0x0d
699 #define DRM_IGD_GMM_ALLOC_REGION 0x0e
700 #define DRM_IGD_GMM_ALLOC_SURFACE 0x0f
701 #define DRM_IGD_GMM_FREE 0x10
702 #define DRM_IGD_GMM_FLUSH_CACHE 0x11
703 #define DRM_IGD_GMM_GET_NUM_SURFACE 0x31
704 #define DRM_IGD_GMM_GET_SURFACE_LIST 0x32
705 #define DRM_IGD_GET_GOLDEN_HTOTAL 0x33
706 #define DRM_IGD_CONTROL_PLANE_FORMAT 0x34
707 #define DRM_IGD_QUERY_2D_CAPS_HWHINT 0x35
708 #define DRM_IGD_DIHCLONE_SET_SURFACE 0x36
709 #define DRM_IGD_SET_OVERLAY_DISPLAY 0x37
710 #define DRM_IGD_WAIT_VBLANK 0x40
713 * The EMGD DRM includes the PVR DRM, and as such, includes the following PVR
714 * DRM ioctls. The numbering must be kept in sync with what is defined in
717 #define DRM_IGD_RESERVED_1 DRM_PVR_RESERVED1 /* Reserved */
718 #define DRM_IGD_RESERVED_2 DRM_PVR_RESERVED2 /* Reserved */
719 #define DRM_IGD_RESERVED_3 DRM_PVR_RESERVED3 /* Reserved */
720 #define DRM_IGD_RESERVED_4 DRM_PVR_RESERVED4 /* Reserved */
721 #define DRM_IGD_RESERVED_5 DRM_PVR_RESERVED5 /* Reserved */
722 #define DRM_IGD_PAN_DISPLAY 0x17
723 #define DRM_IGD_POWER_DISPLAY 0x18
724 #define DRM_IGD_PWR_ALTER 0x19
725 #define DRM_IGD_QUERY_DC 0x1a
726 #define DRM_IGD_QUERY_MAX_SIZE_OVL 0x1b
727 #define DRM_IGD_QUERY_OVL 0x1c
728 #define DRM_IGD_QUERY_MODE_LIST 0x1d
730 * Another PVR DRM ioctl that must be kept in sync with what is defined in
733 #define DRM_IGD_RESERVED_6 DRM_PVR_RESERVED6 /* Reserved */
734 #define DRM_IGD_SET_ATTRS 0x1f
735 #define DRM_IGD_SET_PALETTE_ENTRY 0x20
736 #define DRM_IGD_SET_SURFACE 0x21
737 #define DRM_IGD_SYNC 0x22
738 #define DRM_IGD_DRIVER_PRE_INIT 0x23
739 #define DRM_IGD_DRIVER_GET_PORTS 0x24
740 #define DRM_IGD_START_PVRSRV 0x25
741 #define DRM_IGD_TEST_PVRSRV 0x26
742 /* For Video (MSVDX/TOPAZ) */
743 #define DRM_IGD_VIDEO_CMD_BUF 0x27
744 #define DRM_IGD_GET_DEVICE_INFO 0x28
745 #define DRM_IGD_INIT_VIDEO 0x29
746 #define DRM_IGD_VIDEO_GET_INFO 0x2a
747 #define DRM_IGD_VIDEO_FLUSH_TLB 0x2b
749 #define DRM_IGD_GET_DRM_CONFIG 0x2c
750 #define DRM_IGD_GET_PAGE_LIST 0x2d
751 #define DRM_IGD_GET_OVL_INIT_PARAMS 0x2e
752 #define DRM_IGD_ALTER_OVL2 0x2f
753 #define DRM_IGD_GET_CHIPSET_INFO 0x30
754 #define DRM_IGD_GET_DISPLAY_INFO 0x38
755 #define DRM_IGD_PREINIT_MMU 0x39
756 /* For Buffer Class of Texture Stream */
757 #define DRM_IGD_BC_TS_INIT 0x40
758 #define DRM_IGD_BC_TS_UNINIT 0x41
759 #define DRM_IGD_BC_TS_REQUEST_BUFFERS 0x42
760 #define DRM_IGD_BC_TS_RELEASE_BUFFERS 0x43
761 #define DRM_IGD_BC_TS_SET_BUFFER_INFO 0x44
762 #define DRM_IGD_BC_TS_GET_BUFFERS_COUNT 0x45
763 #define DRM_IGD_BC_TS_GET_BUFFER_INDEX 0x46
764 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,3,0)
765 #define DRMFB_PITCH pitches[0]
766 #define DRMMODE_HANDLE handles[0]
767 #define DRM_MODE_FB_CMD_TYPE drm_mode_fb_cmd2
769 #define DRMFB_PITCH pitch
770 #define DRMMODE_HANDLE handle
771 #define DRM_MODE_FB_CMD_TYPE drm_mode_fb_cmd
777 #define DRM_IOCTL_IGD_ALTER_CURSOR DRM_IOWR(DRM_IGD_ALTER_CURSOR + BASE,\
778 emgd_drm_alter_cursor_t)
779 #define DRM_IOCTL_IGD_ALTER_CURSOR_POS DRM_IOWR(DRM_IGD_ALTER_CURSOR_POS +\
781 emgd_drm_alter_cursor_pos_t)
782 #define DRM_IOCTL_IGD_ALTER_DISPLAYS DRM_IOWR(DRM_IGD_ALTER_DISPLAYS + BASE,\
783 emgd_drm_alter_displays_t)
784 #define DRM_IOCTL_IGD_ALTER_OVL DRM_IOWR(DRM_IGD_ALTER_OVL + BASE,\
785 emgd_drm_alter_ovl_t)
786 #define DRM_IOCTL_IGD_ALTER_OVL2 DRM_IOWR(DRM_IGD_ALTER_OVL2 + BASE,\
787 emgd_drm_alter_ovl2_t)
788 #define DRM_IOCTL_IGD_APPCTX_ALLOC DRM_IOWR(DRM_IGD_APPCTX_ALLOC + BASE,\
789 emgd_drm_appcontext_alloc_t)
790 #define DRM_IOCTL_IGD_APPCTX_FREE DRM_IOWR(DRM_IGD_APPCTX_FREE + BASE,\
791 emgd_drm_appcontext_free_t)
792 #define DRM_IOCTL_IGD_DRIVER_SAVE_RESTORE DRM_IOWR(DRM_IGD_DRIVER_SAVE_RESTORE\
794 emgd_drm_driver_save_restore_t)
795 #define DRM_IOCTL_IGD_ENABLE_PORT DRM_IOWR(DRM_IGD_ENABLE_PORT + BASE,\
796 emgd_drm_enable_port_t)
797 #define DRM_IOCTL_IGD_GET_ATTRS DRM_IOWR(DRM_IGD_GET_ATTRS + BASE,\
798 emgd_drm_get_attrs_t)
799 #define DRM_IOCTL_IGD_GET_DISPLAY DRM_IOWR(DRM_IGD_GET_DISPLAY + BASE,\
800 emgd_drm_get_display_t)
801 #define DRM_IOCTL_IGD_GET_DRM_CONFIG DRM_IOWR(DRM_IGD_GET_DRM_CONFIG + BASE,\
802 emgd_drm_get_drm_config_t)
803 #define DRM_IOCTL_IGD_GET_EDID_BLOCK DRM_IOWR(DRM_IGD_GET_EDID_BLOCK + BASE,\
804 emgd_drm_get_EDID_block_t)
805 #define DRM_IOCTL_IGD_GET_EDID_INFO DRM_IOWR(DRM_IGD_GET_EDID_INFO + BASE,\
806 emgd_drm_get_EDID_info_t)
807 #define DRM_IOCTL_IGD_GET_PIXELFORMATS DRM_IOWR(DRM_IGD_GET_PIXELFORMATS +\
809 emgd_drm_get_pixelformats_t)
810 #define DRM_IOCTL_IGD_GET_PORT_INFO DRM_IOWR(DRM_IGD_GET_PORT_INFO + BASE,\
811 emgd_drm_get_port_info_t)
812 #define DRM_IOCTL_IGD_GMM_ALLOC_REGION DRM_IOWR(DRM_IGD_GMM_ALLOC_REGION +\
814 emgd_drm_gmm_alloc_region_t)
815 #define DRM_IOCTL_IGD_GMM_ALLOC_SURFACE DRM_IOWR(DRM_IGD_GMM_ALLOC_SURFACE +\
817 emgd_drm_gmm_alloc_surface_t)
818 #define DRM_IOCTL_IGD_GMM_GET_NUM_SURFACE DRM_IOW(\
819 DRM_IGD_GMM_GET_NUM_SURFACE +\
821 emgd_drm_gmm_get_num_surface_t)
822 #define DRM_IOCTL_IGD_GMM_GET_SURFACE_LIST DRM_IOW(\
823 DRM_IGD_GMM_GET_SURFACE_LIST +\
825 emgd_drm_gmm_get_surface_list_t)
826 #define DRM_IOCTL_IGD_GMM_FREE DRM_IOW(DRM_IGD_GMM_FREE + BASE,\
828 #define DRM_IOCTL_IGD_GMM_FLUSH_CACHE DRM_IOR(DRM_IGD_GMM_FLUSH_CACHE + BASE,\
829 emgd_drm_gmm_flush_cache_t)
830 #define DRM_IOCTL_IGD_PAN_DISPLAY DRM_IOWR(DRM_IGD_PAN_DISPLAY + BASE,\
831 emgd_drm_pan_display_t)
832 #define DRM_IOCTL_IGD_POWER_DISPLAY DRM_IOWR(DRM_IGD_POWER_DISPLAY + BASE,\
833 emgd_drm_power_display_t)
834 #define DRM_IOCTL_IGD_PWR_ALTER DRM_IOWR(DRM_IGD_PWR_ALTER + BASE,\
836 #define DRM_IOCTL_IGD_QUERY_DC DRM_IOWR(DRM_IGD_QUERY_DC + BASE,\
838 #define DRM_IOCTL_IGD_QUERY_MAX_SIZE_OVL DRM_IOWR(DRM_IGD_QUERY_MAX_SIZE_OVL +\
840 emgd_drm_query_max_size_ovl_t)
841 #define DRM_IOCTL_IGD_QUERY_OVL DRM_IOWR(DRM_IGD_QUERY_OVL + BASE,\
842 emgd_drm_query_ovl_t)
843 #define DRM_IOCTL_IGD_QUERY_MODE_LIST DRM_IOWR(DRM_IGD_QUERY_MODE_LIST + BASE,\
844 emgd_drm_query_mode_list_t)
845 #define DRM_IOCTL_IGD_GET_GOLDEN_HTOTAL DRM_IOWR(DRM_IGD_GET_GOLDEN_HTOTAL + BASE,\
846 emgd_drm_get_golden_htotal_t)
847 #define DRM_IOCTL_IGD_CONTROL_PLANE_FORMAT DRM_IOWR(DRM_IGD_CONTROL_PLANE_FORMAT + BASE,\
848 emgd_drm_control_plane_format_t)
849 #define DRM_IOCTL_IGD_SET_OVERLAY_DISPLAY DRM_IOWR(DRM_IGD_SET_OVERLAY_DISPLAY + BASE,\
850 emgd_drm_set_overlay_display_t)
851 #define DRM_IOCTL_IGD_SET_ATTRS DRM_IOWR(DRM_IGD_SET_ATTRS + BASE,\
852 emgd_drm_set_attrs_t)
853 #define DRM_IOCTL_IGD_SET_PALETTE_ENTRY DRM_IOWR(DRM_IGD_SET_PALETTE_ENTRY +\
855 emgd_drm_set_palette_entry_t)
856 #define DRM_IOCTL_IGD_SET_SURFACE DRM_IOWR(DRM_IGD_SET_SURFACE + BASE,\
857 emgd_drm_set_surface_t)
858 #define DRM_IOCTL_IGD_SYNC DRM_IOWR(DRM_IGD_SYNC + BASE,\
860 #define DRM_IOCTL_IGD_DRIVER_PRE_INIT DRM_IOWR(DRM_IGD_DRIVER_PRE_INIT + BASE,\
861 emgd_drm_driver_pre_init_t)
862 #define DRM_IOCTL_IGD_DRIVER_GET_PORTS DRM_IOWR(DRM_IGD_DRIVER_GET_PORTS + BASE,\
863 emgd_drm_driver_get_ports_t)
864 #define DRM_IOCTL_IGD_START_PVRSRV DRM_IOWR(DRM_IGD_START_PVRSRV + BASE,\
865 emgd_drm_start_pvrsrv_t)
866 #define DRM_IOCTL_IGD_TEST_PVRSRV DRM_IOWR(DRM_IGD_TEST_PVRSRV + BASE,\
867 emgd_drm_test_pvrsrv_t)
869 #define DRM_IOCTL_IGD_GET_OVL_INIT_PARAMS DRM_IOWR(DRM_IGD_GET_OVL_INIT_PARAMS + BASE,\
870 emgd_drm_get_ovl_init_params_t)
871 #define DRM_IOCTL_IGD_GET_CHIPSET_INFO DRM_IOWR(DRM_IGD_GET_CHIPSET_INFO + BASE,\
872 emgd_drm_driver_get_chipset_info_t)
873 #define DRM_IOCTL_IGD_QUERY_2D_CAPS_HWHINT DRM_IOWR(DRM_IGD_QUERY_2D_CAPS_HWHINT + BASE,\
874 emgd_drm_query_2d_caps_hwhint_t)
875 #define DRM_IOCTL_IGD_GET_DISPLAY_INFO DRM_IOR(DRM_IGD_GET_DISPLAY_INFO + BASE,\
876 emgd_drm_get_display_info_t)
878 #define DRM_IOCTL_IGD_DIHCLONE_SET_SURFACE DRM_IOWR(DRM_IGD_DIHCLONE_SET_SURFACE + BASE,\
879 emgd_drm_dihclone_set_surface_t)
881 #define DRM_IOCTL_IGD_WAIT_VBLANK DRM_IOWR(DRM_IGD_WAIT_VBLANK + BASE,\
882 emgd_drm_driver_set_sync_refresh_t)
885 /* From pvr_bridge.h */
886 #define DRM_IOCTL_IGD_RESERVED_1 DRM_IOW(DRM_IGD_RESERVED_1 + BASE, \
887 PVRSRV_BRIDGE_PACKAGE)
888 #define DRM_IOCTL_IGD_RESERVED_2 DRM_IO(DRM_IGD_RESERVED_2 + BASE)
889 #define DRM_IOCTL_IGD_RESERVED_3 DRM_IO(DRM_IGD_RESERVED_3 + BASE)
890 #define DRM_IOCTL_IGD_RESERVED_4 DRM_IO(DRM_IGD_RESERVED_4 + BASE)
891 #define DRM_IOCTL_IGD_RESERVED_5 DRM_IOWR(DRM_IGD_RESERVED_5 + BASE, \
893 #define DRM_IOCTL_IGD_RESERVED_6 DRM_IO(DRM_IGD_RESERVED_6 + BASE)
895 /* For Video (MXVDX/TOPAZ) */
896 #define DRM_IOCTL_IGD_VIDEO_CMD_BUF DRM_IOR(DRM_IGD_VIDEO_CMD_BUF + BASE,\
897 emgd_drm_video_cmd_buf_t)
898 #define DRM_IOCTL_IGD_GET_DEVICE_INFO DRM_IOR(DRM_IGD_GET_DEVICE_INFO + BASE,\
899 emgd_drm_device_info_t)
900 #define DRM_IOCTL_IGD_GET_PAGE_LIST DRM_IOR(DRM_IGD_GET_PAGE_LIST + BASE,\
901 emgd_drm_get_page_list_t)
902 #define DRM_IOCTL_IGD_INIT_VIDEO DRM_IOR(DRM_IGD_INIT_VIDEO + BASE,\
903 emgd_drm_init_video_t)
904 #define DRM_IOCTL_IGD_VIDEO_GET_INFO DRM_IOR(DRM_IGD_VIDEO_GET_INFO + BASE,\
905 emgd_drm_video_get_info_t)
906 #define DRM_IOCTL_IGD_VIDEO_FLUSH_TLB DRM_IOR(DRM_IGD_VIDEO_FLUSH_TLB + BASE,\
907 emgd_drm_video_flush_tlb_t)
908 #define DRM_IOCTL_IGD_PREINIT_MMU DRM_IOR(DRM_IGD_PREINIT_MMU + BASE,\
909 emgd_drm_preinit_mmu_t)
910 #define DRM_IOCTL_IGD_GET_DISPLAY_INFO DRM_IOR(DRM_IGD_GET_DISPLAY_INFO + BASE,\
911 emgd_drm_get_display_info_t)
912 /* For Buffer Class of Texture Stream */
913 #define DRM_IOCTL_IGD_BC_TS_INIT DRM_IOR(DRM_IGD_BC_TS_INIT + BASE,\
915 #define DRM_IOCTL_IGD_BC_TS_UNINIT DRM_IOR(DRM_IGD_BC_TS_UNINIT + BASE,\
917 #define DRM_IOCTL_IGD_BC_TS_REQUEST_BUFFERS DRM_IOR(DRM_IGD_BC_TS_REQUEST_BUFFERS + BASE,\
919 #define DRM_IOCTL_IGD_BC_TS_RELEASE_BUFFERS DRM_IOR(DRM_IGD_BC_TS_RELEASE_BUFFERS + BASE,\
921 #define DRM_IOCTL_IGD_BC_TS_SET_BUFFER_INFO DRM_IOR(DRM_IGD_BC_TS_SET_BUFFER_INFO + BASE,\
923 #define DRM_IOCTL_IGD_BC_TS_GET_BUFFERS_COUNT DRM_IOR(DRM_IGD_BC_TS_GET_BUFFERS_COUNT + BASE,\
925 #define DRM_IOCTL_IGD_BC_TS_GET_BUFFER_INDEX DRM_IOR(DRM_IGD_BC_TS_GET_BUFFER_INDEX + BASE,\