2 * Copyright 2003 Motorola,Inc.
3 * Xianghua Xiao(x.xiao@motorola.com)
13 unsigned long freqProcessor;
14 unsigned long freqSystemBus;
17 #endif /* _ASMLANGUAGE */
19 /* Motorola E500 core provides 16 TLB1 entries; they can be used for
20 * initial memory mapping like legacy BAT registers do. Usually we
21 * use four MAS registers(MAS0-3) to operate on TLB1 entries.
23 * We also need LAWs(Local Access Window) to associate a range of
24 * the local 32-bit address space with a particular target interface
25 * such as PCI/PCI-X, RapidIO, Local Bus and DDR SDRAM.
27 * We put TLB1/LAW code here because memory mapping is board-specific
28 * instead of cpu-specific.
32 * tlbsel(TLB Select):0,1
33 * esel(Entry Select): 0,1,2,...,15 for TLB1
36 #define TLB1_MAS0(tlbsel,esel,nv) \
37 ((((tlbsel) << 28) & MAS0_TLBSEL) |\
38 (((esel) << 16) & MAS0_ESEL ) |\
43 * v(TLB valid bit):0,1
44 * iprot(invalidate protect):0,1
45 * tid(translation identity):8bit to match process IDs
46 * ts(translation space,comparing with MSR[IS,DS]): 0,1
47 * tsize(translation size):1,2,...,9(4K,16K,64K,256K,1M,4M,16M,64M,256M)
49 #define TLB1_MAS1(v,iprot,tid,ts,tsize) \
50 ((((v) << 31) & MAS1_VALID) |\
51 (((iprot) << 30) & MAS1_IPROT) |\
52 (((tid) << 16) & MAS1_TID) |\
53 (((ts) << 12) & MAS1_TS) |\
54 (((tsize) << 8) & MAS1_TSIZE) )
58 * epn(effective page number):20bits
59 * sharen(Shared cache state):0,1
60 * x0,x1(implementation specific page attribute):0,1
61 * w,i,m,g,e(write-through,cache-inhibited,memory coherency,guarded,
64 #define TLB1_MAS2(epn,sharen,x0,x1,w,i,m,g,e) \
65 ((((epn) << 12) & MAS2_EPN) |\
66 (((sharen) << 9) & MAS2_SHAREN) |\
67 (((x0) << 6) & MAS2_X0) |\
68 (((x1) << 5) & MAS2_X1) |\
69 (((w) << 4) & MAS2_W) |\
70 (((i) << 3) & MAS2_I) |\
71 (((m) << 2) & MAS2_M) |\
72 (((g) << 1) & MAS2_G) |\
77 * rpn(real page number):20bits
78 * u0-u3(user bits, useful for page table management in OS):0,1
79 * ux,sx,uw,sw,ur,sr(permission bits, user and supervisor read,
80 * write,execute permission).
82 #define TLB1_MAS3(rpn,u0,u1,u2,u3,ux,sx,uw,sw,ur,sr) \
83 ((((rpn) << 12) & MAS3_RPN) |\
84 (((u0) << 9) & MAS3_U0) |\
85 (((u1) << 8) & MAS3_U1) |\
86 (((u2) << 7) & MAS3_U2) |\
87 (((u3) << 6) & MAS3_U3) |\
88 (((ux) << 5) & MAS3_UX) |\
89 (((sx) << 4) & MAS3_SX) |\
90 (((uw) << 3) & MAS3_UW) |\
91 (((sw) << 2) & MAS3_SW) |\
92 (((ur) << 1) & MAS3_UR) |\
96 #define RESET_VECTOR 0xfffffffc
97 #define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
100 #endif /* __E500_H__ */