include/dt-bindings/reset/qcom,ipq4019-reset.h

   1 /* Copyright (c) 2015 The Linux Foundation. All rights reserved.
   2  *
   3  * Permission to use, copy, modify, and/or distribute this software for any
   4  * purpose with or without fee is hereby granted, provided that the above
   5  * copyright notice and this permission notice appear in all copies.
   6  *
   7  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   8  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   9  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  10  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  11  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  12  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  13  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  14  *
  15  */
  16 #ifndef __QCOM_RESET_IPQ4019_H__
  17 #define __QCOM_RESET_IPQ4019_H__
  18
  19 #define WIFI0_CPU_INIT_RESET                            0
  20 #define WIFI0_RADIO_SRIF_RESET                          1
  21 #define WIFI0_RADIO_WARM_RESET                          2
  22 #define WIFI0_RADIO_COLD_RESET                          3
  23 #define WIFI0_CORE_WARM_RESET                           4
  24 #define WIFI0_CORE_COLD_RESET                           5
  25 #define WIFI1_CPU_INIT_RESET                            6
  26 #define WIFI1_RADIO_SRIF_RESET                          7
  27 #define WIFI1_RADIO_WARM_RESET                          8
  28 #define WIFI1_RADIO_COLD_RESET                          9
  29 #define WIFI1_CORE_WARM_RESET                           10
  30 #define WIFI1_CORE_COLD_RESET                           11
  31 #define USB3_UNIPHY_PHY_ARES                            12
  32 #define USB3_HSPHY_POR_ARES                             13
  33 #define USB3_HSPHY_S_ARES                               14
  34 #define USB2_HSPHY_POR_ARES                             15
  35 #define USB2_HSPHY_S_ARES                               16
  36 #define PCIE_PHY_AHB_ARES                               17
  37 #define PCIE_AHB_ARES                                   18
  38 #define PCIE_PWR_ARES                                   19
  39 #define PCIE_PIPE_STICKY_ARES                           20
  40 #define PCIE_AXI_M_STICKY_ARES                          21
  41 #define PCIE_PHY_ARES                                   22
  42 #define PCIE_PARF_XPU_ARES                              23
  43 #define PCIE_AXI_S_XPU_ARES                             24
  44 #define PCIE_AXI_M_VMIDMT_ARES                          25
  45 #define PCIE_PIPE_ARES                                  26
  46 #define PCIE_AXI_S_ARES                                 27
  47 #define PCIE_AXI_M_ARES                                 28
  48 #define ESS_RESET                                       29
  49 #define GCC_BLSP1_BCR                                   30
  50 #define GCC_BLSP1_QUP1_BCR                              31
  51 #define GCC_BLSP1_UART1_BCR                             32
  52 #define GCC_BLSP1_QUP2_BCR                              33
  53 #define GCC_BLSP1_UART2_BCR                             34
  54 #define GCC_BIMC_BCR                                    35
  55 #define GCC_TLMM_BCR                                    36
  56 #define GCC_IMEM_BCR                                    37
  57 #define GCC_ESS_BCR                                     38
  58 #define GCC_PRNG_BCR                                    39
  59 #define GCC_BOOT_ROM_BCR                                40
  60 #define GCC_CRYPTO_BCR                                  41
  61 #define GCC_SDCC1_BCR                                   42
  62 #define GCC_SEC_CTRL_BCR                                43
  63 #define GCC_AUDIO_BCR                                   44
  64 #define GCC_QPIC_BCR                                    45
  65 #define GCC_PCIE_BCR                                    46
  66 #define GCC_USB2_BCR                                    47
  67 #define GCC_USB2_PHY_BCR                                48
  68 #define GCC_USB3_BCR                                    49
  69 #define GCC_USB3_PHY_BCR                                50
  70 #define GCC_SYSTEM_NOC_BCR                              51
  71 #define GCC_PCNOC_BCR                                   52
  72 #define GCC_DCD_BCR                                     53
  73 #define GCC_SNOC_BUS_TIMEOUT0_BCR                       54
  74 #define GCC_SNOC_BUS_TIMEOUT1_BCR                       55
  75 #define GCC_SNOC_BUS_TIMEOUT2_BCR                       56
  76 #define GCC_SNOC_BUS_TIMEOUT3_BCR                       57
  77 #define GCC_PCNOC_BUS_TIMEOUT0_BCR                      58
  78 #define GCC_PCNOC_BUS_TIMEOUT1_BCR                      59
  79 #define GCC_PCNOC_BUS_TIMEOUT2_BCR                      60
  80 #define GCC_PCNOC_BUS_TIMEOUT3_BCR                      61
  81 #define GCC_PCNOC_BUS_TIMEOUT4_BCR                      62
  82 #define GCC_PCNOC_BUS_TIMEOUT5_BCR                      63
  83 #define GCC_PCNOC_BUS_TIMEOUT6_BCR                      64
  84 #define GCC_PCNOC_BUS_TIMEOUT7_BCR                      65
  85 #define GCC_PCNOC_BUS_TIMEOUT8_BCR                      66
  86 #define GCC_PCNOC_BUS_TIMEOUT9_BCR                      67
  87 #define GCC_TCSR_BCR                                    68
  88 #define GCC_QDSS_BCR                                    69
  89 #define GCC_MPM_BCR                                     70
  90 #define GCC_SPDM_BCR                                    71
  91
  92 #endif