1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2019 MediaTek Inc.
6 #ifndef _DT_BINDINGS_MTK_RESET_H_
7 #define _DT_BINDINGS_MTK_RESET_H_
9 /* PCIe/SATA Subsystem resets */
10 #define MT7622_SATA_PHY_REG_RST 12
11 #define MT7622_SATA_PHY_SW_RST 13
12 #define MT7622_SATA_AXI_BUS_RST 15
13 #define PCIE1_CORE_RST 19
14 #define PCIE1_MMIO_RST 20
16 #define PCIE1_USER_RST 22
17 #define PCIE1_PIPE_RST 23
18 #define PCIE0_CORE_RST 27
19 #define PCIE0_MMIO_RST 28
21 #define PCIE0_USER_RST 30
22 #define PCIE0_PIPE_RST 31
24 /* SSUSB Subsystem resets */
25 #define SSUSB_PHY_PWR_RST 3
26 #define SSUSB_MAC_PWR_RST 4
28 /* ETH Subsystem resets */
29 #define ETHSYS_SYS_RST 0
30 #define ETHSYS_MCM_RST 2
31 #define ETHSYS_HSDMA_RST 5
32 #define ETHSYS_FE_RST 6
33 #define ETHSYS_ESW_RST 16
34 #define ETHSYS_GMAC_RST 23
35 #define ETHSYS_EPHY_RST 24
36 #define ETHSYS_CRYPTO_RST 29
37 #define ETHSYS_PPE_RST 31
39 #endif /* _DT_BINDINGS_MTK_RESET_H_ */