1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
5 * Intel Quark MRC bindings include several properties
6 * as part of an Intel Quark MRC node. In most cases,
7 * the value of these properties uses the standard values
8 * defined in this header.
11 #ifndef _DT_BINDINGS_QRK_MRC_H_
12 #define _DT_BINDINGS_QRK_MRC_H_
14 /* MRC platform data flags */
15 #define MRC_FLAG_ECC_EN 0x00000001
16 #define MRC_FLAG_SCRAMBLE_EN 0x00000002
17 #define MRC_FLAG_MEMTEST_EN 0x00000004
18 /* 0b DDR "fly-by" topology else 1b DDR "tree" topology */
19 #define MRC_FLAG_TOP_TREE_EN 0x00000008
20 /* If set ODR signal is asserted to DRAM devices on writes */
21 #define MRC_FLAG_WR_ODT_EN 0x00000010
24 #define DRAM_WIDTH_X8 0
25 #define DRAM_WIDTH_X16 1
26 #define DRAM_WIDTH_X32 2
29 #define DRAM_FREQ_800 0
30 #define DRAM_FREQ_1066 1
33 #define DRAM_TYPE_DDR3 0
34 #define DRAM_TYPE_DDR3L 1
37 #define DRAM_RANK(n) (1 << (n))
39 /* DRAM channel mask */
40 #define DRAM_CHANNEL(n) (1 << (n))
42 /* DRAM channel width */
43 #define DRAM_CHANNEL_WIDTH_X8 0
44 #define DRAM_CHANNEL_WIDTH_X16 1
45 #define DRAM_CHANNEL_WIDTH_X32 2
47 /* DRAM address mode */
48 #define DRAM_ADDR_MODE0 0
49 #define DRAM_ADDR_MODE1 1
50 #define DRAM_ADDR_MODE2 2
52 /* DRAM refresh rate */
53 #define DRAM_REFRESH_RATE_195US 1
54 #define DRAM_REFRESH_RATE_39US 2
55 #define DRAM_REFRESH_RATE_785US 3
57 /* DRAM SR temprature range */
58 #define DRAM_SRT_RANGE_NORMAL 0
59 #define DRAM_SRT_RANGE_EXTENDED 1
62 #define DRAM_RON_34OHM 0
63 #define DRAM_RON_40OHM 1
65 /* DRAM rtt nom value */
66 #define DRAM_RTT_NOM_40OHM 0
67 #define DRAM_RTT_NOM_60OHM 1
68 #define DRAM_RTT_NOM_120OHM 2
70 /* DRAM rd odt value */
71 #define DRAM_RD_ODT_OFF 0
72 #define DRAM_RD_ODT_60OHM 1
73 #define DRAM_RD_ODT_120OHM 2
74 #define DRAM_RD_ODT_180OHM 3
77 #define DRAM_DENSITY_512M 0
78 #define DRAM_DENSITY_1G 1
79 #define DRAM_DENSITY_2G 2
80 #define DRAM_DENSITY_4G 3
82 #endif /* _DT_BINDINGS_QRK_MRC_H_ */