1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
7 #ifndef DT_BINDINGS_IMXRT_SDRAM_H
8 #define DT_BINDINGS_IMXRT_SDRAM_H
10 #define MEM_SIZE_4K 0x00
11 #define MEM_SIZE_8K 0x01
12 #define MEM_SIZE_16K 0x02
13 #define MEM_SIZE_32K 0x03
14 #define MEM_SIZE_64K 0x04
15 #define MEM_SIZE_128K 0x05
16 #define MEM_SIZE_256K 0x06
17 #define MEM_SIZE_512K 0x07
18 #define MEM_SIZE_1M 0x08
19 #define MEM_SIZE_2M 0x09
20 #define MEM_SIZE_4M 0x0A
21 #define MEM_SIZE_8M 0x0B
22 #define MEM_SIZE_16M 0x0C
23 #define MEM_SIZE_32M 0x0D
24 #define MEM_SIZE_64M 0x0E
25 #define MEM_SIZE_128M 0x0F
26 #define MEM_SIZE_256M 0x10
27 #define MEM_SIZE_512M 0x11
28 #define MEM_SIZE_1G 0x12
29 #define MEM_SIZE_2G 0x13
30 #define MEM_SIZE_4G 0x14
32 #define MUX_A8_SDRAM_A8 0x0
33 #define MUX_A8_NAND_CE 0x1
34 #define MUX_A8_NOR_CE 0x2
35 #define MUX_A8_PSRAM_CE 0x3
36 #define MUX_A8_DBI_CSX 0x4
38 #define MUX_CSX0_NOR_PSRAM_A24 0x0
39 #define MUX_CSX0_SDRAM_CS1 0x1
40 #define MUX_CSX0_SDRAM_CS2 0x2
41 #define MUX_CSX0_SDRAM_CS3 0x3
42 #define MUX_CSX0_NAND_CE 0x4
43 #define MUX_CSX0_NOR_CE 0x5
44 #define MUX_CSX0_PSRAM_CE 0x6
45 #define MUX_CSX0_DBI_CSX 0x7
47 #define MUX_CSX1_NOR_PSRAM_A25 0x0
48 #define MUX_CSX1_SDRAM_CS1 0x1
49 #define MUX_CSX1_SDRAM_CS2 0x2
50 #define MUX_CSX1_SDRAM_CS3 0x3
51 #define MUX_CSX1_NAND_CE 0x4
52 #define MUX_CSX1_NOR_CE 0x5
53 #define MUX_CSX1_PSRAM_CE 0x6
54 #define MUX_CSX1_DBI_CSX 0x7
56 #define MUX_CSX2_NOR_PSRAM_A26 0x0
57 #define MUX_CSX2_SDRAM_CS1 0x1
58 #define MUX_CSX2_SDRAM_CS2 0x2
59 #define MUX_CSX2_SDRAM_CS3 0x3
60 #define MUX_CSX2_NAND_CE 0x4
61 #define MUX_CSX2_NOR_CE 0x5
62 #define MUX_CSX2_PSRAM_CE 0x6
63 #define MUX_CSX2_DBI_CSX 0x7
65 #define MUX_CSX3_NOR_PSRAM_A27 0x0
66 #define MUX_CSX3_SDRAM_CS1 0x1
67 #define MUX_CSX3_SDRAM_CS2 0x2
68 #define MUX_CSX3_SDRAM_CS3 0x3
69 #define MUX_CSX3_NAND_CE 0x4
70 #define MUX_CSX3_NOR_CE 0x5
71 #define MUX_CSX3_PSRAM_CE 0x6
72 #define MUX_CSX3_DBI_CSX 0x7
74 #define MUX_RDY_NAND_RDY_WAIT 0x0
75 #define MUX_RDY_SDRAM_CS1 0x1
76 #define MUX_RDY_SDRAM_CS2 0x2
77 #define MUX_RDY_SDRAM_CS3 0x3
78 #define MUX_RDY_NOR_CE 0x4
79 #define MUX_RDY_PSRAM_CE 0x5
80 #define MUX_RDY_DBI_CSX 0x6
81 #define MUX_RDY_NOR_PSRAM_A27 0x7
83 #define MEM_WIDTH_8BITS 0x0
84 #define MEM_WIDTH_16BITS 0x1
91 #define COL_12BITS 0x0
92 #define COL_11BITS 0x1
93 #define COL_10BITS 0x2