include/dt-bindings/clock/starfive-jh7110-vout.h

   1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
   2 /*
   3  * Copyright 2022 StarFive, Inc <xingyu.wu@starfivetech.com>
   4  */
   5
   6 #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_VOUT_H__
   7 #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_VOUT_H__
   8
   9 /* regisger */
  10 #define JH7110_APB                                              0
  11 #define JH7110_DC8200_PIX0                                      1
  12 #define JH7110_DSI_SYS                                          2
  13 #define JH7110_TX_ESC                                           3
  14 #define JH7110_U0_DC8200_CLK_AXI                                4
  15 #define JH7110_U0_DC8200_CLK_CORE                               5
  16 #define JH7110_U0_DC8200_CLK_AHB                                6
  17 #define JH7110_U0_DC8200_CLK_PIX0                               7
  18 #define JH7110_U0_DC8200_CLK_PIX1                               8
  19 #define JH7110_DOM_VOUT_TOP_LCD_CLK                             9
  20 #define JH7110_U0_CDNS_DSITX_CLK_APB                            10
  21 #define JH7110_U0_CDNS_DSITX_CLK_SYS                            11
  22 #define JH7110_U0_CDNS_DSITX_CLK_DPI                            12
  23 #define JH7110_U0_CDNS_DSITX_CLK_TXESC                          13
  24 #define JH7110_U0_MIPITX_DPHY_CLK_TXESC                         14
  25 #define JH7110_U0_HDMI_TX_CLK_MCLK                              15
  26 #define JH7110_U0_HDMI_TX_CLK_BCLK                              16
  27 #define JH7110_U0_HDMI_TX_CLK_SYS                               17
  28
  29 #define JH7110_CLK_VOUT_REG_END                                 18
  30
  31 /* other */
  32 #define JH7110_DISP_ROOT                                        18
  33 #define JH7110_DISP_AXI                                         19
  34 #define JH7110_DISP_AHB                                         20
  35 #define JH7110_HDMI_PHY_REF                                     21
  36 #define JH7110_HDMITX0_MCLK                                     22
  37 #define JH7110_HDMITX0_SCK                                      23
  38
  39 #define JH7110_MIPI_DPHY_REF                                    24
  40 #define JH7110_U0_PCLK_MUX_BIST_PCLK                            25
  41 #define JH7110_DISP_APB                                         26
  42 #define JH7110_U0_PCLK_MUX_FUNC_PCLK                            27
  43 #define JH7110_U0_DOM_VOUT_CRG_PCLK                             28
  44 #define JH7110_U0_DOM_VOUT_SYSCON_PCLK                          29
  45 #define JH7110_U0_SAIF_AMBA_DOM_VOUT_AHB_DEC_CLK_AHB            30
  46 #define JH7110_U0_AHB2APB_CLK_AHB                               31
  47 #define JH7110_U0_P2P_ASYNC_CLK_APBS                            32
  48 #define JH7110_U0_CDNS_DSITX_CLK_RXESC                          33
  49 #define JH7110_U0_CDNS_DSITX_CLK_TXBYTEHS                       34
  50 #define JH7110_U0_MIPITX_DPHY_CLK_SYS                           35
  51 #define JH7110_U0_MIPITX_DPHY_CLK_DPHY_REF                      36
  52 #define JH7110_U0_MIPITX_APBIF_PCLK                             37
  53 #define JH7110_HDMI_TX_CLK_REF                                  38
  54 #define JH7110_U0_DC8200_CLK_PIX0_OUT                           39
  55 #define JH7110_U0_DC8200_CLK_PIX1_OUT                           40
  56
  57 #define JH7110_CLK_VOUT_END                                     41
  58
  59 /* external clocks */
  60 #define JH7110_HDMITX0_PIXELCLK                 (JH7110_CLK_VOUT_END + 0)
  61 #define JH7110_MIPITX_DPHY_RXESC                (JH7110_CLK_VOUT_END + 1)
  62 #define JH7110_MIPITX_DPHY_TXBYTEHS             (JH7110_CLK_VOUT_END + 2)
  63
  64
  65
  66 #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */