include/dt-bindings/clock/starfive-jh7110-isp.h

   1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
   2 /*
   3  * Copyright 2022 StarFive, Inc <xingyu.wu@starfivetech.com>
   4  */
   5
   6 #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_ISP_H__
   7 #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_ISP_H__
   8
   9 /* regisger */
  10 #define JH7110_DOM4_APB_FUNC                                    0
  11 #define JH7110_MIPI_RX0_PXL                                     1
  12 #define JH7110_DVP_INV                                          2
  13 #define JH7110_U0_M31DPHY_CFGCLK_IN                             3
  14 #define JH7110_U0_M31DPHY_REFCLK_IN                             4
  15 #define JH7110_U0_M31DPHY_TXCLKESC_LAN0                         5
  16 #define JH7110_U0_VIN_PCLK                                      6
  17 #define JH7110_U0_VIN_SYS_CLK                                   7
  18 #define JH7110_U0_VIN_PIXEL_CLK_IF0                             8
  19 #define JH7110_U0_VIN_PIXEL_CLK_IF1                             9
  20 #define JH7110_U0_VIN_PIXEL_CLK_IF2                             10
  21 #define JH7110_U0_VIN_PIXEL_CLK_IF3                             11
  22 #define JH7110_U0_VIN_CLK_P_AXIWR                               12
  23 #define JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C                       13
  24
  25 #define JH7110_CLK_ISP_REG_END                                  14
  26
  27 /* other */
  28 #define JH7110_U3_PCLK_MUX_FUNC_PCLK                            14
  29 #define JH7110_U3_PCLK_MUX_BIST_PCLK                            15
  30 #define JH7110_DOM4_APB                                         16
  31 #define JH7110_U0_VIN_PCLK_FREE                                 17
  32 #define JH7110_U0_VIN_CLK_P_AXIRD                               18
  33 #define JH7110_U0_VIN_ACLK                                      19
  34 #define JH7110_U0_ISPV2_TOP_WRAPPER_CLK_ISP_AXI_IN              20
  35 #define JH7110_U0_ISPV2_TOP_WRAPPER_CLK_ISP_X2                  21
  36 #define JH7110_U0_ISPV2_TOP_WRAPPER_CLK_ISP                     22
  37 #define JH7110_U0_ISPV2_TOP_WRAPPER_CLK_P                       23
  38 #define JH7110_U0_CRG_PCLK                                      24
  39 #define JH7110_U0_SYSCON_PCLK                                   25
  40 #define JH7110_U0_M31DPHY_APBCFG_PCLK                           26
  41 #define JH7110_U0_AXI2APB_BRIDGE_CLK_DOM4_APB                   27
  42 #define JH7110_U0_AXI2APB_BRIDGE_ISP_AXI4SLV_CLK                28
  43 #define JH7110_U3_PCLK_MUX_PCLK                                 29
  44
  45 #define JH7110_CLK_ISP_END                                      30
  46
  47 #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */