include/dt-bindings/clock/starfive,jh7110-crg.h

   1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
   2 /*
   3  * Copyright 2022 Emil Renner Berthing <kernel@esmil.dk>
   4  * Copyright 2022 StarFive Technology Co., Ltd.
   5  */
   6
   7 #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
   8 #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
   9
  10 /* SYSCRG clocks */
  11 #define JH7110_SYSCLK_CPU_ROOT                  0
  12 #define JH7110_SYSCLK_CPU_CORE                  1
  13 #define JH7110_SYSCLK_CPU_BUS                   2
  14 #define JH7110_SYSCLK_GPU_ROOT                  3
  15 #define JH7110_SYSCLK_PERH_ROOT                 4
  16 #define JH7110_SYSCLK_BUS_ROOT                  5
  17 #define JH7110_SYSCLK_NOCSTG_BUS                6
  18 #define JH7110_SYSCLK_AXI_CFG0                  7
  19 #define JH7110_SYSCLK_STG_AXIAHB                8
  20 #define JH7110_SYSCLK_AHB0                      9
  21 #define JH7110_SYSCLK_AHB1                      10
  22 #define JH7110_SYSCLK_APB_BUS                   11
  23 #define JH7110_SYSCLK_APB0                      12
  24 #define JH7110_SYSCLK_PLL0_DIV2                 13
  25 #define JH7110_SYSCLK_PLL1_DIV2                 14
  26 #define JH7110_SYSCLK_PLL2_DIV2                 15
  27 #define JH7110_SYSCLK_AUDIO_ROOT                16
  28 #define JH7110_SYSCLK_MCLK_INNER                17
  29 #define JH7110_SYSCLK_MCLK                      18
  30 #define JH7110_SYSCLK_MCLK_OUT                  19
  31 #define JH7110_SYSCLK_ISP_2X                    20
  32 #define JH7110_SYSCLK_ISP_AXI                   21
  33 #define JH7110_SYSCLK_GCLK0                     22
  34 #define JH7110_SYSCLK_GCLK1                     23
  35 #define JH7110_SYSCLK_GCLK2                     24
  36 #define JH7110_SYSCLK_CORE                      25
  37 #define JH7110_SYSCLK_CORE1                     26
  38 #define JH7110_SYSCLK_CORE2                     27
  39 #define JH7110_SYSCLK_CORE3                     28
  40 #define JH7110_SYSCLK_CORE4                     29
  41 #define JH7110_SYSCLK_DEBUG                     30
  42 #define JH7110_SYSCLK_RTC_TOGGLE                31
  43 #define JH7110_SYSCLK_TRACE0                    32
  44 #define JH7110_SYSCLK_TRACE1                    33
  45 #define JH7110_SYSCLK_TRACE2                    34
  46 #define JH7110_SYSCLK_TRACE3                    35
  47 #define JH7110_SYSCLK_TRACE4                    36
  48 #define JH7110_SYSCLK_TRACE_COM                 37
  49 #define JH7110_SYSCLK_NOC_BUS_CPU_AXI           38
  50 #define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI       39
  51 #define JH7110_SYSCLK_OSC_DIV2                  40
  52 #define JH7110_SYSCLK_PLL1_DIV4                 41
  53 #define JH7110_SYSCLK_PLL1_DIV8                 42
  54 #define JH7110_SYSCLK_DDR_BUS                   43
  55 #define JH7110_SYSCLK_DDR_AXI                   44
  56 #define JH7110_SYSCLK_GPU_CORE                  45
  57 #define JH7110_SYSCLK_GPU_CORE_CLK              46
  58 #define JH7110_SYSCLK_GPU_SYS_CLK               47
  59 #define JH7110_SYSCLK_GPU_APB                   48
  60 #define JH7110_SYSCLK_GPU_RTC_TOGGLE            49
  61 #define JH7110_SYSCLK_NOC_BUS_GPU_AXI           50
  62 #define JH7110_SYSCLK_ISP_TOP_CORE              51
  63 #define JH7110_SYSCLK_ISP_TOP_AXI               52
  64 #define JH7110_SYSCLK_NOC_BUS_ISP_AXI           53
  65 #define JH7110_SYSCLK_HIFI4_CORE                54
  66 #define JH7110_SYSCLK_HIFI4_AXI                 55
  67 #define JH7110_SYSCLK_AXI_CFG1_MAIN             56
  68 #define JH7110_SYSCLK_AXI_CFG1_AHB              57
  69 #define JH7110_SYSCLK_VOUT_SRC                  58
  70 #define JH7110_SYSCLK_VOUT_AXI                  59
  71 #define JH7110_SYSCLK_NOC_BUS_DISP_AXI          60
  72 #define JH7110_SYSCLK_VOUT_TOP_AHB              61
  73 #define JH7110_SYSCLK_VOUT_TOP_AXI              62
  74 #define JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK     63
  75 #define JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF      64
  76 #define JH7110_SYSCLK_JPEGC_AXI                 65
  77 #define JH7110_SYSCLK_CODAJ12_AXI               66
  78 #define JH7110_SYSCLK_CODAJ12_CORE              67
  79 #define JH7110_SYSCLK_CODAJ12_APB               68
  80 #define JH7110_SYSCLK_VDEC_AXI                  69
  81 #define JH7110_SYSCLK_WAVE511_AXI               70
  82 #define JH7110_SYSCLK_WAVE511_BPU               71
  83 #define JH7110_SYSCLK_WAVE511_VCE               72
  84 #define JH7110_SYSCLK_WAVE511_APB               73
  85 #define JH7110_SYSCLK_VDEC_JPG                  74
  86 #define JH7110_SYSCLK_VDEC_MAIN                 75
  87 #define JH7110_SYSCLK_NOC_BUS_VDEC_AXI          76
  88 #define JH7110_SYSCLK_VENC_AXI                  77
  89 #define JH7110_SYSCLK_WAVE420L_AXI              78
  90 #define JH7110_SYSCLK_WAVE420L_BPU              79
  91 #define JH7110_SYSCLK_WAVE420L_VCE              80
  92 #define JH7110_SYSCLK_WAVE420L_APB              81
  93 #define JH7110_SYSCLK_NOC_BUS_VENC_AXI          82
  94 #define JH7110_SYSCLK_AXI_CFG0_MAIN_DIV         83
  95 #define JH7110_SYSCLK_AXI_CFG0_MAIN             84
  96 #define JH7110_SYSCLK_AXI_CFG0_HIFI4            85
  97 #define JH7110_SYSCLK_AXIMEM2_AXI               86
  98 #define JH7110_SYSCLK_QSPI_AHB                  87
  99 #define JH7110_SYSCLK_QSPI_APB                  88
 100 #define JH7110_SYSCLK_QSPI_REF_SRC              89
 101 #define JH7110_SYSCLK_QSPI_REF                  90
 102 #define JH7110_SYSCLK_SDIO0_AHB                 91
 103 #define JH7110_SYSCLK_SDIO1_AHB                 92
 104 #define JH7110_SYSCLK_SDIO0_SDCARD              93
 105 #define JH7110_SYSCLK_SDIO1_SDCARD              94
 106 #define JH7110_SYSCLK_USB_125M                  95
 107 #define JH7110_SYSCLK_NOC_BUS_STG_AXI           96
 108 #define JH7110_SYSCLK_GMAC1_AHB                 97
 109 #define JH7110_SYSCLK_GMAC1_AXI                 98
 110 #define JH7110_SYSCLK_GMAC_SRC                  99
 111 #define JH7110_SYSCLK_GMAC1_GTXCLK              100
 112 #define JH7110_SYSCLK_GMAC1_RMII_RTX            101
 113 #define JH7110_SYSCLK_GMAC1_PTP                 102
 114 #define JH7110_SYSCLK_GMAC1_RX                  103
 115 #define JH7110_SYSCLK_GMAC1_RX_INV              104
 116 #define JH7110_SYSCLK_GMAC1_TX                  105
 117 #define JH7110_SYSCLK_GMAC1_TX_INV              106
 118 #define JH7110_SYSCLK_GMAC1_GTXC                107
 119 #define JH7110_SYSCLK_GMAC0_GTXCLK              108
 120 #define JH7110_SYSCLK_GMAC0_PTP                 109
 121 #define JH7110_SYSCLK_GMAC_PHY                  110
 122 #define JH7110_SYSCLK_GMAC0_GTXC                111
 123 #define JH7110_SYSCLK_IOMUX_APB                 112
 124 #define JH7110_SYSCLK_MAILBOX_APB               113
 125 #define JH7110_SYSCLK_INT_CTRL_APB              114
 126 #define JH7110_SYSCLK_CAN0_APB                  115
 127 #define JH7110_SYSCLK_CAN0_TIMER                116
 128 #define JH7110_SYSCLK_CAN0_CAN                  117
 129 #define JH7110_SYSCLK_CAN1_APB                  118
 130 #define JH7110_SYSCLK_CAN1_TIMER                119
 131 #define JH7110_SYSCLK_CAN1_CAN                  120
 132 #define JH7110_SYSCLK_PWM_APB                   121
 133 #define JH7110_SYSCLK_WDT_APB                   122
 134 #define JH7110_SYSCLK_WDT_CORE                  123
 135 #define JH7110_SYSCLK_TIMER_APB                 124
 136 #define JH7110_SYSCLK_TIMER0                    125
 137 #define JH7110_SYSCLK_TIMER1                    126
 138 #define JH7110_SYSCLK_TIMER2                    127
 139 #define JH7110_SYSCLK_TIMER3                    128
 140 #define JH7110_SYSCLK_TEMP_APB                  129
 141 #define JH7110_SYSCLK_TEMP_CORE                 130
 142 #define JH7110_SYSCLK_SPI0_APB                  131
 143 #define JH7110_SYSCLK_SPI1_APB                  132
 144 #define JH7110_SYSCLK_SPI2_APB                  133
 145 #define JH7110_SYSCLK_SPI3_APB                  134
 146 #define JH7110_SYSCLK_SPI4_APB                  135
 147 #define JH7110_SYSCLK_SPI5_APB                  136
 148 #define JH7110_SYSCLK_SPI6_APB                  137
 149 #define JH7110_SYSCLK_I2C0_APB                  138
 150 #define JH7110_SYSCLK_I2C1_APB                  139
 151 #define JH7110_SYSCLK_I2C2_APB                  140
 152 #define JH7110_SYSCLK_I2C3_APB                  141
 153 #define JH7110_SYSCLK_I2C4_APB                  142
 154 #define JH7110_SYSCLK_I2C5_APB                  143
 155 #define JH7110_SYSCLK_I2C6_APB                  144
 156 #define JH7110_SYSCLK_UART0_APB                 145
 157 #define JH7110_SYSCLK_UART0_CORE                146
 158 #define JH7110_SYSCLK_UART1_APB                 147
 159 #define JH7110_SYSCLK_UART1_CORE                148
 160 #define JH7110_SYSCLK_UART2_APB                 149
 161 #define JH7110_SYSCLK_UART2_CORE                150
 162 #define JH7110_SYSCLK_UART3_APB                 151
 163 #define JH7110_SYSCLK_UART3_CORE                152
 164 #define JH7110_SYSCLK_UART4_APB                 153
 165 #define JH7110_SYSCLK_UART4_CORE                154
 166 #define JH7110_SYSCLK_UART5_APB                 155
 167 #define JH7110_SYSCLK_UART5_CORE                156
 168 #define JH7110_SYSCLK_PWMDAC_APB                157
 169 #define JH7110_SYSCLK_PWMDAC_CORE               158
 170 #define JH7110_SYSCLK_SPDIF_APB                 159
 171 #define JH7110_SYSCLK_SPDIF_CORE                160
 172 #define JH7110_SYSCLK_I2STX0_APB                161
 173 #define JH7110_SYSCLK_I2STX0_BCLK_MST           162
 174 #define JH7110_SYSCLK_I2STX0_BCLK_MST_INV       163
 175 #define JH7110_SYSCLK_I2STX0_LRCK_MST           164
 176 #define JH7110_SYSCLK_I2STX0_BCLK               165
 177 #define JH7110_SYSCLK_I2STX0_BCLK_INV           166
 178 #define JH7110_SYSCLK_I2STX0_LRCK               167
 179 #define JH7110_SYSCLK_I2STX1_APB                168
 180 #define JH7110_SYSCLK_I2STX1_BCLK_MST           169
 181 #define JH7110_SYSCLK_I2STX1_BCLK_MST_INV       170
 182 #define JH7110_SYSCLK_I2STX1_LRCK_MST           171
 183 #define JH7110_SYSCLK_I2STX1_BCLK               172
 184 #define JH7110_SYSCLK_I2STX1_BCLK_INV           173
 185 #define JH7110_SYSCLK_I2STX1_LRCK               174
 186 #define JH7110_SYSCLK_I2SRX_APB                 175
 187 #define JH7110_SYSCLK_I2SRX_BCLK_MST            176
 188 #define JH7110_SYSCLK_I2SRX_BCLK_MST_INV        177
 189 #define JH7110_SYSCLK_I2SRX_LRCK_MST            178
 190 #define JH7110_SYSCLK_I2SRX_BCLK                179
 191 #define JH7110_SYSCLK_I2SRX_BCLK_INV            180
 192 #define JH7110_SYSCLK_I2SRX_LRCK                181
 193 #define JH7110_SYSCLK_PDM_DMIC                  182
 194 #define JH7110_SYSCLK_PDM_APB                   183
 195 #define JH7110_SYSCLK_TDM_AHB                   184
 196 #define JH7110_SYSCLK_TDM_APB                   185
 197 #define JH7110_SYSCLK_TDM_INTERNAL              186
 198 #define JH7110_SYSCLK_TDM_TDM                   187
 199 #define JH7110_SYSCLK_TDM_TDM_INV               188
 200 #define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG   189
 201
 202 #define JH7110_SYSCLK_END                       190
 203
 204 /* AONCRG clocks */
 205 #define JH7110_AONCLK_OSC_DIV4                  0
 206 #define JH7110_AONCLK_APB_FUNC                  1
 207 #define JH7110_AONCLK_GMAC0_AHB                 2
 208 #define JH7110_AONCLK_GMAC0_AXI                 3
 209 #define JH7110_AONCLK_GMAC0_RMII_RTX            4
 210 #define JH7110_AONCLK_GMAC0_TX                  5
 211 #define JH7110_AONCLK_GMAC0_TX_INV              6
 212 #define JH7110_AONCLK_GMAC0_RX                  7
 213 #define JH7110_AONCLK_GMAC0_RX_INV              8
 214 #define JH7110_AONCLK_OTPC_APB                  9
 215 #define JH7110_AONCLK_RTC_APB                   10
 216 #define JH7110_AONCLK_RTC_INTERNAL              11
 217 #define JH7110_AONCLK_RTC_32K                   12
 218 #define JH7110_AONCLK_RTC_CAL                   13
 219
 220 #define JH7110_AONCLK_END                       14
 221
 222 /* STGCRG clocks */
 223 #define JH7110_STGCLK_HIFI4_CLK_CORE            0
 224 #define JH7110_STGCLK_USB0_APB                  1
 225 #define JH7110_STGCLK_USB0_UTMI_APB             2
 226 #define JH7110_STGCLK_USB0_AXI                  3
 227 #define JH7110_STGCLK_USB0_LPM                  4
 228 #define JH7110_STGCLK_USB0_STB                  5
 229 #define JH7110_STGCLK_USB0_APP_125              6
 230 #define JH7110_STGCLK_USB0_REFCLK               7
 231 #define JH7110_STGCLK_PCIE0_AXI_MST0            8
 232 #define JH7110_STGCLK_PCIE0_APB                 9
 233 #define JH7110_STGCLK_PCIE0_TL                  10
 234 #define JH7110_STGCLK_PCIE1_AXI_MST0            11
 235 #define JH7110_STGCLK_PCIE1_APB                 12
 236 #define JH7110_STGCLK_PCIE1_TL                  13
 237 #define JH7110_STGCLK_PCIE_SLV_MAIN             14
 238 #define JH7110_STGCLK_SEC_AHB                   15
 239 #define JH7110_STGCLK_SEC_MISC_AHB              16
 240 #define JH7110_STGCLK_GRP0_MAIN                 17
 241 #define JH7110_STGCLK_GRP0_BUS                  18
 242 #define JH7110_STGCLK_GRP0_STG                  19
 243 #define JH7110_STGCLK_GRP1_MAIN                 20
 244 #define JH7110_STGCLK_GRP1_BUS                  21
 245 #define JH7110_STGCLK_GRP1_STG                  22
 246 #define JH7110_STGCLK_GRP1_HIFI                 23
 247 #define JH7110_STGCLK_E2_RTC                    24
 248 #define JH7110_STGCLK_E2_CORE                   25
 249 #define JH7110_STGCLK_E2_DBG                    26
 250 #define JH7110_STGCLK_DMA1P_AXI                 27
 251 #define JH7110_STGCLK_DMA1P_AHB                 28
 252
 253 #define JH7110_STGCLK_END                       29
 254
 255 /* ISPCRG clocks */
 256 #define JH7110_ISPCLK_DOM4_APB_FUNC             0
 257 #define JH7110_ISPCLK_MIPI_RX0_PXL              1
 258 #define JH7110_ISPCLK_DVP_INV                   2
 259 #define JH7110_ISPCLK_M31DPHY_CFG_IN            3
 260 #define JH7110_ISPCLK_M31DPHY_REF_IN            4
 261 #define JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0       5
 262 #define JH7110_ISPCLK_VIN_ABP                   6
 263 #define JH7110_ISPCLK_VIN_SYS                   7
 264 #define JH7110_ISPCLK_VIN_PIXEL_IF0             8
 265 #define JH7110_ISPCLK_VIN_PIXEL_IF1             9
 266 #define JH7110_ISPCLK_VIN_PIXEL_IF2             10
 267 #define JH7110_ISPCLK_VIN_PIXEL_IF3             11
 268 #define JH7110_ISPCLK_VIN_P_AXI_WR              12
 269 #define JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C       13
 270
 271 #define JH7110_ISPCLK_END                       14
 272
 273 #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */