1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
4 * Author: Shawn Lin <shawn.lin@rock-chips.com>
7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
8 #define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
16 /* sclk gates (special clocks) */
28 #define SCLK_TIMER0 78
29 #define SCLK_TIMER1 79
31 #define SCLK_SDMMC_DRV 81
32 #define SCLK_SDIO_DRV 82
33 #define SCLK_EMMC_DRV 83
34 #define SCLK_SDMMC_SAMPLE 84
35 #define SCLK_SDIO_SAMPLE 85
36 #define SCLK_EMMC_SAMPLE 86
37 #define SCLK_VENC_CORE 87
38 #define SCLK_HEVC_CORE 88
39 #define SCLK_HEVC_CABAC 89
40 #define SCLK_PWM0_PMU 90
41 #define SCLK_I2C0_PMU 91
43 #define SCLK_CIFOUT 93
44 #define SCLK_MIPI_CSI_OUT 94
50 #define SCLK_DSP_IOP 100
51 #define SCLK_DSP_EPP 101
52 #define SCLK_DSP_EDP 102
53 #define SCLK_DSP_EDAP 103
54 #define SCLK_CVBS_HOST 104
55 #define SCLK_HDMI_SFR 105
56 #define SCLK_HDMI_CEC 106
57 #define SCLK_CRYPTO 107
59 #define SCLK_SARADC 109
60 #define SCLK_TSADC 110
61 #define SCLK_MAC_PRE 111
63 #define SCLK_MAC_RX 113
64 #define SCLK_MAC_REF 114
65 #define SCLK_MAC_REFOUT 115
66 #define SCLK_DSP_PFM 116
73 #define SCLK_USBPHY 123
74 #define SCLK_I2S0_SRC 124
75 #define SCLK_I2S1_SRC 125
76 #define SCLK_I2S2_SRC 126
77 #define SCLK_UART0_SRC 127
78 #define SCLK_UART1_SRC 128
79 #define SCLK_UART2_SRC 129
80 #define SCLK_MAC_TX 130
81 #define SCLK_MACREF 131
82 #define SCLK_MACREF_OUT 132
84 #define DCLK_VOP_SRC 185
85 #define DCLK_HDMIPHY 186
92 #define ACLK_ENMCORE 195
93 #define ACLK_RKVENC 196
94 #define ACLK_RKVDEC 197
103 #define ACLK_CIF1 206
104 #define ACLK_CIF2 207
105 #define ACLK_CIF3 208
106 #define ACLK_PERI 209
107 #define ACLK_GMAC 210
110 #define PCLK_GPIO1 256
111 #define PCLK_GPIO2 257
112 #define PCLK_GPIO3 258
114 #define PCLK_I2C1 260
115 #define PCLK_I2C2 261
116 #define PCLK_I2C3 262
119 #define PCLK_UART0 265
120 #define PCLK_UART1 266
121 #define PCLK_UART2 267
122 #define PCLK_TSADC 268
124 #define PCLK_TIMER 270
125 #define PCLK_PERI 271
126 #define PCLK_GPIO0_PMU 272
127 #define PCLK_I2C0_PMU 273
128 #define PCLK_PWM0_PMU 274
131 #define PCLK_MIPI_DSI 277
132 #define PCLK_HDMI_CTRL 278
133 #define PCLK_SARADC 279
134 #define PCLK_DSP_CFG 280
136 #define PCLK_EFUSE0 282
137 #define PCLK_EFUSE1 283
139 #define PCLK_GMAC 285
142 #define HCLK_I2S0_8CH 320
143 #define HCLK_I2S1_2CH 321
144 #define HCLK_I2S2_2CH 322
145 #define HCLK_NANDC 323
146 #define HCLK_SDMMC 324
147 #define HCLK_SDIO 325
148 #define HCLK_EMMC 326
149 #define HCLK_PERI 327
151 #define HCLK_RKVENC 329
152 #define HCLK_RKVDEC 330
153 #define HCLK_CIF0 331
159 #define HCLK_CRYPTO_MST 337
160 #define HCLK_CRYPTO_SLV 338
161 #define HCLK_HOST0 339
163 #define HCLK_CIF1 341
164 #define HCLK_CIF2 342
165 #define HCLK_CIF3 343
169 #define CLK_NR_CLKS (HCLK_VPU + 1)
172 #define SRST_CORE_PO_AD 0
173 #define SRST_CORE_AD 1
175 #define SRST_CPU_NIU_AD 3
176 #define SRST_CORE_PO 4
179 #define SRST_CORE_DBG 8
182 #define PRST_DBG_NIU 11
183 #define ARST_STRC_SYS_AD 15
185 #define SRST_DDRPHY_CLKDIV 16
186 #define SRST_DDRPHY 17
187 #define PRST_DDRPHY 18
188 #define PRST_HDMIPHY 19
189 #define PRST_VDACPHY 20
190 #define PRST_VADCPHY 21
191 #define PRST_MIPI_CSI_PHY 22
192 #define PRST_MIPI_DSI_PHY 23
193 #define PRST_ACODEC 24
194 #define ARST_BUS_NIU 25
195 #define PRST_TOP_NIU 26
196 #define ARST_INTMEM 27
199 #define SRST_MSCH_NIU 30
200 #define PRST_MSCH_NIU 31
202 #define PRST_DDRUPCTL 32
203 #define NRST_DDRUPCTL 33
204 #define PRST_DDRMON 34
205 #define HRST_I2S0_8CH 35
206 #define MRST_I2S0_8CH 36
207 #define HRST_I2S1_2CH 37
208 #define MRST_IS21_2CH 38
209 #define HRST_I2S2_2CH 39
210 #define MRST_I2S2_2CH 40
211 #define HRST_CRYPTO 41
212 #define SRST_CRYPTO 42
215 #define PRST_UART0 45
216 #define PRST_UART1 46
217 #define PRST_UART2 47
219 #define SRST_UART0 48
220 #define SRST_UART1 49
221 #define SRST_UART2 50
231 #define PRST_GPIO1 62
232 #define PRST_GPIO2 63
234 #define PRST_GPIO3 64
236 #define PRST_EFUSE 66
237 #define PRST_EFUSE512 67
238 #define PRST_TIMER0 68
239 #define SRST_TIMER0 69
240 #define SRST_TIMER1 70
241 #define PRST_TSADC 71
242 #define SRST_TSADC 72
243 #define PRST_SARADC 73
244 #define SRST_SARADC 74
245 #define HRST_SYSBUS 75
246 #define PRST_USBGRF 76
248 #define ARST_PERIPH_NIU 80
249 #define HRST_PERIPH_NIU 81
250 #define PRST_PERIPH_NIU 82
251 #define HRST_PERIPH 83
252 #define HRST_SDMMC 84
255 #define HRST_NANDC 87
256 #define NRST_NANDC 88
262 #define SRST_OTG_ADP 94
263 #define HRST_HOST0 95
265 #define HRST_HOST0_AUX 96
266 #define HRST_HOST0_ARB 97
267 #define SRST_HOST0_EHCIPHY 98
268 #define SRST_HOST0_UTMI 99
269 #define SRST_USBPOR 100
270 #define SRST_UTMI0 101
271 #define SRST_UTMI1 102
273 #define ARST_VIO0_NIU 102
274 #define ARST_VIO1_NIU 103
275 #define HRST_VIO_NIU 104
276 #define PRST_VIO_NIU 105
285 #define PRST_CVBS 114
286 #define PRST_HDMI 115
287 #define SRST_HDMI 116
288 #define PRST_MIPI_DSI 117
290 #define ARST_ISP_NIU 118
291 #define HRST_ISP_NIU 119
294 #define ARST_VIP0 122
295 #define HRST_VIP0 123
296 #define PRST_VIP0 124
297 #define ARST_VIP1 125
298 #define HRST_VIP1 126
299 #define PRST_VIP1 127
300 #define ARST_VIP2 128
301 #define HRST_VIP2 129
302 #define PRST_VIP2 120
303 #define ARST_VIP3 121
304 #define HRST_VIP3 122
305 #define PRST_VIP4 123
307 #define PRST_CIF1TO4 124
308 #define SRST_CVBS_CLK 125
309 #define HRST_CVBS 126
311 #define ARST_VPU_NIU 140
312 #define HRST_VPU_NIU 141
315 #define ARST_RKVDEC_NIU 144
316 #define HRST_RKVDEC_NIU 145
317 #define ARST_RKVDEC 146
318 #define HRST_RKVDEC 147
319 #define SRST_RKVDEC_CABAC 148
320 #define SRST_RKVDEC_CORE 149
321 #define ARST_RKVENC_NIU 150
322 #define HRST_RKVENC_NIU 151
323 #define ARST_RKVENC 152
324 #define HRST_RKVENC 153
325 #define SRST_RKVENC_CORE 154
327 #define SRST_DSP_CORE 156
328 #define SRST_DSP_SYS 157
329 #define SRST_DSP_GLOBAL 158
330 #define SRST_DSP_OECM 159
331 #define PRST_DSP_IOP_NIU 160
332 #define ARST_DSP_EPP_NIU 161
333 #define ARST_DSP_EDP_NIU 162
334 #define PRST_DSP_DBG_NIU 163
335 #define PRST_DSP_CFG_NIU 164
336 #define PRST_DSP_GRF 165
337 #define PRST_DSP_MAILBOX 166
338 #define PRST_DSP_INTC 167
339 #define PRST_DSP_PFM_MON 169
340 #define SRST_DSP_PFM_MON 170
341 #define ARST_DSP_EDAP_NIU 171
344 #define SRST_PMU_I2C0 173
345 #define PRST_PMU_I2C0 174
346 #define PRST_PMU_GPIO0 175
347 #define PRST_PMU_INTMEM 176
348 #define PRST_PMU_PWM0 177
349 #define SRST_PMU_PWM0 178
350 #define PRST_PMU_GRF 179
351 #define SRST_PMU_NIU 180
352 #define SRST_PMU_PVTM 181
353 #define ARST_DSP_EDP_PERF 184
354 #define ARST_DSP_EPP_PERF 185
356 #endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */