2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
18 /* sclk gates (special clocks) */
19 #define SCLK_RTC32K 30
20 #define SCLK_SDMMC_EXT 31
26 #define SCLK_SARADC 37
33 #define SCLK_I2S1_OUT 44
34 #define SCLK_I2S2_OUT 45
36 #define SCLK_TIMER0 47
37 #define SCLK_TIMER1 48
38 #define SCLK_TIMER2 49
39 #define SCLK_TIMER3 50
40 #define SCLK_TIMER4 51
41 #define SCLK_TIMER5 52
43 #define SCLK_CIF_OUT 54
48 #define SCLK_CRYPTO 59
53 #define SCLK_DDRCLK 64
54 #define SCLK_VDEC_CABAC 65
55 #define SCLK_VDEC_CORE 66
56 #define SCLK_VENC_DSP 67
57 #define SCLK_VENC_CORE 68
59 #define SCLK_HDMI_SFC 70
60 #define SCLK_HDMI_CEC 71
61 #define SCLK_USB3_REF 72
62 #define SCLK_USB3_SUSPEND 73
63 #define SCLK_SDMMC_DRV 74
64 #define SCLK_SDIO_DRV 75
65 #define SCLK_EMMC_DRV 76
66 #define SCLK_SDMMC_EXT_DRV 77
67 #define SCLK_SDMMC_SAMPLE 78
68 #define SCLK_SDIO_SAMPLE 79
69 #define SCLK_EMMC_SAMPLE 80
70 #define SCLK_SDMMC_EXT_SAMPLE 81
72 #define SCLK_MAC2PHY_RXTX 83
73 #define SCLK_MAC2PHY_SRC 84
74 #define SCLK_MAC2PHY_REF 85
75 #define SCLK_MAC2PHY_OUT 86
76 #define SCLK_MAC2IO_RX 87
77 #define SCLK_MAC2IO_TX 88
78 #define SCLK_MAC2IO_REFOUT 89
79 #define SCLK_MAC2IO_REF 90
80 #define SCLK_MAC2IO_OUT 91
82 #define SCLK_HSADC_TSP 93
83 #define SCLK_USB3PHY_REF 94
84 #define SCLK_REF_USB3OTG 95
85 #define SCLK_USB3OTG_REF 96
86 #define SCLK_USB3OTG_SUSPEND 97
87 #define SCLK_REF_USB3OTG_SRC 98
88 #define SCLK_MAC2IO_SRC 99
92 #define DCLK_HDMIPHY 181
95 #define DCLK_LCDC_SRC 184
98 #define ACLK_AXISRAM 190
99 #define ACLK_VOP_PRE 191
100 #define ACLK_USB3OTG 192
101 #define ACLK_RGA_PRE 193
102 #define ACLK_DMAC 194
104 #define ACLK_BUS_PRE 196
105 #define ACLK_PERI_PRE 197
106 #define ACLK_RKVDEC_PRE 198
107 #define ACLK_RKVDEC 199
108 #define ACLK_RKVENC 200
109 #define ACLK_VPU_PRE 201
110 #define ACLK_VIO_PRE 202
114 #define ACLK_GMAC 206
115 #define ACLK_H265 207
116 #define ACLK_H264 208
117 #define ACLK_MAC2PHY 209
118 #define ACLK_MAC2IO 210
121 #define ACLK_PERI 213
125 #define ACLK_HDCP 217
128 #define PCLK_GPIO0 300
129 #define PCLK_GPIO1 301
130 #define PCLK_GPIO2 302
131 #define PCLK_GPIO3 303
133 #define PCLK_I2C0 305
134 #define PCLK_I2C1 306
135 #define PCLK_I2C2 307
136 #define PCLK_I2C3 308
138 #define PCLK_UART0 310
139 #define PCLK_UART1 311
140 #define PCLK_UART2 312
141 #define PCLK_TSADC 313
143 #define PCLK_TIMER 315
144 #define PCLK_BUS_PRE 316
145 #define PCLK_PERI_PRE 317
146 #define PCLK_HDMI_CTRL 318
147 #define PCLK_HDMI_PHY 319
148 #define PCLK_GMAC 320
149 #define PCLK_H265 321
150 #define PCLK_MAC2PHY 322
151 #define PCLK_MAC2IO 323
152 #define PCLK_USB3PHY_OTG 324
153 #define PCLK_USB3PHY_PIPE 325
154 #define PCLK_USB3_GRF 326
155 #define PCLK_USB2_GRF 327
156 #define PCLK_HDMIPHY 328
158 #define PCLK_PERI 330
159 #define PCLK_HDMI 331
160 #define PCLK_HDCP 332
162 #define PCLK_SARADC 334
165 #define HCLK_PERI 408
167 #define HCLK_GMAC 410
168 #define HCLK_I2S0_8CH 411
169 #define HCLK_I2S1_8CH 413
170 #define HCLK_I2S2_2CH 413
171 #define HCLK_SPDIF_8CH 414
173 #define HCLK_NANDC 416
174 #define HCLK_SDMMC 417
175 #define HCLK_SDIO 418
176 #define HCLK_EMMC 419
177 #define HCLK_SDMMC_EXT 420
178 #define HCLK_RKVDEC_PRE 421
179 #define HCLK_RKVDEC 422
180 #define HCLK_RKVENC 423
181 #define HCLK_VPU_PRE 424
182 #define HCLK_VIO_PRE 425
185 #define HCLK_BUS_PRE 428
186 #define HCLK_PERI_PRE 429
187 #define HCLK_H264 430
189 #define HCLK_OTG_PMU 432
191 #define HCLK_HOST0 434
192 #define HCLK_HOST0_ARB 435
193 #define HCLK_CRYPTO_MST 436
194 #define HCLK_CRYPTO_SLV 437
198 #define HCLK_HDCP 441
200 #define CLK_NR_CLKS (HCLK_HDCP + 1)
202 #define SCLK_MAC2IO 0
203 #define SCLK_MAC2PHY 1
205 #define CLKGRF_NR_CLKS (SCLK_MAC2PHY + 1)
207 /* soft-reset indices */
208 #define SRST_CORE0_PO 0
209 #define SRST_CORE1_PO 1
210 #define SRST_CORE2_PO 2
211 #define SRST_CORE3_PO 3
216 #define SRST_CORE0_DBG 8
217 #define SRST_CORE1_DBG 9
218 #define SRST_CORE2_DBG 10
219 #define SRST_CORE3_DBG 11
220 #define SRST_TOPDBG 12
221 #define SRST_CORE_NIU 13
222 #define SRST_STRC_A 14
225 #define SRST_A53_GIC 18
227 #define SRST_PMU_P 21
228 #define SRST_EFUSE 22
229 #define SRST_BUSSYS_H 23
230 #define SRST_BUSSYS_P 24
231 #define SRST_SPDIF 25
232 #define SRST_INTMEM 26
234 #define SRST_GPIO0 28
235 #define SRST_GPIO1 29
236 #define SRST_GPIO2 30
237 #define SRST_GPIO3 31
242 #define SRST_I2S0_H 35
243 #define SRST_I2S1_H 36
244 #define SRST_I2S2_H 37
245 #define SRST_UART0 38
246 #define SRST_UART1 39
247 #define SRST_UART2 40
248 #define SRST_UART0_P 41
249 #define SRST_UART1_P 42
250 #define SRST_UART2_P 43
256 #define SRST_I2C0_P 48
257 #define SRST_I2C1_P 49
258 #define SRST_I2C2_P 50
259 #define SRST_I2C3_P 51
260 #define SRST_EFUSE_SE_P 52
261 #define SRST_EFUSE_NS_P 53
263 #define SRST_PWM0_P 55
265 #define SRST_TSP_A 57
266 #define SRST_TSP_H 58
268 #define SRST_TSP_HSADC 60
269 #define SRST_DCF_A 61
270 #define SRST_DCF_P 62
274 #define SRST_TSADC 66
275 #define SRST_TSADC_P 67
276 #define SRST_CRYPTO 68
279 #define SRST_USB_GRF 71
280 #define SRST_TIMER_6CH_P 72
281 #define SRST_TIMER0 73
282 #define SRST_TIMER1 74
283 #define SRST_TIMER2 75
284 #define SRST_TIMER3 76
285 #define SRST_TIMER4 77
286 #define SRST_TIMER5 78
287 #define SRST_USB3GRF 79
289 #define SRST_PHYNIU 80
290 #define SRST_HDMIPHY 81
292 #define SRST_ACODEC_p 83
293 #define SRST_SARADC 85
294 #define SRST_SARADC_P 86
295 #define SRST_GRF_DDR 87
296 #define SRST_DFIMON 88
298 #define SRST_DDRMSCH 91
299 #define SRST_DDRCTRL 92
300 #define SRST_DDRCTRL_P 93
301 #define SRST_DDRPHY 94
302 #define SRST_DDRPHY_P 95
304 #define SRST_GMAC_NIU_A 96
305 #define SRST_GMAC_NIU_P 97
306 #define SRST_GMAC2PHY_A 98
307 #define SRST_GMAC2IO_A 99
308 #define SRST_MACPHY 100
309 #define SRST_OTP_PHY 101
310 #define SRST_GPU_A 102
311 #define SRST_GPU_NIU_A 103
312 #define SRST_SDMMCEXT 104
313 #define SRST_PERIPH_NIU_A 105
314 #define SRST_PERIHP_NIU_H 106
315 #define SRST_PERIHP_P 107
316 #define SRST_PERIPHSYS_H 108
317 #define SRST_MMC0 109
318 #define SRST_SDIO 110
319 #define SRST_EMMC 111
321 #define SRST_USB2OTG_H 112
322 #define SRST_USB2OTG 113
323 #define SRST_USB2OTG_ADP 114
324 #define SRST_USB2HOST_H 115
325 #define SRST_USB2HOST_ARB 116
326 #define SRST_USB2HOST_AUX 117
327 #define SRST_USB2HOST_EHCIPHY 118
328 #define SRST_USB2HOST_UTMI 119
329 #define SRST_USB3OTG 120
330 #define SRST_USBPOR 121
331 #define SRST_USB2OTG_UTMI 122
332 #define SRST_USB2HOST_PHY_UTMI 123
333 #define SRST_USB3OTG_UTMI 124
334 #define SRST_USB3PHY_U2 125
335 #define SRST_USB3PHY_U3 126
336 #define SRST_USB3PHY_PIPE 127
338 #define SRST_VIO_A 128
339 #define SRST_VIO_BUS_H 129
340 #define SRST_VIO_H2P_H 130
341 #define SRST_VIO_ARBI_H 131
342 #define SRST_VOP_NIU_A 132
343 #define SRST_VOP_A 133
344 #define SRST_VOP_H 134
345 #define SRST_VOP_D 135
347 #define SRST_RGA_NIU_A 137
348 #define SRST_RGA_A 138
349 #define SRST_RGA_H 139
350 #define SRST_IEP_A 140
351 #define SRST_IEP_H 141
352 #define SRST_HDMI 142
353 #define SRST_HDMI_P 143
355 #define SRST_HDCP_A 144
356 #define SRST_HDCP 145
357 #define SRST_HDCP_H 146
358 #define SRST_CIF_A 147
359 #define SRST_CIF_H 148
360 #define SRST_CIF_P 149
361 #define SRST_OTP_P 150
362 #define SRST_OTP_SBPI 151
363 #define SRST_OTP_USER 152
364 #define SRST_DDRCTRL_A 153
365 #define SRST_DDRSTDY_P 154
366 #define SRST_DDRSTDY 155
367 #define SRST_PDM_H 156
369 #define SRST_USB3PHY_OTG_P 158
370 #define SRST_USB3PHY_PIPE_P 159
372 #define SRST_VCODEC_A 160
373 #define SRST_VCODEC_NIU_A 161
374 #define SRST_VCODEC_H 162
375 #define SRST_VCODEC_NIU_H 163
376 #define SRST_VDEC_A 164
377 #define SRST_VDEC_NIU_A 165
378 #define SRST_VDEC_H 166
379 #define SRST_VDEC_NIU_H 167
380 #define SRST_VDEC_CORE 168
381 #define SRST_VDEC_CABAC 169
382 #define SRST_DDRPHYDIV 175
384 #define SRST_RKVENC_NIU_A 176
385 #define SRST_RKVENC_NIU_H 177
386 #define SRST_RKVENC_H265_A 178
387 #define SRST_RKVENC_H265_P 179
388 #define SRST_RKVENC_H265_CORE 180
389 #define SRST_RKVENC_H265_DSP 181
390 #define SRST_RKVENC_H264_A 182
391 #define SRST_RKVENC_H264_H 183
392 #define SRST_RKVENC_INTMEM 184