include/dt-bindings/clock/r9a07g044-cpg.h

   1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2  *
   3  * Copyright (C) 2021 Renesas Electronics Corp.
   4  */
   5 #ifndef __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
   6 #define __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
   7
   8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
   9
  10 /* R9A07G044 CPG Core Clocks */
  11 #define R9A07G044_CLK_I                 0
  12 #define R9A07G044_CLK_I2                1
  13 #define R9A07G044_CLK_G                 2
  14 #define R9A07G044_CLK_S0                3
  15 #define R9A07G044_CLK_S1                4
  16 #define R9A07G044_CLK_SPI0              5
  17 #define R9A07G044_CLK_SPI1              6
  18 #define R9A07G044_CLK_SD0               7
  19 #define R9A07G044_CLK_SD1               8
  20 #define R9A07G044_CLK_M0                9
  21 #define R9A07G044_CLK_M1                10
  22 #define R9A07G044_CLK_M2                11
  23 #define R9A07G044_CLK_M3                12
  24 #define R9A07G044_CLK_M4                13
  25 #define R9A07G044_CLK_HP                14
  26 #define R9A07G044_CLK_TSU               15
  27 #define R9A07G044_CLK_ZT                16
  28 #define R9A07G044_CLK_P0                17
  29 #define R9A07G044_CLK_P1                18
  30 #define R9A07G044_CLK_P2                19
  31 #define R9A07G044_CLK_AT                20
  32 #define R9A07G044_OSCCLK                21
  33
  34 /* R9A07G044 Module Clocks */
  35 #define R9A07G044_CLK_GIC600            0
  36 #define R9A07G044_CLK_IA55              1
  37 #define R9A07G044_CLK_SYC               2
  38 #define R9A07G044_CLK_DMAC              3
  39 #define R9A07G044_CLK_SYSC              4
  40 #define R9A07G044_CLK_MTU               5
  41 #define R9A07G044_CLK_GPT               6
  42 #define R9A07G044_CLK_ETH0              7
  43 #define R9A07G044_CLK_ETH1              8
  44 #define R9A07G044_CLK_I2C0              9
  45 #define R9A07G044_CLK_I2C1              10
  46 #define R9A07G044_CLK_I2C2              11
  47 #define R9A07G044_CLK_I2C3              12
  48 #define R9A07G044_CLK_SCIF0             13
  49 #define R9A07G044_CLK_SCIF1             14
  50 #define R9A07G044_CLK_SCIF2             15
  51 #define R9A07G044_CLK_SCIF3             16
  52 #define R9A07G044_CLK_SCIF4             17
  53 #define R9A07G044_CLK_SCI0              18
  54 #define R9A07G044_CLK_SCI1              19
  55 #define R9A07G044_CLK_GPIO              20
  56 #define R9A07G044_CLK_SDHI0             21
  57 #define R9A07G044_CLK_SDHI1             22
  58 #define R9A07G044_CLK_USB0              23
  59 #define R9A07G044_CLK_USB1              24
  60 #define R9A07G044_CLK_CANFD             25
  61 #define R9A07G044_CLK_SSI0              26
  62 #define R9A07G044_CLK_SSI1              27
  63 #define R9A07G044_CLK_SSI2              28
  64 #define R9A07G044_CLK_SSI3              29
  65 #define R9A07G044_CLK_MHU               30
  66 #define R9A07G044_CLK_OSTM0             31
  67 #define R9A07G044_CLK_OSTM1             32
  68 #define R9A07G044_CLK_OSTM2             33
  69 #define R9A07G044_CLK_WDT0              34
  70 #define R9A07G044_CLK_WDT1              35
  71 #define R9A07G044_CLK_WDT2              36
  72 #define R9A07G044_CLK_WDT_PON           37
  73 #define R9A07G044_CLK_GPU               38
  74 #define R9A07G044_CLK_ISU               39
  75 #define R9A07G044_CLK_H264              40
  76 #define R9A07G044_CLK_CRU               41
  77 #define R9A07G044_CLK_MIPI_DSI          42
  78 #define R9A07G044_CLK_LCDC              43
  79 #define R9A07G044_CLK_SRC               44
  80 #define R9A07G044_CLK_RSPI0             45
  81 #define R9A07G044_CLK_RSPI1             46
  82 #define R9A07G044_CLK_RSPI2             47
  83 #define R9A07G044_CLK_ADC               48
  84 #define R9A07G044_CLK_TSU_PCLK          49
  85 #define R9A07G044_CLK_SPI               50
  86 #define R9A07G044_CLK_MIPI_DSI_V        51
  87 #define R9A07G044_CLK_MIPI_DSI_PIN      52
  88
  89 #endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */