9066213f5a96471aff139ba4b45a002c42a07c4b
[platform/adaptation/renesas_rcar/renesas_kernel.git] / include / dt-bindings / clock / r8a7794-clock.h
1 /*
2  * Copyright (C) 2014 Renesas Electronics Corporation
3  * Copyright 2013 Ideas On Board SPRL
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation; either version 2 of the License, or
8  * (at your option) any later version.
9  */
10
11 #ifndef __DT_BINDINGS_CLOCK_R8A7794_H__
12 #define __DT_BINDINGS_CLOCK_R8A7794_H__
13
14 /* CPG */
15 #define R8A7794_CLK_MAIN                0
16 #define R8A7794_CLK_PLL0                1
17 #define R8A7794_CLK_PLL1                2
18 #define R8A7794_CLK_PLL3                3
19 #define R8A7794_CLK_LB                  4
20 #define R8A7794_CLK_QSPI                5
21 #define R8A7794_CLK_SDH                 6
22 #define R8A7794_CLK_SD0                 7
23 #define R8A7794_CLK_Z                   8
24
25 /* MSTP0 */
26 #define R8A7794_CLK_MSIOF0              0
27
28 /* MSTP1 */
29 #define R8A7794_CLK_TMU1                11
30 #define R8A7794_CLK_3DG                 12
31 #define R8A7794_CLK_TMU3                21
32 #define R8A7794_CLK_TMU2                22
33 #define R8A7794_CLK_CMT0                24
34 #define R8A7794_CLK_TMU0                25
35
36 /* MSTP2 */
37 #define R8A7794_CLK_SCIFA2              2
38 #define R8A7794_CLK_SCIFA1              3
39 #define R8A7794_CLK_SCIFA0              4
40 #define R8A7794_CLK_MSIOF2              5
41 #define R8A7794_CLK_SCIFB0              6
42 #define R8A7794_CLK_SCIFB1              7
43 #define R8A7794_CLK_MSIOF1              8
44 #define R8A7794_CLK_SCIFB2              16
45
46 /* MSTP3 */
47 #define R8A7794_CLK_CMT1                29
48
49 /* MSTP5 */
50 #define R8A7794_CLK_THERMAL             22
51 #define R8A7794_CLK_PWM                 23
52
53 /* MSTP7 */
54 #define R8A7794_CLK_HSCIF2              13
55 #define R8A7794_CLK_SCIF5               14
56 #define R8A7794_CLK_SCIF4               15
57 #define R8A7794_CLK_HSCIF1              16
58 #define R8A7794_CLK_HSCIF0              17
59 #define R8A7794_CLK_SCIF3               18
60 #define R8A7794_CLK_SCIF2               19
61 #define R8A7794_CLK_SCIF1               20
62 #define R8A7794_CLK_SCIF0               21
63
64 /* MSTP8 */
65 #define R8A7794_CLK_VIN1                10
66 #define R8A7794_CLK_VIN0                11
67 #define R8A7794_CLK_ETHER               13
68
69 /* MSTP9 */
70 #define R8A7794_CLK_GPIO6               5
71 #define R8A7794_CLK_GPIO5               7
72 #define R8A7794_CLK_GPIO4               8
73 #define R8A7794_CLK_GPIO3               9
74 #define R8A7794_CLK_GPIO2               10
75 #define R8A7794_CLK_GPIO1               11
76 #define R8A7794_CLK_GPIO0               12
77
78 /* MSTP11 */
79 #define R8A7794_CLK_SCIFA3              6
80 #define R8A7794_CLK_SCIFA4              7
81 #define R8A7794_CLK_SCIFA5              8
82
83 #endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */